Introduction to Bipolar Junction Transistors (BJTs) Mugisha Omary Introduction to Bipolar Junction Transistors (BJTs) Laboratory Report for EENG 3306 College of Engineering and Computer Science Department of Electrical Engineering University of Texas at Tyler Houston, TX December 8, 2014 Mugisha Omary Group Members Hamza Ahmad Shamir Mohammed I. Project description The purpose of this lab is to take measurement of the common-emitter characteristics (collector current IC vs collector-to-emitter voltage VCE of small-signal NPN and PNP bipolar transistors and also simulate IC vs VCE characteristics of 2N4401 and 2N3906 transistors. A BJT is a semiconductor device that uses a small current to control a larger current. This property makes it essentially a current amplifier. In this lab the student will build a simple test circuit to evaluate a transistor’s current and voltage relationships and then use this data to determine the transistors DC value and plot the collector characteristic curve. II. Theoretical background A BJT is a three terminal two – junction semiconductor device in which the conduction is due to both the charge carrier. Hence it is a bipolar device and it amplifier the sine waveform as they are transferred from input to output. BJT is classified into two types – NPN or PNP. A NPN transistor consists of two N types in between which a layer of P is sandwiched. The transistor consists of three terminal emitter, collector and base. The emitter layer is the source of the charge carriers and it is heartily doped with a moderate cross sectional area. The collector collects the charge carries and hence moderate doping and large cross sectional area. The base region acts a path for the movement of the charge carriers. In order to reduce the recombination of holes and electrons the base region is lightly doped and is of hollow cross sectional area. Normally the transistor operates with the EB junction forward biased. In transistor, the current is same in both junctions, which indicates that there is a transfer of resistance between the two junctions. One to this fact the transistor is known as transfer resistance of transistor. The symbol of an NPN BJT. The symbol is "not pointing in." The symbol of a PNP BJT. The symbol "points inproudly." When a transistor’s base current (IB) is set to a certain value and left unchanged while the collector current is swept through a range of values and IC and VCE are recorded and then graphed, a collector characteristic curve is produced for that particular IB. If IB is now changed, and again the collector current is swept through a range of values, and IC and VCE are plotted, another collector characteristic curve for this different IB value is produced. Repeating this process for several IB values results in a family of curves referred to as the transistors collector characteristic curves. Figure 2 shows the characteristics for a notional transistor. Figure 1. Transistor.

1. Introduction to Bipolar Junction Transistors (BJTs)
Mugisha Omary
Introduction to Bipolar Junction Transistors (BJTs)
Laboratory Report for EENG 3306
College of Engineering and Computer Science
Department of Electrical Engineering
University of Texas at Tyler
Houston, TX
December 8, 2014
Mugisha Omary
Group Members
Hamza Ahmad
Shamir Mohammed
I. Project description
The purpose of this lab is to take measurement of the common-
emitter characteristics (collector current IC vs collector-to-
emitter voltage VCE of small-signal NPN and PNP bipolar
transistors and also simulate IC vs VCE characteristics of
2N4401 and 2N3906 transistors.
A BJT is a semiconductor device that uses a small current to
control a larger current. This property makes it essentially a
current amplifier. In this lab the student will build a simple test
circuit to evaluate a transistor’s current and voltage

2. relationships and then use this data to determine the transistors
.
II. Theoretical background
A BJT is a three terminal two – junction semiconductor device
in which the
conduction is due to both the charge carrier. Hence it is a
bipolar device and it
amplifier the sine waveform as they are transferred from input
to output. BJT is
classified into two types – NPN or PNP. A NPN transistor
consists of two N
types in between which a layer of P is sandwiched. The
transistor consists of
three terminal emitter, collector and base. The emitter layer is
the source of the
charge carriers and it is heartily doped with a moderate cross
sectional area.
The collector collects the charge carries and hence moderate
doping and large
cross sectional area. The base region acts a path for the
movement of the
charge carriers. In order to reduce the recombination of holes
and electrons the
base region is lightly doped and is of hollow cross sectional

3. area. Normally the
transistor operates with the EB junction forward biased. In
transistor, the current is same in both junctions, which indicates
that there is a transfer of resistance between the two junctions.
One to this fact the transistor is known as transfer resistance of
transistor.
The symbol of an NPN BJT. The symbol is "not pointing in."
The symbol of a PNP BJT. The symbol "points inproudly."
When a transistor’s base current (IB) is set to a certain value
and left unchanged while the collector current is swept through
a range of values and IC and VCE are recorded and then
graphed, a collector characteristic curve is produced for that
particular IB. If IB is now changed, and again the collector
current is swept through a range of values, and IC and VCE are
plotted, another collector characteristic curve for this different
IB value is produced. Repeating this process for several IB
values results in a family of curves referred to as the transistors
collector characteristic curves. Figure 2 shows the
characteristics for a notional transistor.
Figure 1. Transistor Collector Characteristic Curves
The flow of the current in the circuit is shown below.
Figure 1- Transistor Current
III. Methods and materials
Equipment
1- Curve Tracer
1- 2N4401 Transistor
1- 2N3906 Transistor
1- Oscilloscope

4. 1- Power Supply
1-Breadboard
Wires bundles
Experimental procedure
We used the curve tracer and connected it to 2N4401 installed
on the breadboard for measuring common-emitter IC vs VCE
characteristics of the NPN transistor, secondly we used the
circuit with the oscilloscope to measure the IC vs VCE
characteristics of the 2N4401 transistor for base currents from
0 to 100µA in increments of 20µA and then we imported the
results in excel and produced a graph as shown in figure 5 of
the lab handout.
For the PNP common emitter , we used the circuit with the
oscilloscope to measure the IC vs VCE characteristics of the
2N3906 transistor for base currents from 0 to -100µA in
increments of -20µA, Adjusted the amplitude of the triangle-
wave generator to obtain a minimal VCE of at least -20V. We
imported these results into excel and produced a graph similar
to that shown in figure 5 of the lab handout.
Figure 2-Oscilloscope connections to the curve tracer
Figure 3- Signal generator connections to the curve tracer
Figure 4- Connections for an NPN BJT
Figure 5- Configuration and connections for a PNP transistor
IV. Results
Measurement of NPN common-emitter graph created using excel
is shown below

5. Figure 6-NPN graph
To determine the current gain β (ratio of IC to IB ) at VCE=5V
and IB=40µA
β=IC/IB=7mA/40µA, β=175
At VCE=15V, IB=80µA, IC=17mA
β=17mA/80µA, β=212.5
Early voltage of the transistor is
Measurement of PNP common-emitter graph created using excel
is shown below
Current gain at VCE= -5v and IB= 40µA, IC= -7mA
β= -7mA/40µA=-175
Current gain at VCE=-15V, IB=80µA, IC= -17mA
β=IC/IB, β=-17mA/80µA, β=-212.5
The Early voltage of the transistor
V. Discussion
A precision half-wave rectifier and voltage amplifier with a
voltage gain of ±10V/V and an output range of ±23V and
±30mA. This amplifier is driven by an external signal generator
and provides a unipolar voltage VCE(positive-going for NPN or
negative-going for PNP, selectable with the Polarity switch) to
the transistor under test. The external signal generator is set to
produce a triangle wave with no dc offset at a frequency of
50Hz. The amplitude of the triangle wave determines the
maximal value of |VCE|.
A transresistance amplifier whose output voltage is proportional
to IC with sensitivity of −5mA/V.

6. A voltage-controlled current source (VCCS) that provides base
current IBto the transistor under test. The transconductance of
the VCCS is ±50µA/V. The polarity of the base current is
determined by the Polarity switch (positive for NPN, negative
for PNP).
VI. Conclusions
A bipolar junction transistor (BJT) is a transistor that relies on
the contact of two types of semiconductor for its operation.
After performing this lab and constructing the circuit in the
laboratory procedure we were able to measure IC vs VCE for an
NPN transistor and we were able to simulate the characteristics
of the 2N4401 NPN BJTs. When the experiment was repeated
for the PNP common-emitter the same results were obtained
except that the graph is in the third quadrant because the IC and
VCE have negative values. At any given base current IB , the
graphs of IC vs VCE were plotted and they all appear to have
the same shape, meaning as VCE increases , IC also increases.
6
Lab 12 – Latches and Flip-Flops
Mugisha Omary
Lab 12 – Latches and Flip-Flops
Laboratory Report for EENG 3302
College of Engineering and Computer Science
Department of Electrical Engineering
University of Texas at Tyler

7. Houston, Texas
December 10, 2013
Mugisha Omary
Group Members
Jonathan Vidana
Hamza Ahmad
Shamir Mohammed
Abstract
The purpose of this experiment is to be able to understand how
latches operate and their similarities and differences to flip-
flops by using NAND gates.
I. Project description
The latch is a digital memory circuit that can remain in the state
in which it was set even after the input signals are removed.
Latches are basically similar to flip-flops because they are bi-

8. stable devices that can reside in either of two states by virtue of
a feedback arrangement, in which the outputs are connected
back to the opposite inputs. The main difference between
latches and flip-flops is in the method used for changing their
state. Latches are level-triggered and flip-flops are edge-
triggered.
After completion of this experiment, we will be able to
understand the operation of laches and similarities and
differences to flip-flops.
II. Theoretical background
When the clock is high the input D propogates to the output Q
as it is and when the clock is low the output is held(irrespective
of the changes in input D).This definition indicates that D latch
can be implemented as a multiplexer with clock signal as the
select input of multiplexer. Applying analogy , we realise that
when clock=1 the input to the CMOS pass transistor should be
D and when clock=0 the input to the pass transistor should be
value of D just before the transition of clock from 1 to 0.To
obtain the value of D just before transition a buffer is
needed.The final design is given below:
Figure 1-D latch
In digital systems, the types of circuits that can retain previous
input levels after original inputs are removed are called
sequential circuits.
The set-reset (S-R) latch has two input, a SET input and a
RESET input, and two outputs, Q and Q. When the Q output is a
1, the latch is SET; when the Q output is a 0, the latch is
RESET.
When an active-LOW input is applied to the SET input, the
latch goes to the SET (Q = 1) condition and remains that way
until an active-LOW signal is applied to the RESET input. Then
it goes to the RESET (Q = 0) condition.
An invalid condition occurs if active-LOW inputs are applied at

9. the same time to both the SET and the RESET inputs. During
the time both the inputs are active, the Q output is 1 and
the output is a 1 (clearly an invalid condition). When both
inputs go HIGH (inactive), the S-R latch stays latched in one
state or the other. However, the exact state is not easily
predictable. The final state of the latch depends on which input
was active last as two inputs went to the inactive state.
Many applications require that the latch be enabled or gated by
another source, called a clock. A gated S-R latch does not
accept the input condition until the gate input is HIGH, and the
required transitions will take place.
Figure 2- A gated S-R latch
The gated D-latch has one data input and a clock input. The
addition of the inverter causes the RESET input to be the
opposite the SET input. If a 1 is present on the D input and the
clock is HIGH (gate enabled), then the latch is SET. If a 0 is
present on the D input while the clock is HIGH, then the latch
will be RESET. While the clock is HIGH, the outputs can
change if the inputs change. Once the clock goes LOW,
however, the output will not change. Notice that the inverter
prevents the invalid state that was possible in the S-R latches.
A major disadvantage of the 7475 is that when the clock is
HIGH (enabled), the output changes with any changes of the
input. Thus, there is no isolation between the input and output
during the HIGH portion of the clock pulse.
Figure 3- A gated D latch
Flip-flops are synchronous bi-stable devices. In this case
synchronous means that the output changes states only at the
specified point on a triggering input called the clock; that is,
changes in the output occur in synchronization with the clock.
An edge triggered flip-flop changes state either at the positive
edge (rising edge) or at the negative edge (falling edge) of the
clock pulse and is sensitive to its inputs only at this transition
of the clock. An edge-triggered flip-flop provides the desired

10. isolation between the input and output.
The preset () and clear () (active-LOW) inputs allow the flip-
flop to be preset or cleared whether the clock is activated or
not. These types of inputs are called asynchronous inputs.
The functioning of the J-K flip-flop is identical to that of the S-
R flip-flop in the SET, RESET, and no-change conditions of
operation. The difference is that the J-K flip-flop has no invalid
state, as does the S-R flip-flop. The J-K flip-flop overcomes
this condition by cross-connecting the outputs back to the
inputs. This connection causes the flip-flop to toggle (change to
the opposite state) when the J and K inputs are both active-
HIGH, thus eliminating the invalid state.
Figure 4- An Edge-Triggered S-R Flip-Flop
The operation of the 7474 DUAL D-Type Positive Edge-
Triggered Flip-Flop is as follows:
The 7474 contain two identical D-type positive edge-triggered
flip-flops, each with active-LOW preset (PRE) and clear (CLR)
inputs. When A goes HIGH, QA goes HIGH on the rising edge
of A. (Notice that the D input of the flip-flop, A is always a 1).
After QA goes to a 1, the D input of the flip-flop, B is a 1, and
when the next positive edge of the clock occurs, QB goes
HIGH. When QB goes HIGH, then the QB output goes LOW and
immediately resets QA back to 0. Because the D input of the
flip-flop, B is now LOW, QB will go LOW on the next clock
pulse. As you can see, QB was ON for exactly one clock period
regardless of how long you kept switch A on.
Figure 5- An Edge-Triggered D Flip-Flop
The operation of the 74ALS112A Dual J-K Negative Edge-
Triggered Flip-Flop is as follows:
The 74ALS112A consist of two identical negative edge-
triggered J-K flip-flops with active-LOW PRE and CLR inputs.
First, operate the CLR and PRE, and verify that the Q
and Q outputs respond properly.
Before performing the clocked portion of this experiment, clear

11. the flip-flop, and then place the () and () inputs in the inactive
states (both HIGH). Notice that the J-K flip-flop toggles when
both the J and K inputs are HIGH and the clock is pulsed. Also
notice that you cannot change the output of the flip-flop by
changing the state of the J and K inputs while the clock is
HIGH. Observe that the output changes on the negative edge (on
the HIGH-to-LOW transmission) of the clock pulse.
Figure 6- An Edge Triggered J-K Flip-Flop
III. Methods and materials
Equipment
· Texas Instruments 7400 NAND gate
· Texas Instruments 7474 dual D-type flip-flop
· Texas Instruments 7475 gated D latch
· Texas Instruments 74ALS112A dual J-K flip-flop
· Twin Industries TW-E41-1060 Breadboard
· Oscilloscope
· Power Supply
Procedure
We installed the integrated circuit on the breadboard as shown
and operated the data switches for each exercise below and
check the results by verified the data expected in the truth table
to make sure they matched with those obtained experimentally.
IV. Results
Table 1- Truth for a S-R latch
S
R
Q
Q’

12. 0
0
Q
Q’
0
1
0
1
1
0
1
0
1
1
Invalid
Invalid
Figure 7- A gated S-R latch
Figure 8- A gated S-R latch
Figure 9-S-R latch waveforms
Table 2- Truth table for Gated D Latch
E
D
Q
Q’
1
0

13. 0
1
1
1
1
0
0
X
Q
Q’
Figure 10- A gated D-latch
Figure 11- A gated D-latch waveform
Table 3- Truth table for D Flip Flop with Edge- Triggered
Clock
D
Q
Rising Edge
0
0
Rising Edge
1
1
Non-Rising Edge
X
Q

14. Figure 12- An Edge-Triggered D Flip-Flop
Table 4-Truth table for D Flip Flop
D
Q (current state)
Q+ (next state)
Operation
0
0
0
Reset
0
1
0
Reset
1
0
1
Set
1
1
1
Set
Figure 13- D Flip Flop

15. J
K
Q (current state)
Q+ (next state)
Operation
0
0
0
0
No change
0
0
1
1
No change
0
1
0
0
Reset
0
1
1
0
Reset
1
0
0
1
Set
1
0
1

16. 1
Set
1
1
0
1
Toggle
1
1
1
0
Toggle
Truth table for a J-K flips flop.
Figure 14-J-K flip-flop using the 74ALS112A
Figure 15- J-K Flip Flop
Discussion
Latches are circuits that store single bits. One basic type of
latch is the RS-latch which has two inputs, labeled Set and
Reset. These two inputs, which are typically labeled S and R,
provide a means for changing the state, Q, of the circuit. When
both inputs, R and S, are equal to 0 the latch maintains its
existing state. When R=0 and S=1 the latch is said to be in the
Set state. In this case, the circuit output is 1. When R=1 and
S=0 the latch is said to be in the reset state and the circuit
output is 0. Finally, if R=S=1 the circuit output is going to be 0.
This is considered to be an illegal state for an RS-latch. A flip-
flop is a basic sequential circuit element that stores one bit. A
flip-flop changes its output state at the edge of a controlling
clock signal. When a set of n flip-flops is used to store n bits of

17. information, we refer to these flip-flops as a register. A
common clock is used for each flip-flop in a register.
CONCLUSION
Latches and flip flops have digital memory circuits that can
remain in the state in which they were set and analyzed. Latches
act as bi-stable devices that can reside in either of two states by
feedback arrangement, where the outputs are connected back to
the opposite inputs. The main difference between latches and
flip-flops is in the method used for changing their state. Latches
are level-triggered and flip-flops are edge-triggered.
11