A Distributed Shared Memory (DSM) system provides a logical abstraction of shared memory built using interconnected nodes with distributed physical memories. There are hardware, software, and hybrid DSM approaches. DSM offers simple abstraction, improved portability, potential performance gains, large unified memory space, and better performance than message passing in some applications. Consistency protocols ensure shared data coherency across distributed memories according to the memory consistency model.

2. Basic Concepts Of DSM:
 A DSM system provides a logical abstraction
of shared memory which is built using a set
of interconnected nodes having physically
distributed memories.

3. Types of DSMs
 Hardware level DSM
 Software level DSM
 Hybrid level DSM

4. Advantages of DSM
 Simple abstraction
 Improved portability of distributed
application programs
 Provides better performance in some
applications
 Large memory space at no extra cost
 Better than message passing systems

5. Comparison of IPC
paradigms
 DFS
 Single shared address space
 Communicate, synchronize using load / store
 Can support message passing
 Message Passing
 Send / Receive
 Communication + synchronization
 Can support shared memory

6. Hardware architectures
 On chip memory
 Bus based multiprocessor
 Ring based multiprocessor
 Switched multiprocessor

7. On chip memory
In this CPU portion of the chip has a address and data lines that directly
connect to the memory portion.
Such chips are used in cars appliances and even toys

8. Bus based multiprocessor
All CPUs connected to one bus (backplane)
Memory and peripherals are accessed via shared bus. System looks the
same from any processor.

9. Consistency protocols

10. Ring DSM architecture
 Shred memory :
 Private areas
 Shared areas

11. (Ring) Memnet: Node memory

12. Switched multiprocessor:
 Multiple clusters interconnected by a bus offer better
scalability
 Example : Dash system

13. NUMA Multiprocessor
 Non-uniform memory access (NUMA) is a
computer memory design used multiprocessing,
where the memory access time depends on the
memory location relative to the processor.
 Under NUMA, a processor can access its own
local memory faster than non-local memory.
 The benefits of NUMA are limited to particular
workloads, notably on servers where the data is
often associated strongly with certain tasks or
users.

14. UMA Multiprocessor
 Uniform memory access (UMA) is a shared memory
architecture used in parallel computers. All the processors
in the UMA model share the physical memory uniformly.
 In a UMA architecture, access time to a memory location
is independent of which processor makes the request or
which memory chip contains the transferred data.
 Uniform memory access computer architectures are often
contrasted with non-uniform memory access (NUMA)
architectures.
 In the UMA architecture, each processor may use a
private cache. Peripherals are also shared in some
fashion.
 The UMA model is suitable for general purpose and time
sharing applications by multiple users. It can be used to
speed up the execution of a single large program in time-
critical applications.

15. D/f bw two Multiprocessor:
BUS BASED
MULTIPROCCESORS
RING BASED
MULTIPROCCESORS
 They are tightly coupled
with the CPU’S
normally in a single
rack.
 It has separate global
memory
 Machines here can be
much more loosely
coupled and this loose
coupling can affect their
performance.
 It has no separate
global memory.

17. DSM design issues
 Granularity of sharing
 Structure of data
 Consistency models
 Coherence protocols

18. Granularity
 False sharing
 Thrashing

19. Thrashing:
 False sharing
 Techniques to reduce
thrashing:
 Application controlled lock
 Pin the block to a node for
specific time
 Customize algorithm to
shared data usage pattern

20. DSM structure
 Organization of data items in the shared
memory

21. Consistency models
//Important.
 Refers to how recent the shared memory updates
are visible to all the other processes running on
different machines

22. Strict consistency
 Strongest form of consistency.
 All write operations are visible to all processes.

23. Sequential consistency
 All processors in the system observe the same
ordering of reads and writes which are issued in
sequence by the individual processors

24. Causal consistency
 Weakening of sequential consistency for
better concurrency
 Causally related operation is the one which
has influenced the other operation

25. PRAM consistency
 Pipelined Random Access Memory consistency
 Write operations performed by different processes may
be seen by different processes in different orders
 All write operations of a single process are pipelined
 Simple, easy to implement and has good performance.

26. Processor consistency
 Adheres to the PRAM consistency
 Constraint on memory coherence
 Order in which the memory operations
are seen by two processors need not be
identical, but the order of writes issued
by each processor must be preserved

27. Weak consistency
 Use a special variable called the
synchronization variable.
 Very difficult to show and keep track of the changes at
time to time.

28. Properties of the weak
consistency model:
 Access to synchronization variables is
sequentially consistent.
 Only when all previous writes are
completed everywhere, access to
synchronizations variable is allowed.
 Until all previous accesses to
synchronization variables are performed,
no read write data access operations will
be allowed.

29. Release consistency
 Uses two synchronization variables (Acquire and
Release)
 Release consistency model uses synchronization
mechanism based on barriers.

30. Eager Release
Consistency(ERC)

31. Lazy Release
Consistency(LRC)

32. Entry consistency
• Use acquire and release at the start and
end of each critical section, respectively.
• Each ordinary shared variable is
associated with some synchronization
variable such as a lock or barrier.
• Entry consistency (EC) is similar to LRC
but more relaxed; shared data is explicitly
associated with synchronization primitives
and is made consistent when such an
operation is performed

33. Scope consistency
 A scope is a limited view of memory with
respect to which memory references are
performed

34. Comparison of consistency
models-1
 Most common: sequential consistency
model .

35. Comparison of Consistency
models-2
 Based on efficiency and programmability

36. Coherence protocols
 Specifies how the rules set by the
memory consistency model are to be
implemented

37. Coherence algorithms
 Maintain consistency among replicas

38. Multiple Reader/ Multiple Writer
algorithm
 Uses twin and diff creation technique

39. Write Protocols for consistency
 Write Update (WU)
 Write Invalidate (WI) protocols

40. Replication versus migration
strategies
 Replication strategy:
 No replication
 Replication
 Migration strategy
 No migration
 Migration
 Non Replicated and Non
Migrating Block- NRNMB.
 Non Replicated, Migrating
Block- NRMB.
 Replicated, Migrating Block-
RMB.
 Replicated Non Migrating
Block-RNMB.

41. Case studies
 Munin
 Linda
 Midway

42. Munin

43. Linda-1

44. Linda-2

45. Linda-3

46. D/F Munin and Midway: