1. INTRODUCTION TO
VLSI DESIGN
By:
Zeeshan Ali Haq
Assistant Professor,
Jamia Hamdard

2. Topics to be covered
• Evolution of VLSI
• MOS Transistor theory
• MOS Structure
• Threshold Voltage

3. Evolution of VLSI
The first “generation” of computers were relied on vacuum tube devices, after
this discrete semiconductor devices, followed by integrated circuits have been
evolved. The first integrated circuit was manufactured independently by two
scientists: Jack and Kilby of Texas Instruments in 1959. The first IC had small
number of devices on a single chip then diodes, transistors, resistors and
capacitors, made it possible to fabricate one or more logic gates on a single
device. Digital integrated circuits are classified according to the number of
transistors integrated on a single chip. The different technologies involved in
digital integrated circuits are as follows.

4. EvolutionContd
Late 40s: Transistors invented at Bell Labs
Late 50s: first integrated circuits
Early 60s: Small Scale Integration (SSI), 10s of transistors on a chip
Late 60s: Medium Scale Integration (MSI), 100s of transistors on a
chip
Early 70s: Large Scale Integration (LSI), 1000s of transistors on a
chip
Early 80s: Very Large Scale Integration (VLSI), 100,000s of
transistors on chip but now increased to 1,000,000s of transistors on
chip

5. Ultra large-scale integration (ULSI):
• It describes very large memories, larger microprocessors, and larger
single-chip computers. Complexities of 100,000 equivalent gates and
greater are classified as ULSI.
Wafer-Scale Integration (WSI):
• Another technique used in IC industry is the wafer-scale integration
(WSI), which uses the complete uncut wafers for the development of
processors and memory. The WSI step was taken in 1980s by Gene
Amdahl who is failed due to the semiconductor level manufacturing
issues.
EvolutionContd

6. System-on- Chip (SOC) :
• Although the WSI technique failed due to semiconductor level
manufacturing issues, the advanced tools in semiconductor
manufacturing produces another thread on IC complexity, which is
known as System-on- Chip (SOC) design. In this SOC, the IC blocks
are manufactured as a various chips and have been integrated in a
chip. In addition, the printed circuit boards are developed to occupy
the chip which involves memory, microprocessors, peripheral
interfaces, Input/Output logic control, data converters etc. to develop
electronic systems.
Advantage of VLSI:
• Smaller size Higher reliability
• Lower cost Lower Power More functionality
Disadvantage of VLSI: Long design and fabrication time and Higher
risk to project
EvolutionContd

7. MOS Transistor Theory
• The MOS field effect transistor (MOSFET) is the fundamental
building block of MOS and CMOS digital integrated circuits.
Compared to BJT, the MOS transistor occupies relatively smaller
silicon area, and its fabrication involves fewer processing steps.

8. • These technological advantages, together with relative simplicity of
MOSFET operation, have helped the MOS transistor the most widely
used switching device in LSI and VLSI circuits. In the figure below
(figure 1), the structure consist of three layers: the metal Gate, the
insulating oxide layer (SiO2), and the P-type bulk semiconductor
called the substrate
• From the Mass Action Law, we know that the semiconductor is
always electrically neutral until and unless external potential is
applied. Thus
𝒏. 𝒑 = 𝒏𝒊
𝟐
Assuming that the substrate is uniformly doped with acceptor ion, the
equilibrium electron and hole concentration is given by
𝒏 𝒑𝒐 ≅
𝒏𝒊
𝟐
𝑵 𝑨
MOSTransistorTheory

9. MOS system under External Bias
Assume that the substrate voltage, VB=0, and Gate voltage be the
controlling parameter. Depending upon the polarity and the magnitude
of VG, three different operating regions can be observed: accumulation,
depletion, and inversion.
• Case-I: If a negative voltage, VG, is applied to the Gate electrode, the
holes in the p-type substrate are attracted towards the semiconductor
oxide interface. The majority carrier concentration near the surface
becomes larger than the equilibrium hole concentration in the
substrate. Hence this condition is called accumulation on the surface.
In this case the oxide electric field is directed towards the Gate
electrode. At the interface, the hole concentration is increased and the
electron concentration is reduced
MOSTransistorTheory

10. Case-II: In case two, let us apply a small positive Gate bias at the Gate
electrode. Since the substrate bias is zero, the oxide electric field will
be directed toward the substrate in this case. The positive surface
potential causes the energy bands to bend downwards near the surface
as shown below. The majority carriers i.e. holes in the substrate will be
repelled back into the substrate and will leave negatively charged ions.
Thus a region devoid of any major charge carriers is created, and this
region is called depletion region. In this region, the surface near the
semiconductor-oxide interface is devoid of any major charge carriers
MOSTransistorTheory

11. • The thickness, xd, of this depletion region due to small positive
potential at the Gate electrode can easily be found as a function of the
surface potential φs.
𝒅𝑸 = −𝒒. 𝑵 𝑨. 𝒅𝒙
The change in the surface potential required to displace this charge
sheet dQ by the distance xd away from the surface can be founded by
using the Poisson equation.
𝒅𝝋 𝒔 = −𝒙.
𝒅𝑸
𝜺 𝒔𝒊
=
𝒒. 𝑵 𝑨. 𝒙
𝜺 𝒔𝒊
𝒅𝒙
Integrating the above equation, along the vertical dimension
(perpendicular to the surface) yields
𝝋 𝑭
𝝋 𝒔
𝒅𝝋 𝒔 =
𝟎
𝒙 𝒅 𝒒. 𝑵 𝑨. 𝒙
𝜺 𝒔𝒊
𝒅𝒙
MOSTransistorTheory

12. 𝝋 𝒔 − 𝝋 𝑭 =
𝒒. 𝑵 𝑨. 𝒙 𝒅
𝟐
𝜺 𝒔𝒊
Thus the depth of the depletion region is given by
𝒙 𝒅 =
𝟐𝜺 𝒔𝒊. ǀ𝝋 𝒔 − 𝝋 𝑭ǀ
𝒒. 𝑵 𝑨
And the depletion charge density, which consists solely of fixed
acceptor ions in this region, is given by the following expression
𝑸 = −𝒒. 𝑵 𝑨. 𝒙 𝒅 = − 𝟐𝒒. 𝑵 𝑨. 𝜺 𝒔𝒊. ǀ𝝋 𝒔 − 𝝋 𝑭ǀ
MOSTransistorTheory

13. Case-III: In the third case we further increase the positive Gate bias.
Due to the increase in the surface potential, the downward bending of
the energy band will also increase. Eventually, the mid-gap energy level
Ei becomes smaller than the Fermi level EFP on the surface. This
means that the substrate semiconductor in this region becomes n-
type.
• Within this thin layer, the electron density is larger than the majority
hole density The n-type region created near the surface by the positive
gate bias is called the inversion layer, and this condition is called
surface inversion.
MOSTransistorTheory

14. • Thus the depletion region depth achieved at the onset of surface
inversion is also equal to maximum depletion depth, 𝑥 𝑑𝑚, which
remains constant for higher Gate voltages.
𝒙 𝒅𝒎 =
𝟐. 𝜺 𝒔𝒊. ǀ𝟐𝝋 𝑭ǀ
𝒒. 𝑵 𝑨
MOSTransistorTheory

15. MOS Structure

16. • This four terminal device consist of p-type substrate, having two n+
regions, Drain and Source, are formed. The surface of the substrate
between Drain and Source is covered with thin silicon oxide layer to
act as an insulating layer. On top of this thin layer, a metal contact for
Gate electrode is provided
• The two n+ regions are the current conducting terminals of the
device. The device is completely symmetrical with respect to the
Drain and source regions. These regions are defined separately with
respect to the potential applied to the regions and the direction of the
current flow.
MOSStructure

17. • There are two types of MOSFET based on the presence or absence of
the conduction channel.
• Enhancement type MOSFET: no conducting channel at zero gate
bias
• Depletion type MOSFET: physical presence of conducting channel
at zero gate bias
• n-channel MOSFET: n+ Source and Drain terminal, n-type channel,
and p-type substrate
• p-channel MOSFET: p+ Source and Drain terminal, p-type channel,
and n-type substrate
MOSStructure

18. Control the current conduction between the
source and the drain, using the electric
field generated by the gate voltage as a
control variable. Since the current flow in
the channel is also controlled by the drain-
,to-source voltage and by the substrate
voltage, the current can be considered a
function of these external terminal voltages
MOSStructure

19. Threshold Voltage

20. • The work function difference between the gate and the channel
The work function difference −𝝋 𝑮𝑪 between gate and the channel
reflects the built in potential of the MOS system. Depending on the gate
material the work function difference is given as follows:
𝝋 𝑮𝑪 = 𝝋 𝑭 𝒔𝒖𝒃𝒔𝒕𝒓𝒂𝒕𝒆 − 𝝋 𝑴 𝒇𝒐𝒓 𝒎𝒆𝒕𝒂𝒍 𝒈𝒂𝒕𝒆
𝝋 𝑮𝑪 = 𝝋 𝑭 𝒔𝒖𝒃𝒔𝒕𝒓𝒂𝒕𝒆 − 𝝋 𝑭 𝒈𝒂𝒕𝒆 𝒇𝒐𝒓 𝒑𝒐𝒍𝒚𝒔𝒊𝒍𝒍𝒊𝒄𝒐𝒏 𝒈𝒂𝒕𝒆
• The gate voltage component to change the surface potential
The externally applied gate voltage must be changed to achieve surface
inversion, i.e., to change the surface potential by 〖-2φ〗_F
ThresholdVoltage

21. • The gate voltage component to offset the depletion region charge
This component is due to the fixed acceptor ions located in the
depletion region near the surface. We can calculate the depletion region
charge density at surface inversion (𝝋 𝑺 = −𝝋 𝑭) from the
previous equation of charge density as follows
𝑸 𝑩𝟎 = − 𝟐𝒒. 𝑵 𝑨. 𝜺 𝒔𝒊. ǀ −𝟐𝝋 𝑭 ǀ for VSB = 0
𝑸 𝑩 = − 𝟐𝒒. 𝑵 𝑨. 𝜺 𝒔𝒊. ǀ −𝟐𝝋 𝑭 +𝑽 𝑺𝑩ǀ for VSB ≠ 0
Now the voltage component that offsets the depletion charge density is
given by –QB/Cox where Cox is the gate oxide capacitance per unit area
ThresholdVoltage

22. • The voltage component to offset the fixed charges in the gate
oxide and in the silicon-oxide interface
𝑽 𝑻 = 𝑽 𝑻𝟎 −
𝑸 𝑩 − 𝑸 𝑩𝒐
𝑪 𝒐𝒙
𝑸 𝑩 − 𝑸 𝑩𝒐
𝑪 𝒐𝒙
= −
𝟐𝒒. 𝑵 𝑨. 𝜺 𝒔𝒊
𝑪 𝒐𝒙
( ǀ − 𝟐𝝋 𝑭 + 𝑽 𝑺𝑩 − ǀ − 𝟐𝝋 𝑭)
𝑽 𝑻 = 𝑽 𝑻𝟎 + 𝜸( ǀ − 𝟐𝝋 𝑭 + 𝑽 𝑺𝑩 − ǀ − 𝟐𝝋 𝑭)
𝜸 =
𝟐𝒒. 𝑵 𝑨. 𝜺 𝒔𝒊
𝑪 𝒐𝒙
Where 𝛾 is the substrate bias (or body effect) coefficient
ThresholdVoltage