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ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011



    Energy Efficient and Process Tolerant Full Adder in
               Technologies beyond CMOS
                    Aminul Islam1, Member, IEEE, M. W. Akram2, Mohd. Hasan2, Member, IEEE
                                  1
                                   Department of Electronics and Communication Engineering,
                      Birla Institute of Technology (deemed university), Mesra, Ranchi, Jharkhand, India
                                               E-mail: aminulislam@bitmesra.ac.in
                2
                  Department of Electronics Engineering, Zakir Husain College of Engineering and Technology
                                          Aligarh Muslim University, Aligarh, U.P., India
                                                  E-mail: akrammw@gmail.com

Abstract—This paper presents 1-bit full adder cell in emerging           these limitations by device technology parameter optimization
technologies like FinFET and CNFET that operates in the                  or selecting operating point of the device where both energy
moderate inversion region for energy efficiency, robustness              and speed are in acceptable range. Our proposed strategy is
and higher performance. The performance of the adder is                  to design energy efficient and moderate performance 1-bit full
improved by the optimum selection of important process
                                                                         adder in moderate inversion region (MIR) [4], where devices
parameters like oxide and fin thickness in FinFET and number
of carbon nanotubes, chirality vector and pitch in CNFET.
                                                                         are operated at or near their threshold voltage to extend the
The optimized CNFET-based full adder (OP-CNFET) has                      application domain of subthreshold circuits. Moreover, in the
higher speed, lower PDP (power-delay product) and lower                  moderate inversion region (MIR), the transistor exhibits
power dissipation as compared to the MOSFET and FinFET                   performance close to subthreshold with much lower variability.
full adder cells. The OP-CNFET design also offers tight spread              This paper presents an optimized static 1-bit full adder cell
in power, delay and PDP variability against process, voltage             using fin field effect transistor (FinFET) [5], [6] and carbon
and temperature variations. All the evaluations have been                nanotube field effect transistor (CNFET) [7]–[10] in the moderate
carried out using HSPICE simulations based on 32 nm BPTM                 inversion region (MIR) for achieving high energy efficiency,
(Berkeley Predictive Technology Model).
                                                                         robustness and good performance. The operation in MIR region
Index Terms—Variability, power-delay product (PDP),
                                                                         helps to recover the huge penalty in performance and also to
moderate inversion region (MIR), optimized FinFET-based                  minimize the energy/switching by optimum selection of important
full adder (OP-FinFET), optimized CNFET-based full adder                 process parameters like oxide thickness and fin thickness for
(OP-CNFET).                                                              FinFET and number of carbon nanotube, chirality vector and
                                                                         pitch for CNFET. Moreover, it also performs variability analysis
                       I. INTRODUCTION                                   of the full adder circuit against process, voltage, and temperature
                                                                         (PVT) variations. Full adder based on emerging technologies
    Addition is the most commonly used arithmetic operation in
                                                                         like FinFET and CNFET are more robust than the conventional
microelectronic systems and it is often one of the speed-limiting
                                                                         MOSFET-based full adder. It is a first attempt to the best of our
elements [1]. Hence, the optimization of the adder both in terms
                                                                         knowledge to investigate the near threshold performance of a
of speed and/or power consumption should be pursued. It is
                                                                         full adder cell in emerging technologies beyond CMOS. The full
necessary to improve the performance of full adder cell for fast
                                                                         adder cells are analyzed and compared at 100 MHz on HSPICE
and low energy operations of arithmetic block. In the last five
                                                                         environment using 32 nm BPTM (Berkeley Predictive
years it has been demonstrated that operating the device at
                                                                         Technology Model (BPTM) [11]. The results of CNFET-based
minimum energy point (MEP) gives large penalty in delay,
                                                                         full adder are based on the experimentally validated Stanford
where as minimum energy delay point (MEDP) gives better
                                                                         model [12]. The rest of the paper is organized as follows.
circuit performance in terms of delay as well as energy and
                                                                         Section II briefly describes the structure of the full adder cell.
turn out to be the center of attraction for the researchers.
                                                                         The FinFET structure is described in Section III. Section IV
However, there is a new class of circuit applications which
                                                                         details the CNFET structure. The performance of full adder
demands for ultra low energy consumption with moderate
                                                                         cell in different technologies is reported in Section V. Section
throughput. These circuits must be operated at minimum
                                                                         VI explains the process parameter optimization of FinFET.
energy point to achieve energy at ultra low level. This
                                                                         Process parameter optimization of CNFET is reported in
represents an important mind-shift: rather than starting out
                                                                         section VII. Section VIII presents comparison of full adder
from a design optimized for maximum performance. The initial
                                                                         cells using optimized process parameters. Impact of PVT
design point is now the minimum-energy one. It has been
                                                                         variations on design metrics is investigated in Section IX. Section
shown that for most of the digital circuit’s minimum energy
                                                                         X concludes this paper.
point occurs in the subthreshold operational region of the
MOS transistors [2], [3]. However, performance degradation
                                                                                         II. THE 1-BIT FULL ADDER CELL
due to minute leakage current as drive current and more
sensitivity for process variation due to exponential                        The full-adder [13] operation can be described as follows:
dependency of drive current on threshold voltage limits its              given the three inputs A, B, and Cin, it is desired to obtain two
application area. Hence there is pressing need to overcome               1-bit outputs, SUM and CARRY, where
                                                                    31
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        SUM  A  B  C in                        (1)                       width, thus providing a substantial performance and power
                                                                            improvement compared to the Si-MOSFET [14].
         CARRY  A.B  C in  ( A  B ).            (2)
Several logic styles are used in the literature to design full adder
cells. Each design style has its own merits and demerits. Classical
designs of full adders normally use only one logic style for the
whole full-adder design. One example of such design is the
standard static CMOS full adder shown in Fig. 1. This full adder
is based on regular CMOS structure with conventional pull-up
and pull-down transistors offering full-swing output and good
driving capabilities.

                     III. FINFET STRUCTURE
     Geometric parameters of the conventional Si-CMOS                         Figure 1. Standard CMOS 1-bit full adder cell with conventional
devices have been scaled down aggressively to achieve                                               MOSFET[13].
increased integration density, increased operational
frequency and reduced power consumption. However
beyond submicron region increased static leakage power
dissipation and increased sensitivity to process variation in
performance parameters cause major bottleneck for further
device scaling. Researchers have shown that the promising
multi-gate transistor [15] offers remarkable advantages in terms
of different design metrics. It increases the driving current
with the sub-threshold and gate tunneling leakage currents
within acceptable limit as compared to the standard single-
gate MOSFETs. The multiple electrically coupled gates and
the thin silicon body suppress the short-channel effects
(SCE), hence reducing the subthreshold leakage current in a
multi-gate MOSFET. Reduced SCE improves subthreshold
slope and allows increasing the oxide thickness which results
                                                                            Figure 2. N-type FinFET, P-type FinFET and symmetrical FinFET
in lower gate leakage current. It has been also observed from
                                                                              structure. L: gate length. tsi: fin thickness. Hfin: fin height. tox:
the previous research that multi-gate devices shows better                                            oxide thickness[5].
parameters variation immunity than conventional single gate
device. The most promising multi-gate device is the FinFET
[5], [6] due to the self alignment of the two gates and the
relative compatibility with the existing standard CMOS
fabrication process. The architecture of a double-gate FinFET
with symmetric gates is shown in Fig. 2. The fin thickness
and the gate oxide thickness are the most significant
dimensions in the design of FinFETs because these
parameters have strong impact on its electrical characteristics
[5].
                                                                                   Figure 3. Top view of CNFET structure with multiple
                     IV. CNFET STRUCTURE                                                              channels[12].
                                                                            A single walled CNT (SWCNT) is formed by rolling a sheet of
    Most of the fundamental limitations for traditional silicon
                                                                            graphene (single atomic layer of graphite) into a cylinder.
MOSFETs are mitigated in carbon nanotube field effect
                                                                            The direction of rolling, defined as chirality vector (n 1, n2),
transistor (CNFET) shown in Fig. 3. With ultralong (1
                                                                            determines the properties of the CNT as shown in Fig. 4. A
micrometer) mean free path for elastic scattering, a ballistic or
                                                                            CNT acts as a metal if n1 = n2 or n1 “ n2 = 3i, where ‘i’ is an
near-ballistic transport is obtained with an intrinsic carbon
                                                                            integer. Otherwise, the CNT is semiconducting. The Vt
nanotube (CNT) under low voltage bias to achieve the ultimate
                                                                            (threshold voltage) of CNFET can be varied with CNT
device performance [7]–[10]. The quasi-1-D structure
                                                                            diameter. The Vt of CNFET is an inverse function of the CNT
provides better electrostatic control over the channel region
                                                                            diameter [14]. Compared to silicon technology, the CNFET
than 3-D device (e.g., bulk CMOS) and 2-D device (e.g., fully
                                                                            shows better device performance than the Si-MOSFET even
depleted SOI) structures [10]. Ballistic transport operation
                                                                            with device non-idealities. Increasing the number of CNTs
and low IOFF (OFF-current) make the CNFET a suitable device
                                                                            per device is the most effective way to improve the circuit
for high performance and increased integration. The CNFETs
                                                                            speed. Compared to Si-CMOS circuits, CNFET circuits with
can be scaled down to 10 nm channel length and 4 nm channel
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one to ten CNTs per device is about two to ten times faster,                    TABLE I. NOMINAL PROCESS PARAMETERS    OF   FINFET-BASED D ESIGN
the energy consumption per cycle is about seven to two
times lower and the EDP (energy-delay product) is about 15–
20 times lower [14].

     V. PERFORMANCE OF FULL ADDER CELL IN DIFFERENT
     TECHNOLOGIES WITH NOMINAL PROCESS PARAMETERS
     Nominal process parameters of FinFET- and CNFET-based
designs are tabulated in Table I and II respectively. The 1-bit
static CMOS full adder cells are analyzed with different supply
voltages above the threshold voltage operating at a frequency
of 100 MHz. The structure is simulated with a load capacitance
                                                                               TABLE II. N OMINAL PROCESS PARAMETERS   OF   CNFET-BASED D ESIGN
of 50 fF and at a temperature of 50°C with minimum size transistors.
The minimum size transistors are chosen to minimize the area
and observe the severity of process variation. The BPTM (
Berkeley Predictive Technology Model) used for MOSFET is
the 32 nm high-performance, stained silicon, high-k metal gate
model, which is used in Intel’s latest silicon process technology.
As transistors shrink and threshold voltage scales, leakage
current increases exponentially. Managing that leakage is crucial
for reliable low-power operation and is an increasingly important
factor in circuit design. The gate leakage is significantly reduced
in the high-k metal gate process used here for bulk CMOS giving
rise to energy efficient and high performance systems. The
proposed implementation in FinFET and CNFET technologies
makes full adders even more energy efficient, robust and faster.
This paper proposes the implementation of full adder (Fig. 1)
using FinFET and CNFET technologies by replacing all the N-
type MOSFET and P-type MOSFET with N-type and P-type
FinFET/CNFET structures. The threshold voltages for all
technologies are considered similar at nominal process
parameters and also at the optimum process parameters for fair
comparison. The PDPs of full adders are estimated by scaling
VDD (supply voltage) from 0.9 V down to 0.3 V (Fig. 5). It is
apparent from Fig. 5 that for an input frequency of 100 MHz, the              Figure 5. Power-delay product of full adders vs. VDD at f = 100
                                                                                                          MHz.
minimum energy point for the full adder cell using MOSFET and
FinFET technologies is at VDD = 0.3V. For MOSFET and FinFET-                the delay increases at a faster rate than the reduction in power
based full adders, the PDP decreases with decreasing VDD. This              dissipation due to low driving capability of CNFET (since
is attributed to the fact that Pdynamic (dynamic power) is                  only one CNT is used for this design). Extensive simulation
quadratically related to VDD. The Pdynamic is the dominant                  using HSPICE is carried out to establish the optimum VDD
contributor to the total energy consumption. However, for                   and found that 0.33 V is the optimum operating voltage in the
CNFET-based full adder, the PDP does not decrease as the                    moderate inversion region (MIR) for the full adder cell using
supply voltage is scaled down in the similar manner. This so                MOSFET and FinFET (keeping all design metrics in
happens because at the nominal process parameters of CNFET,                 consideration). Although, the CNFET-based full adder in MIR
                                                                            does not offer minimum energy point, however minimum
                                                                            energy point is achieved by the optimum selection of most
                                                                            important process parameters even in case of CNFET. This
                                                                            supply voltage has been chosen to minimize the effect of
                                                                            delay penalty. Supply voltage variation of 10% is also
                                                                            considered. It is observed from Fig. 6 that FinFET-based full
                                                                            adder cell consumes higher power dissipation than the
                                                                            conventional MOSFET cell at all supply voltages due to its
                                                                            higher driving current [5], [6]. Although the leakage power
                                                                            dissipation for the FinFET structure is less than the single gate
                                                                            MOSFET structure, however increase in dynamic power
  Figure 4. Latice structure of (a) unrolled and (b) rolled graphite        dissipation is higher than the reduction in leakage power
                      sheet to form CNT [14].                               dissipation. The CNFET-based full adder cell has less power
                                                                            dissipation than FinFET structure with nominal process
                                                                       33
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parameters; this is because of lower driving current and
capacitance values. It is observed from Fig. 7 that the full adder
cell with FinFET has shorter delay than the conventional
MOSFET cell at all supply voltages due to its higher current
driving capability [5], [6]. The CNFET based full adder cell offers
longer delay than the FinFET structure; this is because of lower
current driving capability at the nominal process parameters. In
the next section, the performance of FinFET-based adder is
enhanced by optimization of FinFET’s process parameters.

       VI. FINFET’S PROCESS PARAMETER OPTIMIZATION                          Figure 8. PDP of the FinFET-based full adder vs. oxide thickness.

     The PDPs of FinFET-based full adder cell for different oxide
thicknesses are shown in Fig. 8. PDP increases as the gate oxide
thickness increases; this is because the reduction in power
dissipation is less than the increase in delay. It is evident from
Fig. 8 that the oxide thickness of 2.3 nm gives the optimum result
for different performance parameters under consideration. The
optimum value of the oxide thickness is then used to investigate
the variation of PDP with fin thickness. The PDPs of the FinFET
based full adder cell at different fin thicknesses is shown in Fig.
9. It is evident from Fig. 9 that the PDP decreases upto a certain
value of fin thickness and then increases. It is clear that the fin        Figure 9. PDP of the FinFET-based full adder cell vs. fin thickness.
thickness of 14 nm together with oxide thickness of 2.3 nm gives
the optimum result for different performance parameters under
consideration. In the next section, the performance of CNFET-
based full adder is improved by the optimization of CNFET’s
process parameters.

      VII. CNFET’S PROCESS PARAMETER OPTIMIZATION
   The PDP of the CNFET-based full adder cell for different
number of carbon nanotubes is shown in Fig. 10.



                                                                            Figure 10. PDP of the CNFET-Based full adder cell vs. number of
                                                                                                       CNT.
                                                                           It is observed from Fig.10 that the PDP decreases with increase
                                                                           in number of CNT. This is due to the increase in the driving
                                                                           current and hence reduction in delay, which outweighs the
                                                                           increase in power dissipation. However, increase in number of
                                                                           CNT also incurs penalty in power dissipation and area. Thus,
                                                                           keeping all the design metrics (such as leakage, power, delay,
                                                                           and PDP) in mind the optimum number of CNT is chosen to be
 Figure 6. Power dissipation of full adder vs. VDD at f = 100 MHz.         equal to 9. The optimum value of number of carbon nanotube is
                                                                           then used to observe the effect of chirality vector variation on
                                                                           the PDP. The PDP of the CNFET-based full adder cell at different
                                                                           chirality vector is shown in Fig. 11. It is observed from Fig. 11
                                                                           that PDP decreases with increase in chirality vector. This occurs
                                                                           because Vt of CNFET decreases with increase in chirality vector
                                                                           resulting in decrease in delay and increase in power dissipation.
                                                                           The reduction in delay outweighs the increase in power
                                                                           dissipation. Hence, the PDP decreases with increase of chirality
                                                                           vector but at the cost of higher power dissipation. Thus,
                                                                           considering all design metrics like leakage and power, delay and
                                                                           PDP, chirality vector of (26, 0) is chosen to be optimal. The
                                                                           optimum value of chirality vector is then used to observe the
     Figure 7. Delay of the full adder vs. VDD at f = 100 MHz.             effect of pitch variation on the PDP. The PDP of the CNFET-
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© 2011 ACEEE
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based full adder cell at different pitch value is shown in Fig.
12. It shows that the PDP increases with decrease in pitch. This
occurs because a decrease in inter-tube distance results in the
reduction of drive current due to increase in inter-tube coupling.
The decrease in drive current increases the delay. However,
power dissipation decreases due to reduction in drive current.
The increase in delay is higher than the reduction in power
dissipation. Hence, the PDP increases with decrease in pitch.
However, increase in pitch also incurs penalty in power
dissipation. Therefore, keeping all design metrics in mind, a pitch
of 20 nm is chosen to be the best that gives the optimum results
together with optimum value of number of CNT and chirality                        Figure 12. PDP of CNFET-based full adder vs. pitch.
vector. The performance and comparison of the adder cell in                   TABLE I. COMPARISON OF FULL ADDER CELL USING OPTIMIZED PROCESS
optimized technologies are described in the next section.                                       PARAMETERS AT VDD=0.33 V

  VIII. COMPARISON OF FULL ADDER CELLS USING OPTIMIZED
                  PROCESS PARAMETERS
     Different performance parameters using CMOS
technology and technology beyond CMOS are reported in
Table III. The values of average power, delay and PDP are                  There is an improvement in PDP also, since reduction in delay
normalized with respect to that of OP-CNFET (optimized                     outweighs the increase in power dissipation. For the FinFET-
CNFET-based full adder) and are reported in bracket. It is                 based full adder cell, we conclude that fin thickness of 14 nm
observed that the full adder cell with FinFET and CNFET                    and gate oxide thickness of 2.3 nm together with supply voltage
technologies for optimum values of process parameters result               of 0.33 V gives the optimum result. For the CNFET-based full
in significant performance improvement. At the optimum value               adder cell, we conclude that the number of CNT of 9, chirality
of process parameters, CNFET-based full adder has lowest                   vector of (26, 0), and 20 nm pitch together with supply voltage of
power dissipation. This is due to the fact that the increase in            0.33 V gives the optimum result. The optimization of the full
its leakage power dissipation is much less than the full adder             adder in terms of speed and power consumption is necessary to
cell using MOSFET and FinFET structure, which is the                       investigate the potential of technologies beyond CMOS. Its
dominant contributor to total power dissipations in the deep               robustness against PVT variations is even more important and
submicron regime. An improvement in delay is because of                    essential in deep submicron technology. The next section
higher driving current of FinFET and CNFET technologies at                 describes investigation of PVT variation for different
the same supply voltages. It is apparent that the OP-FinFET                technologies.
(optimized FinFET-based full adder) consumes higher power
dissipation than the conventional MOSFET-based full adder                   IX. INVESTIGATION OF IMPACT OF PVT VARIATIONS ON DESIGN
at all supply voltages. This is attributed to fact that FinFET                                      METRICS
has higher drive current [5], [6] at the same supply voltages                  Due to aggressive scaling, random variations in process,
due to the presence of its double gate. Although the leakage               supply voltage and temperature (PVT) are posing a major
power dissipation of FinFET structure is less than single                  challenge to high performance circuits and system design [16].
gate MOSFET, the increase in dynamic power dissipation is                  The process variations include variation in oxide thickness (tox),
higher than the reduction in leakage power dissipation.                    channel length (L) in short channel devices, channel width (W)
                                                                           in narrow channel devices, substrate doping concentration
                                                                           (NSUB), channel doping concentration (NCH), polysilicon gate
                                                                           doping concentration (NPOLY), source/drain sheet resistance
                                                                           (RSD). All these process parameters affect Vt, which in turn
                                                                           modulates the drain to source current IDS. Therefore,
                                                                           propagation delay (tp) along with average power dissipation
                                                                           (P) and power-delay product (PDP) are taken as important
                                                                           design metrics for the analysis and design of full adder circuit
                                                                           in this paper. PVT variations can be mitigated by various
                                                                           design techniques. Adaptive body biasing is one such
                                                                           technique [17]. Circuit design techniques such as body
Figure 11. PDP of CNFET-based full adder cell vs. chirality vector         biasing will help, but their effect diminishes with technology
                                                                           scaling. This paper investigates for the first time to the best
                                                                           of our knowledge static CMOS 1-bit full adder against PVT
                                                                           variations at 32 nm technology node using Monte Carlo
                                                                           method in the moderate inversion region. This investigation
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                       ACKNOWLEDGMENT                                       microprocessor frequency and leakage,” IEEE J. Solid-State Circuits,
    The authors wish to thank administration of Birla Institute             vol. 37, no. 11, Nov. 2002.
of Technology (deemed university), Mesra, Ranchi, Jharkhand,
India. This work was supported in part by BIT, Mesra, Ranchi,
Jharkhand, India by sponsoring first author.

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DOI: 01.IJCOM.02.02.25
ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011


                         Aminul Islam (M’10) graduated in               degree from IIT, Kanpur, India in the Electrical Engineering
                         Computer Engineering from The In-              Department His research interests include computer-aided
                         stitution of Engineers (India) in 2001,        design for conventional nanoscale Silicon and non-conven-
                         and post graduated in Electronics              tional Silicon technologies (that includes FinFET, CNFET),
                         and Communication Engineering                  robust design of ultra-low power nanoscale circuit for por-
                         from Birla Institute of Technology             table computing and wireless communications. He has pub-
                         (deemed university), Mesra, Ranchi,            lished more than 10 research papers in reputed Conferences
                         Jharkhand, India in 2006. Until No-            and Journals.
                         vember 2006, he was with Indian Air                                     Dr. Mohd Hasan (M’10) received
Force. Since November 2006, he has been with the Electron-                                       the B.Tech. degree in Electronics
ics and Communication Engineering Department, Birla Insti-                                       Engineering from Aligarh Muslim
tute of Technology, Mesra, Ranchi, Jharkhand, India, where                                       University (AMU), India in 1990, the
he is currently an Asst. Professor. His research interests in-                                   M.Tech. degree in Integrated Elec-
clude VLSI design for nanoscale emerging silicon and non-                                        tronics and Circuits from the IIT,
silicon technologies (that includes FinFET, CNFET), robust                                       Delhi, India in 1992 and joined as
design of ultra-low power nanoscale circuit for portable com-                                    Lecturer in Electronics Engineering
puting and wireless communications. He is currently work-                                        Department of AMU in 1992. He re
ing toward the Ph.D. degree in the field of VLSI design from
the Department of Electronics Engineering, Aligarh Muslim               ceived the Ph.D. degree from the University of Edinburgh,
University, Aligarh, Uttar Pradesh, India. He has published             UK in 2004 on a Commonwealth Scholarship in the area of
more than 25 research papers in reputed Conferences and                 Low Power Architectures for Multi-carrier Systems. He has
Journals.                                                               also worked as a postdoctoral visiting researcher on a pres-
                                                                        tigious Royal Academy of Engineering, UK funded project
                        Md. Waseem Akram received the                   on Low Power FPGA Architecture in 2008-2009 in the School
                        B.Tech. degree in Electronics and Tele-         of Engineering, University of Edinburgh, UK. He has been
                        Communication Engineering from Na-              currently working as Professor at Aligarh Muslim University,
                        tional Institute of Science and Tech-           Aligarh, India since 2005. He has published more than 100
                        nology (NIST), Orissa, India in 2008,           research papers in reputed Journals and Conferences. His
                        the M.Tech (Electronic Circuits & Sys-          research interest includes Low power VLSI design,
                        tems Design) degree from Aligarh                Nanoelectronics, FPGA Architectures along with Embedded
                        Muslim University, India in 2010. He is         System Design.
                        currently working toward the Ph.D.




                                                                   37
© 2011 ACEEE
DOI: 01.IJCOM.02.02. 25

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Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOS

  • 1. ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011 Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOS Aminul Islam1, Member, IEEE, M. W. Akram2, Mohd. Hasan2, Member, IEEE 1 Department of Electronics and Communication Engineering, Birla Institute of Technology (deemed university), Mesra, Ranchi, Jharkhand, India E-mail: aminulislam@bitmesra.ac.in 2 Department of Electronics Engineering, Zakir Husain College of Engineering and Technology Aligarh Muslim University, Aligarh, U.P., India E-mail: akrammw@gmail.com Abstract—This paper presents 1-bit full adder cell in emerging these limitations by device technology parameter optimization technologies like FinFET and CNFET that operates in the or selecting operating point of the device where both energy moderate inversion region for energy efficiency, robustness and speed are in acceptable range. Our proposed strategy is and higher performance. The performance of the adder is to design energy efficient and moderate performance 1-bit full improved by the optimum selection of important process adder in moderate inversion region (MIR) [4], where devices parameters like oxide and fin thickness in FinFET and number of carbon nanotubes, chirality vector and pitch in CNFET. are operated at or near their threshold voltage to extend the The optimized CNFET-based full adder (OP-CNFET) has application domain of subthreshold circuits. Moreover, in the higher speed, lower PDP (power-delay product) and lower moderate inversion region (MIR), the transistor exhibits power dissipation as compared to the MOSFET and FinFET performance close to subthreshold with much lower variability. full adder cells. The OP-CNFET design also offers tight spread This paper presents an optimized static 1-bit full adder cell in power, delay and PDP variability against process, voltage using fin field effect transistor (FinFET) [5], [6] and carbon and temperature variations. All the evaluations have been nanotube field effect transistor (CNFET) [7]–[10] in the moderate carried out using HSPICE simulations based on 32 nm BPTM inversion region (MIR) for achieving high energy efficiency, (Berkeley Predictive Technology Model). robustness and good performance. The operation in MIR region Index Terms—Variability, power-delay product (PDP), helps to recover the huge penalty in performance and also to moderate inversion region (MIR), optimized FinFET-based minimize the energy/switching by optimum selection of important full adder (OP-FinFET), optimized CNFET-based full adder process parameters like oxide thickness and fin thickness for (OP-CNFET). FinFET and number of carbon nanotube, chirality vector and pitch for CNFET. Moreover, it also performs variability analysis I. INTRODUCTION of the full adder circuit against process, voltage, and temperature (PVT) variations. Full adder based on emerging technologies Addition is the most commonly used arithmetic operation in like FinFET and CNFET are more robust than the conventional microelectronic systems and it is often one of the speed-limiting MOSFET-based full adder. It is a first attempt to the best of our elements [1]. Hence, the optimization of the adder both in terms knowledge to investigate the near threshold performance of a of speed and/or power consumption should be pursued. It is full adder cell in emerging technologies beyond CMOS. The full necessary to improve the performance of full adder cell for fast adder cells are analyzed and compared at 100 MHz on HSPICE and low energy operations of arithmetic block. In the last five environment using 32 nm BPTM (Berkeley Predictive years it has been demonstrated that operating the device at Technology Model (BPTM) [11]. The results of CNFET-based minimum energy point (MEP) gives large penalty in delay, full adder are based on the experimentally validated Stanford where as minimum energy delay point (MEDP) gives better model [12]. The rest of the paper is organized as follows. circuit performance in terms of delay as well as energy and Section II briefly describes the structure of the full adder cell. turn out to be the center of attraction for the researchers. The FinFET structure is described in Section III. Section IV However, there is a new class of circuit applications which details the CNFET structure. The performance of full adder demands for ultra low energy consumption with moderate cell in different technologies is reported in Section V. Section throughput. These circuits must be operated at minimum VI explains the process parameter optimization of FinFET. energy point to achieve energy at ultra low level. This Process parameter optimization of CNFET is reported in represents an important mind-shift: rather than starting out section VII. Section VIII presents comparison of full adder from a design optimized for maximum performance. The initial cells using optimized process parameters. Impact of PVT design point is now the minimum-energy one. It has been variations on design metrics is investigated in Section IX. Section shown that for most of the digital circuit’s minimum energy X concludes this paper. point occurs in the subthreshold operational region of the MOS transistors [2], [3]. However, performance degradation II. THE 1-BIT FULL ADDER CELL due to minute leakage current as drive current and more sensitivity for process variation due to exponential The full-adder [13] operation can be described as follows: dependency of drive current on threshold voltage limits its given the three inputs A, B, and Cin, it is desired to obtain two application area. Hence there is pressing need to overcome 1-bit outputs, SUM and CARRY, where 31 © 2011 ACEEE DOI: 01.IJCOM.02.02.25
  • 2. ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011 SUM  A  B  C in (1) width, thus providing a substantial performance and power improvement compared to the Si-MOSFET [14]. CARRY  A.B  C in  ( A  B ). (2) Several logic styles are used in the literature to design full adder cells. Each design style has its own merits and demerits. Classical designs of full adders normally use only one logic style for the whole full-adder design. One example of such design is the standard static CMOS full adder shown in Fig. 1. This full adder is based on regular CMOS structure with conventional pull-up and pull-down transistors offering full-swing output and good driving capabilities. III. FINFET STRUCTURE Geometric parameters of the conventional Si-CMOS Figure 1. Standard CMOS 1-bit full adder cell with conventional devices have been scaled down aggressively to achieve MOSFET[13]. increased integration density, increased operational frequency and reduced power consumption. However beyond submicron region increased static leakage power dissipation and increased sensitivity to process variation in performance parameters cause major bottleneck for further device scaling. Researchers have shown that the promising multi-gate transistor [15] offers remarkable advantages in terms of different design metrics. It increases the driving current with the sub-threshold and gate tunneling leakage currents within acceptable limit as compared to the standard single- gate MOSFETs. The multiple electrically coupled gates and the thin silicon body suppress the short-channel effects (SCE), hence reducing the subthreshold leakage current in a multi-gate MOSFET. Reduced SCE improves subthreshold slope and allows increasing the oxide thickness which results Figure 2. N-type FinFET, P-type FinFET and symmetrical FinFET in lower gate leakage current. It has been also observed from structure. L: gate length. tsi: fin thickness. Hfin: fin height. tox: the previous research that multi-gate devices shows better oxide thickness[5]. parameters variation immunity than conventional single gate device. The most promising multi-gate device is the FinFET [5], [6] due to the self alignment of the two gates and the relative compatibility with the existing standard CMOS fabrication process. The architecture of a double-gate FinFET with symmetric gates is shown in Fig. 2. The fin thickness and the gate oxide thickness are the most significant dimensions in the design of FinFETs because these parameters have strong impact on its electrical characteristics [5]. Figure 3. Top view of CNFET structure with multiple IV. CNFET STRUCTURE channels[12]. A single walled CNT (SWCNT) is formed by rolling a sheet of Most of the fundamental limitations for traditional silicon graphene (single atomic layer of graphite) into a cylinder. MOSFETs are mitigated in carbon nanotube field effect The direction of rolling, defined as chirality vector (n 1, n2), transistor (CNFET) shown in Fig. 3. With ultralong (1 determines the properties of the CNT as shown in Fig. 4. A micrometer) mean free path for elastic scattering, a ballistic or CNT acts as a metal if n1 = n2 or n1 “ n2 = 3i, where ‘i’ is an near-ballistic transport is obtained with an intrinsic carbon integer. Otherwise, the CNT is semiconducting. The Vt nanotube (CNT) under low voltage bias to achieve the ultimate (threshold voltage) of CNFET can be varied with CNT device performance [7]–[10]. The quasi-1-D structure diameter. The Vt of CNFET is an inverse function of the CNT provides better electrostatic control over the channel region diameter [14]. Compared to silicon technology, the CNFET than 3-D device (e.g., bulk CMOS) and 2-D device (e.g., fully shows better device performance than the Si-MOSFET even depleted SOI) structures [10]. Ballistic transport operation with device non-idealities. Increasing the number of CNTs and low IOFF (OFF-current) make the CNFET a suitable device per device is the most effective way to improve the circuit for high performance and increased integration. The CNFETs speed. Compared to Si-CMOS circuits, CNFET circuits with can be scaled down to 10 nm channel length and 4 nm channel 32 © 2011 ACEEE DOI: 01.IJCOM.02.02.25
  • 3. ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011 one to ten CNTs per device is about two to ten times faster, TABLE I. NOMINAL PROCESS PARAMETERS OF FINFET-BASED D ESIGN the energy consumption per cycle is about seven to two times lower and the EDP (energy-delay product) is about 15– 20 times lower [14]. V. PERFORMANCE OF FULL ADDER CELL IN DIFFERENT TECHNOLOGIES WITH NOMINAL PROCESS PARAMETERS Nominal process parameters of FinFET- and CNFET-based designs are tabulated in Table I and II respectively. The 1-bit static CMOS full adder cells are analyzed with different supply voltages above the threshold voltage operating at a frequency of 100 MHz. The structure is simulated with a load capacitance TABLE II. N OMINAL PROCESS PARAMETERS OF CNFET-BASED D ESIGN of 50 fF and at a temperature of 50°C with minimum size transistors. The minimum size transistors are chosen to minimize the area and observe the severity of process variation. The BPTM ( Berkeley Predictive Technology Model) used for MOSFET is the 32 nm high-performance, stained silicon, high-k metal gate model, which is used in Intel’s latest silicon process technology. As transistors shrink and threshold voltage scales, leakage current increases exponentially. Managing that leakage is crucial for reliable low-power operation and is an increasingly important factor in circuit design. The gate leakage is significantly reduced in the high-k metal gate process used here for bulk CMOS giving rise to energy efficient and high performance systems. The proposed implementation in FinFET and CNFET technologies makes full adders even more energy efficient, robust and faster. This paper proposes the implementation of full adder (Fig. 1) using FinFET and CNFET technologies by replacing all the N- type MOSFET and P-type MOSFET with N-type and P-type FinFET/CNFET structures. The threshold voltages for all technologies are considered similar at nominal process parameters and also at the optimum process parameters for fair comparison. The PDPs of full adders are estimated by scaling VDD (supply voltage) from 0.9 V down to 0.3 V (Fig. 5). It is apparent from Fig. 5 that for an input frequency of 100 MHz, the Figure 5. Power-delay product of full adders vs. VDD at f = 100 MHz. minimum energy point for the full adder cell using MOSFET and FinFET technologies is at VDD = 0.3V. For MOSFET and FinFET- the delay increases at a faster rate than the reduction in power based full adders, the PDP decreases with decreasing VDD. This dissipation due to low driving capability of CNFET (since is attributed to the fact that Pdynamic (dynamic power) is only one CNT is used for this design). Extensive simulation quadratically related to VDD. The Pdynamic is the dominant using HSPICE is carried out to establish the optimum VDD contributor to the total energy consumption. However, for and found that 0.33 V is the optimum operating voltage in the CNFET-based full adder, the PDP does not decrease as the moderate inversion region (MIR) for the full adder cell using supply voltage is scaled down in the similar manner. This so MOSFET and FinFET (keeping all design metrics in happens because at the nominal process parameters of CNFET, consideration). Although, the CNFET-based full adder in MIR does not offer minimum energy point, however minimum energy point is achieved by the optimum selection of most important process parameters even in case of CNFET. This supply voltage has been chosen to minimize the effect of delay penalty. Supply voltage variation of 10% is also considered. It is observed from Fig. 6 that FinFET-based full adder cell consumes higher power dissipation than the conventional MOSFET cell at all supply voltages due to its higher driving current [5], [6]. Although the leakage power dissipation for the FinFET structure is less than the single gate MOSFET structure, however increase in dynamic power Figure 4. Latice structure of (a) unrolled and (b) rolled graphite dissipation is higher than the reduction in leakage power sheet to form CNT [14]. dissipation. The CNFET-based full adder cell has less power dissipation than FinFET structure with nominal process 33 © 2011 ACEEE DOI: 01.IJCOM.02.02. 25
  • 4. ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011 parameters; this is because of lower driving current and capacitance values. It is observed from Fig. 7 that the full adder cell with FinFET has shorter delay than the conventional MOSFET cell at all supply voltages due to its higher current driving capability [5], [6]. The CNFET based full adder cell offers longer delay than the FinFET structure; this is because of lower current driving capability at the nominal process parameters. In the next section, the performance of FinFET-based adder is enhanced by optimization of FinFET’s process parameters. VI. FINFET’S PROCESS PARAMETER OPTIMIZATION Figure 8. PDP of the FinFET-based full adder vs. oxide thickness. The PDPs of FinFET-based full adder cell for different oxide thicknesses are shown in Fig. 8. PDP increases as the gate oxide thickness increases; this is because the reduction in power dissipation is less than the increase in delay. It is evident from Fig. 8 that the oxide thickness of 2.3 nm gives the optimum result for different performance parameters under consideration. The optimum value of the oxide thickness is then used to investigate the variation of PDP with fin thickness. The PDPs of the FinFET based full adder cell at different fin thicknesses is shown in Fig. 9. It is evident from Fig. 9 that the PDP decreases upto a certain value of fin thickness and then increases. It is clear that the fin Figure 9. PDP of the FinFET-based full adder cell vs. fin thickness. thickness of 14 nm together with oxide thickness of 2.3 nm gives the optimum result for different performance parameters under consideration. In the next section, the performance of CNFET- based full adder is improved by the optimization of CNFET’s process parameters. VII. CNFET’S PROCESS PARAMETER OPTIMIZATION The PDP of the CNFET-based full adder cell for different number of carbon nanotubes is shown in Fig. 10. Figure 10. PDP of the CNFET-Based full adder cell vs. number of CNT. It is observed from Fig.10 that the PDP decreases with increase in number of CNT. This is due to the increase in the driving current and hence reduction in delay, which outweighs the increase in power dissipation. However, increase in number of CNT also incurs penalty in power dissipation and area. Thus, keeping all the design metrics (such as leakage, power, delay, and PDP) in mind the optimum number of CNT is chosen to be Figure 6. Power dissipation of full adder vs. VDD at f = 100 MHz. equal to 9. The optimum value of number of carbon nanotube is then used to observe the effect of chirality vector variation on the PDP. The PDP of the CNFET-based full adder cell at different chirality vector is shown in Fig. 11. It is observed from Fig. 11 that PDP decreases with increase in chirality vector. This occurs because Vt of CNFET decreases with increase in chirality vector resulting in decrease in delay and increase in power dissipation. The reduction in delay outweighs the increase in power dissipation. Hence, the PDP decreases with increase of chirality vector but at the cost of higher power dissipation. Thus, considering all design metrics like leakage and power, delay and PDP, chirality vector of (26, 0) is chosen to be optimal. The optimum value of chirality vector is then used to observe the Figure 7. Delay of the full adder vs. VDD at f = 100 MHz. effect of pitch variation on the PDP. The PDP of the CNFET- 34 © 2011 ACEEE DOI: 01.IJCOM.02.02.25
  • 5. ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011 based full adder cell at different pitch value is shown in Fig. 12. It shows that the PDP increases with decrease in pitch. This occurs because a decrease in inter-tube distance results in the reduction of drive current due to increase in inter-tube coupling. The decrease in drive current increases the delay. However, power dissipation decreases due to reduction in drive current. The increase in delay is higher than the reduction in power dissipation. Hence, the PDP increases with decrease in pitch. However, increase in pitch also incurs penalty in power dissipation. Therefore, keeping all design metrics in mind, a pitch of 20 nm is chosen to be the best that gives the optimum results together with optimum value of number of CNT and chirality Figure 12. PDP of CNFET-based full adder vs. pitch. vector. The performance and comparison of the adder cell in TABLE I. COMPARISON OF FULL ADDER CELL USING OPTIMIZED PROCESS optimized technologies are described in the next section. PARAMETERS AT VDD=0.33 V VIII. COMPARISON OF FULL ADDER CELLS USING OPTIMIZED PROCESS PARAMETERS Different performance parameters using CMOS technology and technology beyond CMOS are reported in Table III. The values of average power, delay and PDP are There is an improvement in PDP also, since reduction in delay normalized with respect to that of OP-CNFET (optimized outweighs the increase in power dissipation. For the FinFET- CNFET-based full adder) and are reported in bracket. It is based full adder cell, we conclude that fin thickness of 14 nm observed that the full adder cell with FinFET and CNFET and gate oxide thickness of 2.3 nm together with supply voltage technologies for optimum values of process parameters result of 0.33 V gives the optimum result. For the CNFET-based full in significant performance improvement. At the optimum value adder cell, we conclude that the number of CNT of 9, chirality of process parameters, CNFET-based full adder has lowest vector of (26, 0), and 20 nm pitch together with supply voltage of power dissipation. This is due to the fact that the increase in 0.33 V gives the optimum result. The optimization of the full its leakage power dissipation is much less than the full adder adder in terms of speed and power consumption is necessary to cell using MOSFET and FinFET structure, which is the investigate the potential of technologies beyond CMOS. Its dominant contributor to total power dissipations in the deep robustness against PVT variations is even more important and submicron regime. An improvement in delay is because of essential in deep submicron technology. The next section higher driving current of FinFET and CNFET technologies at describes investigation of PVT variation for different the same supply voltages. It is apparent that the OP-FinFET technologies. (optimized FinFET-based full adder) consumes higher power dissipation than the conventional MOSFET-based full adder IX. INVESTIGATION OF IMPACT OF PVT VARIATIONS ON DESIGN at all supply voltages. This is attributed to fact that FinFET METRICS has higher drive current [5], [6] at the same supply voltages Due to aggressive scaling, random variations in process, due to the presence of its double gate. Although the leakage supply voltage and temperature (PVT) are posing a major power dissipation of FinFET structure is less than single challenge to high performance circuits and system design [16]. gate MOSFET, the increase in dynamic power dissipation is The process variations include variation in oxide thickness (tox), higher than the reduction in leakage power dissipation. channel length (L) in short channel devices, channel width (W) in narrow channel devices, substrate doping concentration (NSUB), channel doping concentration (NCH), polysilicon gate doping concentration (NPOLY), source/drain sheet resistance (RSD). All these process parameters affect Vt, which in turn modulates the drain to source current IDS. Therefore, propagation delay (tp) along with average power dissipation (P) and power-delay product (PDP) are taken as important design metrics for the analysis and design of full adder circuit in this paper. PVT variations can be mitigated by various design techniques. Adaptive body biasing is one such technique [17]. Circuit design techniques such as body Figure 11. PDP of CNFET-based full adder cell vs. chirality vector biasing will help, but their effect diminishes with technology scaling. This paper investigates for the first time to the best of our knowledge static CMOS 1-bit full adder against PVT variations at 32 nm technology node using Monte Carlo method in the moderate inversion region. This investigation 35 © 2011 ACEEE DOI: 01.IJCOM.02.02. 25
  • 6. ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011 reveals the robustness of FinFET- and CNFET-based adder REFERENCES cell against PVT variations in the moderate inversion region. [1] J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Device parameters tox, L, W, NSUB, NCH, NPOLY, RSD are assumed Circuits: A Design Perspective, 2nd ed., Prentice Hall, Englewood have independent Gaussian distributions with 3ó variation Cliffs, NJ, 2002. of 10% [6]. The values of average power, delay and PDP [2] B. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and variability are normalized with respect to that of OP-CNFET sizing for minimum energy operation in subthreshold circuits,” and are reported in bracket (Table IV). It is observed from IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1778–1786, Sep. Table IV that the emerging technology-based full adder cells 2005. OP-FinFET and OP-CNFET offer tighter spread in power, [3] B. Zhai et al., “A 2.60 pJ/inst subthreshold sensor processor for optimal energy efficiency,” in IEEE Symp. VLSI Circuits delay and PDP variabilities against PVT variations. OP- Dig.Tech. Papers, 2006, pp. 154–155. FinFET full adder cell is more robust than the CMOS-based [4] D. Markovic, C. C. Wang, L. P. Alarcon, T-T. Liu, and J. M. full adder cell because the short channel and process variation Rabaey, “Ultralow-power design in near-threshold region,” Proc. effects are minimized due to the presence of double gate in IEEE, vol. 98, no. 2, Feb. 2010. FinFET. Moreover, FinFET offers better channel electrostatic [5] S. A. Tawfik, and Volkan Kursun, “FinFET technology than MOSFET. It is observed that the CNFET is more robust development guidelines for higher performance, lower power, and against process variations compared to Si-CMOS. This is stronger resilience to parameter variations,” IEEE Int. Midwest Symp. due to its cylindrical geometry. A variation in the gate oxide Circuits and Systems (MWSCAS), 2009, pp. 431-434. thickness that strongly affects the drive current and [6] R. Vaddi, S. Dasgupta, and R. P. Agarwal, “Device and circuit co-design robustness studies in the subthreshold logic for ultralow- capacitance of CMOS transistors has a negligible impact on power applications for 32 nm CMOS’’, IEEE Trans. Electron the CNFET operation. Moreover the gate width in CNFET is Devices, vol. 57, no. 3, pp. 654-664, 2010. not the effective channel width of the transistor. [7] A. Javey, J. Guo, D. B. Farmer, Q. Wang, D. Wang, R. G. TABLE I. VARIABILITY ANALYSIS R ESULTS OF FULL ADDERS USING CMOS AND Gordon, M. Lundstrom, and H. Dai, “Carbon nanotube field-effect TECHNOLOGIES BEYOND CMOS AT VDD =0.33 V transistors with integrated ohmic contacts and high-k gate dielectrics,” Nano Lett., vol. 4, no. 3, pp. 447–450, 2004. [8] A. Javey, J. Guo, D. B. Farmer, Q. Wang, E. Yenilmez, R. G. Gordon, M. Lundstrom, and H. Dai, “Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays,” Nano Lett., vol. 4, no. 7, pp. 1319–1322, 2004. [9] Z. Yao, C. L. Kane, and C. Dekker, “High-field electrical transport in single-wall carbon nanotubes,” Phys. Rev. Lett., vol. 84, no. 13, pp. 2941– 2944, Mar. 2000. X. CONCLUSION [10] Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber, This paper presents a technology beyond CMOS-based full “High performance silicon nanowire field effect transistors,” Nano Lett., vol. 3, no. 2, pp. 149–152, 2003. adder cell optimized in terms of overall power, delay, and energy [11] Berkeley Predictive Technology Model: Device Group, efficiency by judicious selection of process parameters and University of California at Berkeley [online] Available: http://www- supply voltage. FinFET-based full adder cell is found to exhibit device.eecs.berkeley.edu/~ptm. higher switching speed and energy efficiency as compared to [12] Stanford University CNFETModelWeb site. (2008). [Online]. MOSFET-based full adder cell in the Moderate Inversion Region Available: http://nano.stanford.edu/model.php?id=23 (MIR) with nominal value of process parameters. The optimized [13] A.M. Shams, T.K. Darwish, M.A. Bayoumi, “Performance FinFET-based full adder offers better performance and tighter analysis of low-power 1-bit CMOS full adder cells,” IEEE Trans. spread in power consumption, delay and PDP against PVT Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20–29, variations. At nominal process parameters, CNFET-based full Jan. 2002. [14] J. Deng, “Device modeling and circuit performance evaluation adder does not offer much improvement in different design metrics for nanoscale devices: silicon technology beyond 45 nm node and in the moderate inversion region. However for the optimum value carbon nanotube field effect transistors,” Ph.D. dissertation, Dept. of process parameters, it achieves the highest improvement in Elect. Eng., Stanford Univ., Cambridge, MA, 2007. all the design metrics among all technologies considered in this [15] K. Kim et al., “Leakage power analysis of 25-nm double-gate paper. Moreover, the CNFET-based full adder cell exhibits more CMOS devices and circuits,” IEEE Trans. Electron Devices, vol. robustness against PVT variations than the MOSFET-based 52, no. 5, pp. 980-986, May 2005. full adder cell. It is concluded that both the FinFET and CNFET [16] S. Borkar, et al., “Parameter variations and impact on circuits technologies are very promising for realizing robust circuits such and microarchitecture,” in Proc. Design Automation Conf., 2003, as full adder in future scaled technology nodes. pp. 338-342. [17] James W. Tschanz, et al., “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on ACKNOWLEDGMENT microprocessor frequency and leakage,” IEEE J. Solid-State Circuits, The authors wish to thank administration of Birla Institute vol. 37, no. 11, Nov. 2002. of Technology (deemed university), Mesra, Ranchi, Jharkhand, India. This work was supported in part by BIT, Mesra, Ranchi, Jharkhand, India by sponsoring first author. 36 © 2011 ACEEE DOI: 01.IJCOM.02.02.25
  • 7. ACEEE Int. J. on Communication, Vol. 02, No. 02, July 2011 Aminul Islam (M’10) graduated in degree from IIT, Kanpur, India in the Electrical Engineering Computer Engineering from The In- Department His research interests include computer-aided stitution of Engineers (India) in 2001, design for conventional nanoscale Silicon and non-conven- and post graduated in Electronics tional Silicon technologies (that includes FinFET, CNFET), and Communication Engineering robust design of ultra-low power nanoscale circuit for por- from Birla Institute of Technology table computing and wireless communications. He has pub- (deemed university), Mesra, Ranchi, lished more than 10 research papers in reputed Conferences Jharkhand, India in 2006. Until No- and Journals. vember 2006, he was with Indian Air Dr. Mohd Hasan (M’10) received Force. Since November 2006, he has been with the Electron- the B.Tech. degree in Electronics ics and Communication Engineering Department, Birla Insti- Engineering from Aligarh Muslim tute of Technology, Mesra, Ranchi, Jharkhand, India, where University (AMU), India in 1990, the he is currently an Asst. Professor. His research interests in- M.Tech. degree in Integrated Elec- clude VLSI design for nanoscale emerging silicon and non- tronics and Circuits from the IIT, silicon technologies (that includes FinFET, CNFET), robust Delhi, India in 1992 and joined as design of ultra-low power nanoscale circuit for portable com- Lecturer in Electronics Engineering puting and wireless communications. He is currently work- Department of AMU in 1992. He re ing toward the Ph.D. degree in the field of VLSI design from the Department of Electronics Engineering, Aligarh Muslim ceived the Ph.D. degree from the University of Edinburgh, University, Aligarh, Uttar Pradesh, India. He has published UK in 2004 on a Commonwealth Scholarship in the area of more than 25 research papers in reputed Conferences and Low Power Architectures for Multi-carrier Systems. He has Journals. also worked as a postdoctoral visiting researcher on a pres- tigious Royal Academy of Engineering, UK funded project Md. Waseem Akram received the on Low Power FPGA Architecture in 2008-2009 in the School B.Tech. degree in Electronics and Tele- of Engineering, University of Edinburgh, UK. He has been Communication Engineering from Na- currently working as Professor at Aligarh Muslim University, tional Institute of Science and Tech- Aligarh, India since 2005. He has published more than 100 nology (NIST), Orissa, India in 2008, research papers in reputed Journals and Conferences. His the M.Tech (Electronic Circuits & Sys- research interest includes Low power VLSI design, tems Design) degree from Aligarh Nanoelectronics, FPGA Architectures along with Embedded Muslim University, India in 2010. He is System Design. currently working toward the Ph.D. 37 © 2011 ACEEE DOI: 01.IJCOM.02.02. 25