1. International Journal of Electronics and Communication Engineering AND COMMUNICATION0976 –
INTERNATIONAL JOURNAL OF ELECTRONICS & Technology (IJECET), ISSN
6464(Print), ISSN 0976 – 6472(Online) Volume & Issue 3, October- December (2012), © IAEME
ENGINEERING 3, TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 3, Issue 3, October- December (2012), pp. 14-21 IJECET
© IAEME: www.iaeme.com/ijecet.asp
Journal Impact Factor (2012): 3.5930 (Calculated by GISI) ©IAEME
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DESIGN OF POWER EFFICIENT 4x4 ARRAY MULTIPLIER USING
ADIABATIC LOGIC
A.Andamuthu,
Assistant Professor
Muthayammal Engineering College,Tamilnadu,India.
Email ID: andamuthuece@gmail.com
R. Shankar,
Assistant Professor
Dept of ECE, Vidhya Mandhir Institute of Technology
Erode, Email: sha8189@gmail.com
J. Vinoth Kumar
Assistant Professor
Dept of ECE, J. J. College of Engineering and Technology
Trichy, Email: vino.vinothkumar@gmail.com
ABSTRACT
The main process of this paper is to reduce the power in array multiplier using adiabatic logic.
Adiabatic logic is an approach to low-power digital circuits that differs fundamentally from other
practical low-power techniques. When adiabatic logic is used, the signal energies stored on
circuit capacitances may be recycled instead of dissipated as heat. With the help of TSPICE
simulations, the power consumption is analyzed by variation of parameter. In existing method,
two logic families, 2N-2P logic and 2N-2N2P logic are compared with conventional CMOS
logic for array multiplier circuits. In proposed method, 2N-2P logic is enhanced by adding pull
down network and power clock to reduce the power consumption. It is find that adiabatic
technique is good choice for low power application in specified frequency range.
IndexTerms— Adiabatic logic, power dissipation, power clock
I. INTRODUCTION
Reducing power consumption has become an important issue in integrated circuit design
owing to the strong demand for low power system-on-chip (SoC) and portable electronic
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2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
equipment [2].The energy dissipated in adiabatic circuits is considerably lesser than that in the
static CMOS circuits, hence adiabatic circuits are promising candidates for low power circuits
that can be operated in the frequency range in which signals are digitally processed. In this study,
we compare the power consumption in Adiabatic CMOS logic circuits and conventional CMOS
circuits.
In most of the DSP system the multiplier is part of the critical path that determines the
overall performance of the system. That is why enhancing the performance of the 1-bit full-adder
cell (the building block of the binary adder) is a significant goal. Based on the full adder design
circuits, the multiplier was designed. Adiabatic logic circuits reduce the energy dissipation
during switching process, and reuse the some of energy by recycling from the load capacitance
[4, 5]. For recycling, the adiabatic circuits use the constant current source power supply and for
reduce dissipation it uses the trapezoidal [6] or sinusoidal power supply voltage [3].
II. PRINCIPLES OF ADIABATIC
LOGIC:
The word ADIABATIC comes from a Greek word that is used to describe
thermodynamic processes that exchange no energy with the environment and therefore, no
energy loss in the form of dissipated heat. In real-life computing, such ideal process cannot be
achieved because of the presence of dissipative elements like resistances in a circuit. However,
one can achieve very low energy dissipation by slowing down the speed of operation and only
switching transistors under certain conditions. The signal energies stored in the circuit
capacitances are recycled instead, of being dissipated as heat. The adiabatic logic is also known
as ENERGY RECOVERY CMOS. In the adiabatic switching approach, the circuit energies are
conserved rather than dissipated as heat. Depending on the application and the system
requirements, this approach can sometimes be used to reduce the power dissipation of the digital
systems.
III. ADIABATIC LOGIC FAMILIES:
Practical adiabatic families can be classified as either Partially adiabatic or fully
adiabatic. In partially adiabatic circuit, some charge is allowed to be transferred to the ground,
while in fully adiabatic circuit all the charge on the load capacitance is recovered by the power
supply. Fully adiabatic circuits face so many problems with respect to operating speed and input
power clock synchronization. Different logic families are 2N-2P Adiabatic logic, 2N- 2N2P
Adiabatic Logic, Positive Feedback Adiabatic Logic (PFAL),NMOS Energy Recovery Logic
(NERL), Clocked Adiabatic Logic (CAL),True Single-Phase Adiabatic Logic (TSEL),Source-
coupled Adiabatic Logic (SCAL),Two phase adiabatic static CMOS logic(2PASCL) and fully
adiabatic logic families are ,Pass Transistor Adiabatic Logic (PAL),Split- Rail Charge Recovery
Logic (SCRL). In this project we are going with enhanced 2N-2P adiabatic logic family
compared with 2N-2P,2N-2N2P logic families and conventional cmos logic.
IV.2N-2P ADIABATIC LOGIC FAMILY:
The schematic and simulated waveform of the 2N-2P inverter gate is shown in Fig.2 and
Fig.3 respectively. Initially, input ‘in’ is high and input ‘/in’ is low. When power clock (pck)
rises from zero to VDD, since F is on so output ‘out’ remains ground level. Output ‘/out’ follows
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3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
the pck. When pck reaches at VDD, outputs ‘out’ and ‘/out’ hold logic value zero and VDD
respectively. This output values can be used for the next stage as an inputs. Now pck falls from
VDD to zero, ‘/out’ returns its energy to pck hence delivered charge is recovered. ECRL uses
four phase clocking rule to efficiently recover the charge delivered by pck. For detailed study
follow the reference [4].
2N-2P INVERTER
Fig.2
WAVEFORM FOR 2N-2P INVERTER
Fig.3
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4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
4x4 2N-2P ARRAY MULTIPLIER
WAVEFORM FOR 4x4 2N-2P ARRAY MULTIPLIER
V.2N-2N2P ADIABATIC LOGIC
The schematic and simulated waveform of the 2N-2N2P inverter gate is shown in Fig.4
and Fig.5 respectively The 2N-2N2P logic family was derived from 2N-2P in order to reduce
the coupling effect. The major difference with respect to 2N-2P is that the latch is made by two
pMOSFETs and two nMOSFETs, rather than by only two pMOSFETs as in 2N-2P.The
additional cross-coupled nMOSFET switches lead to non-floating outputs for a large part of the
recovery phase.
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5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
2N-2N2P INVERTER
Fig.4
WAVEFORM FOR 2N-2N2P INVERTER
Fig.5
4x4 2N-2N2P ARRAY MULTIPLIER
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6. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
WAVEFORM FOR 4x4 2N-2N2P ARRAY MULTIPLIER
VI. ENHANCED 2N-2P ADIABATIC LOGIC
The ENHANCED 2N-2P operation consists of
• The pre-resolving phase, when the inputs are preresolved.
• The Evaluate phase, when PC raises and evaluates using the pre-resolved circuit states.
• The Hold phase.
• The Recovery phase.
ENHANCED 2N-2P INVERTER
WAVEFORM FOR ENHANCED 2N-2P INV:
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7. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
4x4 ENHANCED 2N-2P ARRAY MULTIPLIER
WAVEFORM FOR 4x4 ENHANCED 2N-2P ARRAY MULTIPLIER:
VII. COMPARISION RESULTS OF 4x4 ARRAY MULTIPLIERS:
LOGICFAMILIES Avg.
POWER(uw)
CMOS 0.5914806
2N-2P 0.5213958
2N-2N2P 0.5114439
ENHANCED2N-2P 0.3460064
VIII. CONCLUSION
The different parameter variations against adiabatic logic families are investigated, which
shows that adiabatic logic families highly depend upon its. But less power consumption in
adiabatic logic families can be still achieved than CMOS logic over the wide range of parameter
variations. Enhanced 2n-2p logic shows better energy savings than other families at the 100Mhz
frequency. Hence adiabatic logic families can be used for low power application over the wide
range of applications.
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8. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 3, October- December (2012), © IAEME
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[3] B. Voss and M. Glesner, “A low power
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[4] Y. Moon and D.K. Jeong, “An efficient charge recovery logic circuit,” IEEE J. Solid-State
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[6] J. S. Denker, “A review of adiabatic computing,” in IEEE Symp. On Low Power Electronics,
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[7] T. Gabara, “Pulsed Power Supply CMOS,” Technical Digest IEEE Symposium Low Power
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