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RISC & CISC
ARCHITECTURE
‫الطالب‬ ‫إعداد‬:
‫مطر‬ ‫إبراهيم‬ ‫حيدر‬
‫النظم‬ ‫و‬ ‫السيطرة‬ ‫قسم‬/‫حسابات‬
Contents
1. Introduction.
2. What is RISC and CISC?
3. RISC Architecture.
4. Typical Features of RISC Architecture.
5. CISC Architecture.
6. Typical Features of CISC Architecture.
7. SEMANTIC GAP.
8. The Advantages and Disadvantages of RISC and
CISC.
9. Comparison Between RISC and CISC.
10. Examples & Applications of RISC and CISC.
11. Difference between RISC and CISC Architecture
12. References.
1. Introduction
Instruction set or instruction set architecture is the
structure of the computer that provides commands to the
computer to guide the computer for processing data
manipulation. Instruction set consists of instructions,
addressing modes, native data types, registers, interrupt,
exception handling and memory architecture. Instruction
set can be emulated in software by using an interpreter or
built into hardware of the processor. Instruction Set
Architecture can be considered as a boundary between
the software and hardware.
Instruction set of Processor
Classification of microcontrollers and
microprocessors can be done based on
the RISC and CISC instruction set
architecture.
Instruction set specifies processor
functionality including the operations
supported by the processor, storage
mechanisms of the processor, and the
way of compiling the programs to the
processor.
2. What is RISC and CISC?
The RISC and CISC can be expanded as follows:
RISC represents the Reduced Instruction Set Computer
CISC represents the Complex Instruction Set Computer.
3. RISC Architecture
The microcontroller architecture that utilizes small and
highly optimized set of instructions is termed as the
Reduced Instruction Set Computer or simply called as
RISC. It is also called as LOAD/STORE architecture.
RISC chips evolved around the mid-1970 as a reaction at
CISC chips. In 70's, John Cocke at IBM's T.J Watson
Research Center provided the fundamental concepts of RISC,
the idea came from the IBM 801 minicomputer built in 1971
which is used as a fast controller in a very large telephone
switching system.
 This chip contained many traits a later RISC chip should
have: few instructions, fix-sized instructions in a fixed format,
execution on a single cycle of a processor and a Load / Store
architecture.
 These ideas were further refined and articulated by a
group at University Of California Berkeley led by David
Patterson, who coined the term "RISC".
They realized that RISC promised higher performance,
less cost and faster design time.
The simple load/store computers such as MIPS are
commonly called RISC architectures. David A. Patterson
was the finder of the term RISC, after that John L.
Hennessy invented the MIPS architecture to represent
RISC
RISC Architecture
4. Typical Features of RISC Architecture
1. Pipelining technique of RISC, executes multiple parts or stages of
instructions simultaneously such that every instruction on the
CPU is optimized. Hence, the RISC processors have Clock per
Instruction of one cycle, and this is called as One Cycle
Execution.
2. It optimizes the usage of register with more number of registers
in the RISC and more number of interactions within the memory
can be prevented.
3. Simple addressing modes, even complex addressing can be
done by using arithmetic AND/ OR logical operations.
4. It simplifies the compiler design by using identical general
purpose registers which allows any register to be used in
any context.
5. For efficient usage of the registers and optimization of the
pipelining uses, reduced instruction set is required.
6. The number of bits used for the opcode is reduced.
7. In general there are 32 or more registers in the RISC.
5. CISC Architecture
The main intend of the CISC processor architecture is
to complete task by using less number of assembly
lines.
For this purpose, the processor is built to execute a
series of operations.
Complex instruction is also termed as MULT, which
operates memory banks of a computer directly
without making the compiler to perform storing and
loading functions.
CISC computers are based on a complex instruction set in
which instructions are executed by microcode.
Microcode allows developers to change hardware designs
and still maintain backward compatibility with instructions
for earlier computers by changing only the microcode, thus
make a complex instruction set possible and flexible.
Although CISC designs allow a lot of hardware flexibility,
the supporting of microcode slows microprocessor
performance because of the number of operations that must
be performed to execute each CISC instruction.
A CISC instruction set typically includes many instructions
with different sizes and execution cycles, which makes CISC
instructions harder to pipeline.
From the 60's CISC microprocessors became prevalent, each
successive processor having more and more complicated
hardware and more and more complex instruction sets.
This trend started from Intel 80486, Pentium MMX to
Pentium III.
CISC Architecture
6. Typical Features of CISC Architecture
1. To simplify the computer architecture, CISC supports
microprogramming.
2. CISC have more number of predefined instructions which
makes high level languages easy to design and implement.
3. CISC consists of less number of registers and more number of
addressing modes, generally 5 to 20.
4. CISC processor takes varying cycle time for execution of
instructions – multi-clock cycles.
5. Because of the complex instruction set of the CISC, the
pipelining technique is very difficult.
6. CISC consists of more number of instructions, generally
from 100 to 250.
7. Special instructions are used very rarely.
8. Operands in memory are manipulated by instructions.
7. SEMANTIC GAP
Both RISC and CISC architectures have been developed
as an attempt to cover the semantic gap.
With an objective of improving efficiency of software
development, several powerful programming languages
have come up, viz., Ada, C, C++, Java, etc.
Semantic Gap
They provide a high level of abstraction, conciseness and
power. By this evolution the semantic gap grows.
To enable efficient compilation of high level language
programs, CISC and RISC designs are the two options.
CISC designs involve very complex architectures,
including a large number of instructions and addressing
modes, whereas RISC designs involve simplified
instruction set and adapt it to the real requirements of user
programs.
CISC and RISC Design
8. The Advantages and Disadvantages
of RISC and CISC
The Advantages of RISC architecture
1. RISC architecture has a set of instructions, so high-level
language compilers can produce more efficient code
2. It allows freedom of using the space on microprocessors
because of its simplicity.
3. Many RISC processors use the registers for passing
arguments and holding the local variables.
4. RISC functions use only a few parameters, and the RISC
processors cannot use the call instructions, and
therefore, use a fixed length instruction which is easy to
pipeline.
5. The speed of the operation can be maximized and the
execution time can be minimized.
Very less number of instructional formats, a few
numbers of instructions and a few addressing modes are
needed.
The Disadvantages of RISC architecture
1. Mostly, the performance of the RISC processors depends on the
programmer or compiler as the knowledge of the compiler plays a vital
role while changing the CISC code to a RISC code
2. While rearranging the CISC code to a RISC code, termed as a code
expansion, will increase the size. And, the quality of this code
expansion will again depend on the compiler, and also on the machine’s
instruction set.
3. The first level cache of the RISC processors is also a disadvantage of
the RISC, in which these processors have large memory caches on the
chip itself. For feeding the instructions, they require very fast memory
systems.
Advantages of CISC architecture
1. Microprogramming is easy assembly language to implement,
and less expensive than hard wiring a control unit.
2. The ease of microcoding new instructions allowed designers to
make CISC machines upwardly compatible:
3. As each instruction became more accomplished, fewer
instructions could be used to implement a given task.
Disadvantages of CISC architecture
1. The performance of the machine slows down due to the
amount of clock time taken by different instructions will be
dissimilar
2. Only 20% of the existing instructions is used in a typical
programming event, even though there are various
specialized instructions in reality which are not even used
frequently.
9. Comparison Between RISC and CISC
The RISC processors have a smaller set of instructions
with few addressing modes.
The CISC processors have a larger set of instructions with
many addressing modes.
RISC Vs CISC
Memory Unit
RISC has no memory unit and uses a separate hardware to
implement instructions. CISC has a memory unit to implement
complex instructions
Program
RISC has a hard-wired unit of programming. CISC has a
microprogramming unit
Design
RISC is a complex compiler design. CISC is an easy compiler
design
Calculations
RISC calculations are faster and more precise. CISC
calculations are slow and precise
Decoding
RISC decoding of instructions is simple. CISC decoding of
instructions is complex
Time
Execution time is very less in RISC. Execution time is very
high in CISC.
External memory
RISC does not require external memory for calculations. CISC
requires external memory for calculations.
Pipelining
RISC Pipelining does function correctly. CISC Pipelining does
not function correctly.
Stalling
RISC stalling is mostly reduced in processors. CISC processors
often stall.
Code Expansion
Code expansion can be a problem in RISC whereas, in CISC,
Code expansion is not a problem.
Disc space
Space is saved in RISC whereas in CISC space is wasted.
10. Examples & Applications of
RISC and CISC
Examples of CISC architecture
VAX,
PDP-11,
Motorola 68k,
desktop PCs on Intel’s x86 architecture.
Examples of RISC architecture
 DEC Alpha,
ARC,
 AMD 29k,
 Atmel AVR,
 Intel i860,
Blackfin,
i960,
Motorola 88000,
MIPS,
PA-RISC,
Power, SPARC,
 SuperH, and ARM too.
Applications of RISC and CISC
RISC is used in high-end applications like video processing,
telecommunications and image processing.
CISC is used in low-end applications such as security
systems, home automation, etc.
11. Difference between RISC and
CISC Architecture
RISC
1. RISC stands for Reduced
Instruction Set Computer.
2. RISC processors have simple
instructions taking about one clock
cycle. The average clock cycle
per instruction (CPI) is 1.5
3. Performance is optimized with
more focus on software
4. It has no memory unit and uses
separate hardware to implement
instructions..
5. It has a hard-wired unit of
programming.
CISC
1. CISC stands for Complex
Instruction Set Computer.
2. CSIC processor has complex
instructions that take up multiple
clocks for execution. The average
clock cycle per instruction (CPI) is
in the range of 2 and 15.
3. Performance is optimized with
more focus on hardware.
4. It has a memory unit to
implement complex instructions.
5. It has a microprogramming unit.
RISC
6. The instruction set is reduced
i.e. it has only a few instructions
in the instruction set. Many of
these instructions are very
primitive.
7. The instruction set has a
variety of different instructions
that can be used for complex
operations.
8. Complex addressing modes
are synthesized using the
software.
9. Multiple register sets are
present
10. RISC processors are highly
pipelined
CISC
6. The instruction set has a
variety of different instructions
that can be used for complex
operations.
7. CISC has many different
addressing modes and can thus
be used to represent higher-
level programming language
statements more efficiently.
8. CISC already supports
complex addressing modes
9. Only has a single register set
10. They are normally not
pipelined or less pipelined
RISC
11. The complexity of RISC lies with
the compiler that executes the
program
12. Execution time is very less
13. Code expansion can be a
problem
14. The decoding of instructions is
simple.
15. It does not require external
memory for calculations
CISC
11. The complexity lies in the
microprogram
12. Execution time is very high
13. Code expansion is not a
problem
14. Decoding of instructions is
complex
15. It requires external memory for
calculations
RISC
16. The most common RISC
microprocessors are Alpha,
ARC, ARM, AVR, MIPS, PA-
RISC, PIC, Power
Architecture, and SPARC.
17. RISC architecture is used
in high-end applications
such as video processing,
telecommunications and
image processing.
CISC
16. Examples of CISC
processors are the
System/360, VAX, PDP-11,
Motorola 68000 family, AMD,
and Intel x86 CPUs.
17. CISC architecture is used
in low-end applications such
as security systems, home
automation, etc.
12. References.
 https://www.elprocus.com/
 https://www.watelectronics.com/
 https://www.listdifferences.com/
 https://www.researchgate.net/publication/201987790_A_New_Tren
d_for_CISC_and_RISC_Architectures?enrichId=rgreq-
00012251f91a927ae86159e486f71f97-
XXX&enrichSource=Y292ZXJQYWdlOzIwMTk4Nzc5MDtBUzo5OTg2MT
cyNjc2MDk3MUAxNDAwODIwMjk5OTc2&el=1_x_2&_esc=publicatio
nCoverPdf
 Yi Gao, Shilang Tang, Zhangli Ding, "Comparison between CISC and
RISC", 2000
 John L. Hennessy, David A. Patterson, "Computer Architecture A
Quantitative Approach", Third Edition, 2006.

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R&c

  • 1. RISC & CISC ARCHITECTURE ‫الطالب‬ ‫إعداد‬: ‫مطر‬ ‫إبراهيم‬ ‫حيدر‬ ‫النظم‬ ‫و‬ ‫السيطرة‬ ‫قسم‬/‫حسابات‬
  • 2. Contents 1. Introduction. 2. What is RISC and CISC? 3. RISC Architecture. 4. Typical Features of RISC Architecture. 5. CISC Architecture.
  • 3. 6. Typical Features of CISC Architecture. 7. SEMANTIC GAP. 8. The Advantages and Disadvantages of RISC and CISC. 9. Comparison Between RISC and CISC. 10. Examples & Applications of RISC and CISC. 11. Difference between RISC and CISC Architecture 12. References.
  • 4. 1. Introduction Instruction set or instruction set architecture is the structure of the computer that provides commands to the computer to guide the computer for processing data manipulation. Instruction set consists of instructions, addressing modes, native data types, registers, interrupt, exception handling and memory architecture. Instruction set can be emulated in software by using an interpreter or built into hardware of the processor. Instruction Set Architecture can be considered as a boundary between the software and hardware.
  • 5. Instruction set of Processor Classification of microcontrollers and microprocessors can be done based on the RISC and CISC instruction set architecture. Instruction set specifies processor functionality including the operations supported by the processor, storage mechanisms of the processor, and the way of compiling the programs to the processor.
  • 6. 2. What is RISC and CISC? The RISC and CISC can be expanded as follows: RISC represents the Reduced Instruction Set Computer CISC represents the Complex Instruction Set Computer.
  • 7. 3. RISC Architecture The microcontroller architecture that utilizes small and highly optimized set of instructions is termed as the Reduced Instruction Set Computer or simply called as RISC. It is also called as LOAD/STORE architecture.
  • 8. RISC chips evolved around the mid-1970 as a reaction at CISC chips. In 70's, John Cocke at IBM's T.J Watson Research Center provided the fundamental concepts of RISC, the idea came from the IBM 801 minicomputer built in 1971 which is used as a fast controller in a very large telephone switching system.  This chip contained many traits a later RISC chip should have: few instructions, fix-sized instructions in a fixed format, execution on a single cycle of a processor and a Load / Store architecture.
  • 9.  These ideas were further refined and articulated by a group at University Of California Berkeley led by David Patterson, who coined the term "RISC". They realized that RISC promised higher performance, less cost and faster design time. The simple load/store computers such as MIPS are commonly called RISC architectures. David A. Patterson was the finder of the term RISC, after that John L. Hennessy invented the MIPS architecture to represent RISC
  • 11. 4. Typical Features of RISC Architecture 1. Pipelining technique of RISC, executes multiple parts or stages of instructions simultaneously such that every instruction on the CPU is optimized. Hence, the RISC processors have Clock per Instruction of one cycle, and this is called as One Cycle Execution. 2. It optimizes the usage of register with more number of registers in the RISC and more number of interactions within the memory can be prevented.
  • 12. 3. Simple addressing modes, even complex addressing can be done by using arithmetic AND/ OR logical operations. 4. It simplifies the compiler design by using identical general purpose registers which allows any register to be used in any context. 5. For efficient usage of the registers and optimization of the pipelining uses, reduced instruction set is required. 6. The number of bits used for the opcode is reduced. 7. In general there are 32 or more registers in the RISC.
  • 13. 5. CISC Architecture The main intend of the CISC processor architecture is to complete task by using less number of assembly lines. For this purpose, the processor is built to execute a series of operations. Complex instruction is also termed as MULT, which operates memory banks of a computer directly without making the compiler to perform storing and loading functions.
  • 14. CISC computers are based on a complex instruction set in which instructions are executed by microcode. Microcode allows developers to change hardware designs and still maintain backward compatibility with instructions for earlier computers by changing only the microcode, thus make a complex instruction set possible and flexible. Although CISC designs allow a lot of hardware flexibility, the supporting of microcode slows microprocessor performance because of the number of operations that must be performed to execute each CISC instruction.
  • 15. A CISC instruction set typically includes many instructions with different sizes and execution cycles, which makes CISC instructions harder to pipeline. From the 60's CISC microprocessors became prevalent, each successive processor having more and more complicated hardware and more and more complex instruction sets. This trend started from Intel 80486, Pentium MMX to Pentium III.
  • 17. 6. Typical Features of CISC Architecture 1. To simplify the computer architecture, CISC supports microprogramming. 2. CISC have more number of predefined instructions which makes high level languages easy to design and implement. 3. CISC consists of less number of registers and more number of addressing modes, generally 5 to 20.
  • 18. 4. CISC processor takes varying cycle time for execution of instructions – multi-clock cycles. 5. Because of the complex instruction set of the CISC, the pipelining technique is very difficult. 6. CISC consists of more number of instructions, generally from 100 to 250. 7. Special instructions are used very rarely. 8. Operands in memory are manipulated by instructions.
  • 19. 7. SEMANTIC GAP Both RISC and CISC architectures have been developed as an attempt to cover the semantic gap. With an objective of improving efficiency of software development, several powerful programming languages have come up, viz., Ada, C, C++, Java, etc.
  • 21. They provide a high level of abstraction, conciseness and power. By this evolution the semantic gap grows. To enable efficient compilation of high level language programs, CISC and RISC designs are the two options. CISC designs involve very complex architectures, including a large number of instructions and addressing modes, whereas RISC designs involve simplified instruction set and adapt it to the real requirements of user programs.
  • 22. CISC and RISC Design
  • 23. 8. The Advantages and Disadvantages of RISC and CISC
  • 24. The Advantages of RISC architecture 1. RISC architecture has a set of instructions, so high-level language compilers can produce more efficient code 2. It allows freedom of using the space on microprocessors because of its simplicity.
  • 25. 3. Many RISC processors use the registers for passing arguments and holding the local variables. 4. RISC functions use only a few parameters, and the RISC processors cannot use the call instructions, and therefore, use a fixed length instruction which is easy to pipeline. 5. The speed of the operation can be maximized and the execution time can be minimized. Very less number of instructional formats, a few numbers of instructions and a few addressing modes are needed.
  • 26. The Disadvantages of RISC architecture 1. Mostly, the performance of the RISC processors depends on the programmer or compiler as the knowledge of the compiler plays a vital role while changing the CISC code to a RISC code 2. While rearranging the CISC code to a RISC code, termed as a code expansion, will increase the size. And, the quality of this code expansion will again depend on the compiler, and also on the machine’s instruction set. 3. The first level cache of the RISC processors is also a disadvantage of the RISC, in which these processors have large memory caches on the chip itself. For feeding the instructions, they require very fast memory systems.
  • 27. Advantages of CISC architecture 1. Microprogramming is easy assembly language to implement, and less expensive than hard wiring a control unit. 2. The ease of microcoding new instructions allowed designers to make CISC machines upwardly compatible: 3. As each instruction became more accomplished, fewer instructions could be used to implement a given task.
  • 28. Disadvantages of CISC architecture 1. The performance of the machine slows down due to the amount of clock time taken by different instructions will be dissimilar 2. Only 20% of the existing instructions is used in a typical programming event, even though there are various specialized instructions in reality which are not even used frequently.
  • 29. 9. Comparison Between RISC and CISC The RISC processors have a smaller set of instructions with few addressing modes. The CISC processors have a larger set of instructions with many addressing modes.
  • 31. Memory Unit RISC has no memory unit and uses a separate hardware to implement instructions. CISC has a memory unit to implement complex instructions Program RISC has a hard-wired unit of programming. CISC has a microprogramming unit Design RISC is a complex compiler design. CISC is an easy compiler design
  • 32. Calculations RISC calculations are faster and more precise. CISC calculations are slow and precise Decoding RISC decoding of instructions is simple. CISC decoding of instructions is complex Time Execution time is very less in RISC. Execution time is very high in CISC.
  • 33. External memory RISC does not require external memory for calculations. CISC requires external memory for calculations. Pipelining RISC Pipelining does function correctly. CISC Pipelining does not function correctly. Stalling RISC stalling is mostly reduced in processors. CISC processors often stall.
  • 34. Code Expansion Code expansion can be a problem in RISC whereas, in CISC, Code expansion is not a problem. Disc space Space is saved in RISC whereas in CISC space is wasted.
  • 35. 10. Examples & Applications of RISC and CISC
  • 36. Examples of CISC architecture VAX, PDP-11, Motorola 68k, desktop PCs on Intel’s x86 architecture.
  • 37. Examples of RISC architecture  DEC Alpha, ARC,  AMD 29k,  Atmel AVR,  Intel i860, Blackfin, i960, Motorola 88000, MIPS, PA-RISC, Power, SPARC,  SuperH, and ARM too.
  • 38. Applications of RISC and CISC RISC is used in high-end applications like video processing, telecommunications and image processing. CISC is used in low-end applications such as security systems, home automation, etc.
  • 39. 11. Difference between RISC and CISC Architecture
  • 40. RISC 1. RISC stands for Reduced Instruction Set Computer. 2. RISC processors have simple instructions taking about one clock cycle. The average clock cycle per instruction (CPI) is 1.5 3. Performance is optimized with more focus on software 4. It has no memory unit and uses separate hardware to implement instructions.. 5. It has a hard-wired unit of programming. CISC 1. CISC stands for Complex Instruction Set Computer. 2. CSIC processor has complex instructions that take up multiple clocks for execution. The average clock cycle per instruction (CPI) is in the range of 2 and 15. 3. Performance is optimized with more focus on hardware. 4. It has a memory unit to implement complex instructions. 5. It has a microprogramming unit.
  • 41. RISC 6. The instruction set is reduced i.e. it has only a few instructions in the instruction set. Many of these instructions are very primitive. 7. The instruction set has a variety of different instructions that can be used for complex operations. 8. Complex addressing modes are synthesized using the software. 9. Multiple register sets are present 10. RISC processors are highly pipelined CISC 6. The instruction set has a variety of different instructions that can be used for complex operations. 7. CISC has many different addressing modes and can thus be used to represent higher- level programming language statements more efficiently. 8. CISC already supports complex addressing modes 9. Only has a single register set 10. They are normally not pipelined or less pipelined
  • 42. RISC 11. The complexity of RISC lies with the compiler that executes the program 12. Execution time is very less 13. Code expansion can be a problem 14. The decoding of instructions is simple. 15. It does not require external memory for calculations CISC 11. The complexity lies in the microprogram 12. Execution time is very high 13. Code expansion is not a problem 14. Decoding of instructions is complex 15. It requires external memory for calculations
  • 43. RISC 16. The most common RISC microprocessors are Alpha, ARC, ARM, AVR, MIPS, PA- RISC, PIC, Power Architecture, and SPARC. 17. RISC architecture is used in high-end applications such as video processing, telecommunications and image processing. CISC 16. Examples of CISC processors are the System/360, VAX, PDP-11, Motorola 68000 family, AMD, and Intel x86 CPUs. 17. CISC architecture is used in low-end applications such as security systems, home automation, etc.
  • 44. 12. References.  https://www.elprocus.com/  https://www.watelectronics.com/  https://www.listdifferences.com/  https://www.researchgate.net/publication/201987790_A_New_Tren d_for_CISC_and_RISC_Architectures?enrichId=rgreq- 00012251f91a927ae86159e486f71f97- XXX&enrichSource=Y292ZXJQYWdlOzIwMTk4Nzc5MDtBUzo5OTg2MT cyNjc2MDk3MUAxNDAwODIwMjk5OTc2&el=1_x_2&_esc=publicatio nCoverPdf  Yi Gao, Shilang Tang, Zhangli Ding, "Comparison between CISC and RISC", 2000  John L. Hennessy, David A. Patterson, "Computer Architecture A Quantitative Approach", Third Edition, 2006.