1. 496 CHAPTER 12 INTERRUPTS
11. Explain how a type 0 interrupt occurs. CHAPTER 13
12. Where is the interrupt descriptor table located for protected mode operation?
13. Each protected mode interrupt descriptor contains what information?
14.
15.
Describe the differences between a protected and real mode interrupt.
Describe the operation of the BOUND instruction.
Direct Memory Access
16.
17.
Describe the operation of the INTO instruction.
What memory locations contain the vector for an INT 44H instruction? and DMA-Controlled I/O
18. Explain the operation of the IRET instruction.
19. What is the purpose of interrupt vector type number 7?
20. List the events that occur when an interrupt becomes active.
21. Explain the purpose of the interrupt flag (IF).
22. Explain the purpose of the trap flag (TF).
23. How is IF cleared and set?
24. How is TF cleared and set?
25. The NMI interrupt input automatically vectors through which vector type number?
26. Does the INTA signal activate for the NMI pin?
27. The INTR input is _______ -sensitive. INTRODUCTION
28. The NMI input is _______ -sensitive.
29. When the INTA signal becomes a logic 0, it indicates that the microprocessor is waiting for In previous chapters, we discussed basic and interrupt-processed I/O. Now we turn to the final
an interrupt __________ number to be placed on the data bus (DO-D7). form of I/O called direct memory access (DMA). The DMA I/O technique provides direct ac-
30. What is a FIFO? cess to the memory while the microprocessor is temporarily disabled. This allows data to be
31. Develop a circuit that places interrupt type number 86H on the data bus in response to the transferred between memory and the I/O device at a rate that is limited only by the speed of the
INTR input. memory components in the system or the DMA controller. The DMA transfer speed can ap-
32. Develop a circuit that places interrupt type number CCH on the data bus in response to the proach 32-40 M-byte transfer rates with today's high-speed RAM memory components.
INTR input. DMA transfers are used for many purposes, but more common are DRAM refresh, video
33. Explain why pull-up resistors on DO-D7 cause the microprocessor to respond with interrupt displays for refreshing the screen, and disk memory system reads and writes. The DMA
vector type number FFH for the INTA pulse. transfer is also used to do high-speed memory-to-memory transfers.
34. What is a daisy-chain? This chapter also explains the operation of disk memory systems and video systems that
35. Why must interrupting devices be polled in a daisy-chained interrupt system? are often DMA-processed. Disk memory includes floppy, fixed, and optical disk storage. Video
36. Whatisthe8259A? systems include digital and analog monitors.
37. How many 8259As are required to have 64 interrupt inputs?
38. What is the purpose of the IRO-IR7 pins on the 8259A?
39. When are the CAS2-CASO pins used on the 8259A? CHAPTER OBJECTIVES
40. Where is a slave INT pin connected on the master 8259A in a cascaded system?
41. WhatisanlCW? Upon completion of this chapter, you will be able to:
42. What is an OCW?
1. Describe a DMA transfer.
43. How many ICWs are needed to program the 8259A when operated as a single master in a
2. Explain the operation of the HOED and HEDA direct memory access control signals.
system?
3. Explain the function of the 8237 DMA controller when used for DMA transfers.
44. Where is the vector type number stored in the 8259A?
4. Program the 8237 to accomplish DMA transfers.
45. Where is the sensitivity of the IR pins programmed in the 8259A?
5. Describe the disk standards found in personal computer systems.
46. What is the purpose of ICW1?
6. Describe the various video interface standards that are found in the personal computer.
47. What is a non-specific EOI?
48. Explain priority rotation in the 8259A.
49. What is the purpose of IRR in the 8259A?
50. At which I/O ports is the master 8259A PIC found in the personal computer?
51. At which I/O ports is the slave 8259A found in the personal computer? 13-1 BASIC DMA OPERATION
Two control signals are used to request and acknowledge a direct memory access (DMA)
transfer in the microprocessor-based system. The HOED pin is an input that is used to request a
DMA action and the HEDA pin is an output that acknowledges the DMA action. Figure 13-1
shows the timing that is typically found on these two DMA control pins.
497

2. 498 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-2 THE 8237 DMA CONTROLLER 499
FIGURE 13-1 HOLD and orT. FIGURE 13-2 A circuit that Vcc
HLDA timing for the micro- generates system control sig-
CLK
processor. nals in a DMA environment.
10K
HOLD
2 1A 4 IPlRP
, 3 1B 1Y
HLDA W/R l[02 5 2A
2Y
7
IOWC
6 2B
V^ , 11 3A 9
MRpr1-
74F04 10 3B 3Y
14 4A 4Y
1
~ MWTC
Whenever the HOLD input is placed at a logic 1 level, a DMA action (hold) is re- 13 4B
quested. The microprocessor responds, within a few clocks, by suspending the execution of
HL DA 15,,
the program and by placing its address, data, and control bus at their high-impedance states. G
M/iO 1~
A/B
The high-impedance state causes the microprocessor to appear as if it has been removed from
74F257
its socket. This state allows external I/O devices or other microprocessors to gain access to
the system buses so that memory can be accessed directly.
As the timing diagram indicates, HOLD is sampled in the middle of any clocking cycle.
Thus, the hold can take effect any time during the operation of any instruction in the micro-
processor's instruction set. As soon as the microprocessor recognizes the hold, it stops executing 13-2 THE 8237 DMA CONTROLLER
software and enters hold cycles. Note that the HOLD input has a higher priority than the INTR
or NMI interrupt inputs. Interrupts take effect at the end of an instruction, while a HOLD takes The 8237 DMA controller supplies the memory and I/O with control signals and memory ad-
effect in the middle of an instruction. The only microprocessor pin that has a higher priority than dress information during the DMA transfer. The 8237 is actually a special-purpose micro-
a HOLD is the RESET pin. Note that the HOLD input may not be active during a RESET or the processor whose job is high-speed data transfer between memory and the I/O. Figure 13-3
reset is not guaranteed. shows the pin-out and block diagram of the 8237 programmable DMA controller. Although this
The HLDA signal becomes active to indicate that the microprocessor has indeed placed its device may not appear as a discrete component in modern microprocessor-based systems, it does
buses at their high-impedance state, as can be seen in the timing diagram. Note that there are a appear within system controller chip-sets found in most systems. Although not described be-
few clock cycles between the time that HOLD changes and until HLDA changes. The HLDA cause of its complexity, the chip set (82357 ISP or integrated system peripheral controller) and
output is a signal to the external requesting device that the microprocessor has relinquished con- its integral set of two DMA controllers are programmed exactly as the 8237. The ISP also pro-
trol of its memory and I/O space. You could call the HOLD input a DMA request input and the vides a pair of 8259A programmable interrupt controllers for the system.
HLDA output a DMA grant signal. The 8237 is a four-channel device that is compatible with the 8086/8088 microprocessors.
The 8237 can be expanded to include any number of DMA channel inputs, although four chan-
Basic DMA Definitions nels seem to be adequate for many small systems. The 8237 is capable of DMA transfers at rates
of up to 1.6M bytes per second. Each channel is capable of addressing a full 64K-byte section of
Direct memory accesses normally occur between an I/O device and memory without the use of
memory and can transfer up to 64K bytes with a single programming.
the microprocessor. A DMA read transfers data from the memory to the I/O device. A DMA
write transfers data from an I/O device to memory. In both operations, the memory and I/O are
controlled simultaneously, which is why the system contains separate memory and I/O control Pin Definitions
signals. This special control bus structure of the microprocessor allows DMA transfers. A DMA CLK The clock input is connected to the system clock signal as long as that
read causes both the MRDC and IOWC signals to simultaneously activate, transferring data from signal is 5 MHz or less. In the 8086/8088 system, the clock must be
the memory to the I/O device. A DMA write causes the MWTC and IORC signals to both acti- inverted for the proper operation of the 8237.
vate. These control bus signals are available to all microprocessors in the Intel family except the cs Chip select enables the 8237 for programming. The CS pin is normally
8086/8088 system. The 8086/8088 require their generation with either a system controller or a
connected to the output of a decoder. The decoder does not use the
circuit such as the one illustrated in Figure 13-2. The DM A controller provides the memory with
8086/8088 control signal IO/M (M/IO) because it contains the new
its address and a signal from the controller (DACK) selects the I/O device during the DMA
memory and I/O control signals (MEMR, MEMW, IOR, and IOW).
transfer.
The data transfer speed is determined by the speed of the memory device or a DMA con- RESET The reset pin clears the command, status, request, and temporary
troller that often controls DMA transfers. If the memory speed is 100 ns, DMA transfers occur at registers. It also clears the first/last flip-flop and sets the mask register.
rates of up to 1/100 ns or 10 M-bytes per second. If the DMA controller in a system functions at This input primes the 8237 so it is disabled until programmed
a maximum rate of 5 MHz and we still use 100 ns memory, the maximum transfer rate is 5 MHz otherwise.
because the DMA controller is slower than the memory. In many cases, the DMA controller READY A logic 0 on the ready input causes the 8237 to enter wait states for
slows the speed of the system when DMA transfers occur. slower memory and/or I/O components.

3. CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-2 THE 8237 DMA CONTROLLER 501
500
ADSTB Address strobe functions as ALE, except that it is used by the DMA
controller to latch address bits A15-A8 during the DMA transfer.
MEMR Memory read is an output that causes memory to read data during a
DMA read cycle.
MEMW Memory write is an output that causes memory to write data during a
DMA write cycle.
Internal Registers
CAR The current address register is used to hold the 16-bit memory
address used for the DMA transfer. Each channel has its own current
address register for this purpose. When a byte of data is transferred
during a DMA operation, the CAR is either incremented or
decremented, depending on how it is programmed.
CWCR The current word count register programs a channel for the number
of bytes (up to 64K) transferred during a DMA action. The number
loaded into this register is one less than the number of bytes transferred.
FIGURE 13-3 The 8237A-5 programmable DMA controller, (a) Block diagram, and (b) pin-out. For example, if a 10 is loaded into the CWCR, then 11 bytes are
(Courtesy of Intel Corporation.) transferred during the DMA action.
BA and BWC The base address (BA) and base word count (BWC) registers are used
HLDA A hold acknowledge signals the 8237 that the microprocessor has when auto-initialization is selected for a channel. In the auto-
relinquished control of the address, data, and control buses. initialization mode, these registers are used to reload both the CAR and
CWCR after the DMA action is completed. This allows the same count
DREQ3-DREQO The DMA request inputs are used to request a DMA transfer for each
and address to be used to transfer data from the same memory area.
of the four DMA channels. Because the polarity of these inputs is
programmable, they are either active-high or active-low inputs. CR The command register programs the operation of the 8237 DMA
controller. Figure 13-4 depicts the function of the command register.
DB7-DBO The data bus pins are connected to the microprocessor data bus
connections and are used during the programming of the DMA The command register uses bit position 0 to select the memory-to-
memory DMA transfer mode. Memory-to-memory DMA transfers use
controller.
DMA channel 0 to hold the source address and DMA channel 1 to hold the
IOR I/O read is a bi-directional pin used during programming and during a destination address. (This is similar to the operation of a MOVSB instruc-
DMA write cycle. tion.) A byte is read from the address accessed by channel 0 and saved
IOW I/O write is a bi-directional pin used during programming and during a
DMA read cycle.
FIGURE 13-4 8237 A-5 7 6 5 4 3 2 1 (H -Bit Number
EOF End-of-process is a bi-directional signal that is used as an input to
terminate a DMA process or as an output to signal the end of the DMA
command register. (Courtesy i.i.u.i.iTTi
transfer. This input is often used to interrupt a DMA transfer at the end
of a DMA cycle.
of Intel Corporation.)
k o Memory-to memory disable
1 Memory-to-memory enable
' 0 Channel 0 address hold disable
A3-AO These address pins select an internal register during programming and
also provide part of the DMA transfer address during a DMA action. .X Ifbit0 = 0
___ T 0 Controller enable
A7-A4 These address pins are outputs that provide part of the DMA transfer L1 Controller disable
address during a DMA action. '0 Normal timing
HRQ Hold request is an output that connects to the HOLD input of the
.X If bit 0 = 1
microprocessor in order to request a DMA transfer.
F 0 Fixed priority
DACK3-DACKO DMA channel acknowledge outputs acknowledge a channel DMA L 1 Rotating priority
request. These outputs are programmable as either active-high or active- I" 0 Late write selection
low signals. The DACK outputs are often used to select the DMA
LX If bit 3 = 1
controlled I/O device during the DMA transfer.
T0 DREQ sense active hiah
AEN The address enable signal enables the DMA address latch connected to L1 DREQ sense active low
the DB7-DBO pins on the 8237. It is also used to disable any buffers in f0 DACK sense active low
the system connected to the microprocessor. L1 DACK sense active high

4. 13-2 THE 8237 DMA CONTROLLER 503
502 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O
within the 8237 in a temporary holding register. Next, the 8237 initiates FIGURE 13-6 8237A-5 re- 5 4 3 2 1 0 ^ -Bit Number
quest register. (Courtesy of
a memory write cycle, in which the contents of the temporary holding
Intel Corporation.)
register are written into the address selected by DMA channel 1. The 00 Select channel 0
number of bytes transferred is determined by the channel 1 count register. 01 Select channel 1
10 Select channel 2
The channel 0 address hold enable bit (bit position 1) programs 11 Select channel 3
channel 0 for memory-to-memory transfers. For example, if you must 0 Reset request bit
fill an area of memory with data, channel 0 can be held at the same 1 Set request bit
address while channel 1 changes for memory-to-memory transfer. This
copies the contents of the address accessed by channel 0 into a block of
EOF is input or until the DREQ input becomes inactive. Single mode
memory accessed by channel 1.
releases the HOLD after each byte of data is transferred. If the DREQ
The controller enable/disable bit (bit position 2) turns the entire
pin is held active, the 8237 again requests a DMA transfer through the
controller on and off. The normal and compressed bit (bit position 3)
DRQ line to the microprocessor's HOED input. Block mode automati-
determine whether a DMA cycle contains 2 (compressed) or 4 (normal)
cally transfers the number of bytes indicated by the count register for
clocking periods. Bit position 5 is used in normal timing to extend the
the channel. DREQ need not be held active through the block mode
write pulse so it appears one clock earlier in the timing for I/O devices
transfer. Cascade mode is used when more than one 8237 is present
that require a wider write pulse. in a system.
Bit position 4 selects priority for the four DMA channel DREQ
RR The request register is used to request a DMA transfer via software
inputs. In the fixed priority scheme, channel 0 has the highest priority
and channel 3 has the lowest. In the rotating priority scheme, the most (see Figure 13-6). This is very useful in memory-to-memory transfers,
where an external signal is not available to begin the DMA transfer.
recently serviced channel assumes the lowest priority. For example, if
channel 2 just had access to a DMA transfer, it assumes the lowest MRSR The mask register set/reset sets or clears the channel mask, as
priority and channel 3 assumes the highest priority position. Rotating illustrated in Figure 13-7. If the mask is set, the channel is disabled.
priority is an attempt to give all channels equal priority. Recall that the RESET signal sets all channel masks to disable them.
The remaining two bits (bit positions 6 and 7) program the polarities MSR The mask register (see Figure 13-8) clears or sets all of the masks with
of the DREQ inputs and the DACK outputs. one command instead of individual channels, as with the MRSR.
MR The mode register programs the mode of operation for a channel. SR The status register shows the status of each DMA channel (see
Note that each channel has its own mode register (see Figure 13-5), Figure 13-9). The TC bits indicate whether the channel has reached its
as selected by bit positions 1 and 0. The remaining bits of the mode terminal count (transferred all its bytes). Whenever the terminal count
register select the operation, auto-initialization, increment/decrement, is reached, the DMA transfer is terminated for most modes of operation.
and mode for the channel. Verification operations generate the DMA The request bits indicate whether the DREQ input for a given channel
addresses without generating the DMA memory and I/O control signals. is active.
The modes of operation include demand mode, single mode, block
mode, and cascade mode. Demand mode transfers data until an external FIGURE 13-7 8237A-5 7 6 5 4 3 2 1 0-* -Bit Number
mask register set/reset I I I I I I I I I
mode. (Courtesy of Intel
[
7 6 5 4 3 2 1 CH -Bit Number Don't Care 00 Select channel 0 mask bit
FIGURE 13-5 8237A-5 Corporation.)
mode register (Courtesy of
Intel Corporation).
en———— 01
10
11
Select channel 1 mask bit
Select channel 2 mask bit
Select channel 3 mask bit
00 Channel 0 select
01 Channel 1 select "0 Clear mask bit
10 Channel 2 select . 1 Set mask bit
11 Channel 3 select
[" 00 Verify transfer
01 Write transfer FIGURE 13-8 8237A-5 7 6 5 4 3 2 1 0 * - -Bit Number
10 Read transfer mask register. (Courtesy of II I I I I I I I
11 Illegal
LXX If bits 6 and 7 = 11
0 Autoinitialization disable
Intel Corporation.)
Don't Care
k 0 Clear channel 0 mask bit
1 Set channel 0 mask bit
1 Autoinitialization enable
0 Address increment select 4 0 Clear channel 1 mask bit
1 Set channel 1 mask bit
00
01
1 Address decrement select
Demand mode select
Single mode select
-tr 0 Clear channel 2 mask bit
1 Set channel 2 mask bit
0 Clear channel 3 mask bit
10 Block mode select
11 Cascade mode select 1 Set channel 3 mask bit

5. 504 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-2 THE 8237 DMA CONTROLLER 505
FIGURE 13-9 8237A-5 7 6 5 4 3 2 1 -Bit Number Signals
status register. (Courtesy of 1 1 1 1 1 1 1 1 CS IOR IOW A3 A2 A1 AO
Internal Flip-Flop L/atcl DllS UDU-UD/
Intel Corporation.) ' — 1 Channel 0 has reached TC 0 Base and Current Address Write 0 1 0 0 0 0 0 0 AO-A7
1
' ——— 1 Channel 1 has reached TC 0 1 0 0 0 0 0 1 A8-A15
———— 1 Channel 2 has reached TC Current Address Read 0 0 1 0 0 0 0 0 AO-A7
0 0 1 0 0 0 0 1 A8-A15
Base and Current Word Count Write 0 1 0 0 0 0 1 0 WO-W7
0 1 0 0 0 0 1 1 W8-W15
Current Word Count Read 0 0 1 0 0 0 1 0 WO-W7
' ————————————— 1 Channel 3 reauest 0 0 1 0 0 0 1 1 W8-W15
1 Base and Current Address Write 0 1 0 0 0 1 0 0 AO-A7
0 1 0 0 0 1 0 1 A8-A15
Current Address Read 0 0 1 0 0 1 0 0 AO-A7
Software Command 0 0 1 0 0 1 0 1 A8-A15
Base and Current Word Count Write 0 1 0 0 0 1 1 0 WO-W7
Three software commands are used to control the operation of the 8237. These commands do not 0 1 0 0 0 1 1 1 W8-W15
have a binary bit pattern, as do the various control registers within the 8237. A simple output to Current Word Count Read 0 0 1 0 0 1 1 0 WO-W7
the correct port number enables the software command. Figure 13-10 shows the I/O port assign- 0 0 1 0 0 1 1 1 W8-W15
2 Base and Current Address Write 0 1 0 0 1 0 0 0 AO-A7
ments that access all registers and the software commands. 0 1 0 0 1 0 0 1 A8-A15
The function of the software commands are explained in the following list: Current Address Read 0 0 1 0 1 0 0 0 AO-A7
0 0 1 0 1 0 0 1 A8-A15
1. Clear the first/last flip-flop—Clears the first/last (F/L) flip-flop within the 8237. The F/L
Base and Current Word Count Write 0 1 0 0 1 0 1 0 WO-W7
flip-flop selects which byte (low or high order) is read/written in the current address and cur- 0 1 0 0 1 0 1 1 W8-W15
rent count registers. If F/L = 0, the low order byte is selected; if F/L = 1, the high order byte Current Word Count Read 0 0 1 0 1 0 1 0 WO-W7
is selected. Any read or write to the address or count register automatically toggles the F/L 0 0 1 0 1 0 1 1 W8-W15
flip-flop. 3 Base and Current Address Write 0 1 0 0 1 1 0 0 AO-A7
0 1 0 0 1 1 0 1 A8-A15
2. Master clear—Acts exactly the same as the RESET signal to the 8237. As with the RESET
Current Address Read 0 0 1 0 1 1 0 0 AO-A7
signal, this command disables all channels. 0 0 1 0 1 1 0 1 A8-A15
3. Clear mask register—Enables all four DMA channels. Base and Current Word Count Write 0 1 0 0 1 1 1 0 WO-W7
0 1 0 0 1 1 1 1 W8-W15
Programming the Address and Count Registers Current Word Count Read 0 0 1 0 1 1 1 0
1
WO-W7
0 0 1 0 1 1 1 W8-W15
Figure 13-11 illustrates the I/O port locations for programming the count and address registers
for each channel. Notice that the state of the F/L flip-flop determines whether the LSB or MSB FIGURE 13-11 8237A-5 DMA channel I/O port addresses. (Courtesy of Intel Corporation.)
is programmed. If the state of the F/L flip-flop is unknown, the count and address could be pro-
grammed incorrectly. It is also important that the DMA channel be disabled before its address
There are four steps required to program the 8237: (1) the F/L flip-flop is cleared using a
and count are programmed. clear F/L command, (2) the channel is disabled, (3) the LSB and then MSB of the address are
programmed, and (4) the LSB and MSB of the count are programmed. Once these four opera-
FIGURE 13-10 8237 A-5
tions are performed, the channel is programmed and ready to use. Additional programming is re-
Signals
Operation quired to select the mode of operation before the channel is enabled and started.
command and control port as- A3 A2 A1 AO IOR IOW
signments. (Courtesy of Intel 1 0 0 0 0 1 Read Status Register
Corporation.) 1 n 0 0 1 0 Write Command Register The 8237 Connected to the 80X86 Microprocessor
1 0 0 1 0 1 Illegal
1 o 0 1 1 0 Write Request Register Figure 13-12 shows an 80X86-based system that contains the 8237 DMA controller.
1 o 1 0 0 1 Illegal
The address enable (AEN) output of the 8237 controls the output pins of the latches and
1 0 1 0 1 0 Write Single Mask Register Bit
the outputs of the 74LS257 (E). During normal 80X86 operation (AEN = 0), latches A and C and
1 n 1 1 0 1 Illegal
1 0 1 1 1 0 Write Mode Register the multiplexer (E) provide address bus bits A19-A16 and A7-AO. The multiplexer provides the
1 1 0 0 0 1 Illegal system control signals as long as the 80X86 is in control of the system. During a DMA action
1 1 0 0 1 0 Clear Byte Pointer Flip/Flop
(AEN = 1), latches A and C are disabled along with the multiplexer (E). Latches D and B now
1 1 0 1 0 1 Read Temporary Register
provide address bits A19-A16 and A15-A8. Address bus bits A7-AO are provided directly by
1 1 0 1 1 0 Master Clear
1 1 1 0 0 1 Illegal the 8237 and contain a part of the DMA transfer address. The control signals MEMR, MEMW,
1 1 1 0 1 0 Clear Mask Register IOR, and IOW are provided by the DMA controller.
1 1 1 1 0 1 Illegal The address strobe output (ADSTB) of the 8237 clocks the address (A15-A8) into latch D
1 1 1 1 1 0 Write All Mask Register Bits
during the DMA action so that the entire DMA transfer address becomes available on the address

6. o FIGURE 13-12 Complete 8088 minimum mode DMA system.

7. 508 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-2 THE 8237 DMA CONTROLLER 509
TABLE 13-1 DMA page ;Calling parameters:
register ports. Channel Port number (A16-A23) Port number (A24-A31) SI = source address
; DI = destination address
0 87H 487 H CX - count
1 83H 483H ES - segment of source and destination
2 81H 481 H = 0010 LATCHB EQU 10H ; latch B
3 82H 482H = 007C CLEAR_F EQU 7CH ;F/L flip flop
4 8FH 48FH = 0070 CHO_A EQU 7 OH ; channel 0 address
= 0072 CH1_A EQU 72H ; channel 1 address
5 8BH 48BH
= 0073 CH1_C EQU 73H ; channel 1 count
6 89H 489H = 007B MODE EQU 7BH ; mode
7 8AH 48AH = 0078 CMMD EQU 78H ; command
= 007F MASKS EQU 7FH ; masks
= 0079 REQ EQU 79H ; request register
= 0078 STATUS EQU 78H ; status register
bus. Address bus bits A19-A16 are provided by latch B, which must be programmed with these four 0000 TRANS PROC FAR USES AX
address bits before the controller is enabled for the DMA transfer. The DMA operation of the 8237
is limited to a transfer of not more than 64K bytes within the same 64K-byte section of the memory. 0001 8C CO MOV AX,ES ; program latch B
The decoder (F) selects the 8237 for programming and the 4-bit latch (B) for the upper- 0003 8A C4 MOV AL,AH
0005 CO E8 SHR AL, 4
most four address bits. The latch in a PC is called the DMA page register (8-bits) that holds ad- 0008 E6 10 OUT LATCHB , AL
dress bits A16-A23 for a DMA transfer. A high page register also exists, but its address is OOOA E6 7C OUT CLEAR_F , AL ;clear F/L flip-flop
chip-dependent. The port numbers for the DMA page registers are listed in Table 13-1 (these are OOOC 8C CO MOV AX,ES ; program source address
for the Intel ISP). The decoder in this system enables the 8237 for I/O port addresses OOOE Cl EO SHL AX, 4
XX60H-XX7FH, and the I/O latch (B) for ports XXOOH-XX1FH. Notice that the decoder 0011 03 C6 ADD AX, SI ; form source offset
output is combined with the IOW signal to generate an active-high clock for the latch (B). 0013 E6 70 OUT CHO_A,AL
0015 8A C4 MOV AL,AH
During normal 80X86 operation, the DMA controller and integrated circuits B and D are 0017 E6 70 OUT CHO_A, AL
disabled. During a DMA action, integrated circuits A, C, and E are disabled so that the 8237 can
0019 8C CO MOV AX,ES
take control of the system through the address, data, and control buses. 001B Cl EO
; program destination address
SHL AX, 4
In the personal computer, the two DMA controllers are programmed at I/O ports 001E 03 C7 ADD AX,DI ; f orm destination offset
OOOOH-OOOFH for DMA channels 0-3, and at ports OOCOH-OODFH for DMA channels 4-7. 0020 E6 72 OUT CH1_A,AL
0022 8A C4 MOV AL,AH
Note that the second controller is programmed at even addresses only, so the channel 4 base and 0024 E6 72 OUT CH1_A,AL
current address is programmed at I/O port OOCOH and the channel 4 base and current count is
programmed at port OOC2H. The page register, which holds address bits A23-A16 of the DMA 0026 8B Cl MOV AX,CX ; program count
0028 48 DEC- AX
address, are located at I/O ports 0087H (CH-0), 0083H (CH-1), 0081H (CH-2), 0082H (CH-3), 0029 E6 73
; ad just count
OUT CH1_C,AL
(no channel 4), 008BH (CH-5), 0089H (CH-6) and 008AH (CH-7). The page register functions 002B 8A C4 MOV AL,AH
as the address latch described with the examples in this text. 002D E6 73 OUT CH1_C , AL
002F BO 88 MOV AL, 88H ; program mode
Memory-to-Memory Transfer with the 8237 0031 E6 7B OUT MODE , AL
0033 BO 85 MOV AL, 85H
The memory-to-memory transfer is much more powerful than even the automatically repeated 0035 E6 7B OUT MODE , AL
MOVSB instruction. While the repeated MOVSB instruction tables the 8088 4.2 [as per byte, the
0037 BO 01 MOV AL,1 ; enable block transfer
8237 requires only 2.0 |is per byte, which is over twice as fast as a software data transfer. This is 0039 E6 78 OUT CMMD, AL
not true if an 80386, 80846, or Pentium/Pentium Pro is in use in the system.
003B BO OE MOV AL,OEH ; unmask channel 0
Sample Memory-to-Memory DMA Transfer, Suppose that the contents of memory locations 10000H- 003D E6 7F OUT MASKS , AL
13FFFH are to be transferred into memory locations 14000H-17FFFH. This is accomplished with
003F BO 04 MOV AL,4 ; start DMA transfer
a repeated string move instruction, or, at a much faster rate, with the DMA controller. 0041 E6 79 OUT REQ , AL
Example 13-1 illustrates the software required to initialize the 8237 and program latch B in
Figure 13-12 for this DMA transfer. This software is written for an embedded application. For it to . REPEAT ;wait until DMA complete
0043 E4 78 IN AL, STATUS
function in the PC, you must use the port addresses listed in Table 13-1 for the page registers. .UNTIL AL &1
EXAMPLE 13-1 RET
;A procedure that transfers a block of data using the ENDP
;8237A DMA controller in Figure 13-12. This is a
;memory-to-memory block transfer.
Programming the DMA controller requires a few steps, as illustrated in Example 13-1.
The leftmost digit of the 5-digit address is sent to latch B. Next, the channels are programmed

8. 510 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O
13-2 THE 8237 DMA CONTROLLER 511
after the F/L flip-flop is cleared. Note that we use channel 0 as the source and channel 1 as the 0013 8C CO MOV AX,ES ; program source address
destination for a memory-to-memory transfer. The count is next programmed with a value that is 0015 Cl EO 04 SHL AX, 4
0018 03 C7 ADD AX,DI ; form source offset
one less than the number of bytes to be transferred. Next, the mode register of each channel is 001A E6 70 OUT CHO_A,AL
programmed, the command register selects a block move, channel 0 is enabled, and a software 001C 8A C4 MOV AL,AH
DMA request is initiated. Before return is made from the procedure, the status register is tested 001E E6 70 OUT CHO_A,AL
for a terminal count. Recall that the terminal count flag indicates that the DMA transfer is com- 0020 8C CO MOV AX,ES /program destination address
pleted. The TC also disables the channel, preventing additional transfers. 0022 Cl EO 04 SHL AX, 4
0025 03 C7 ADD AX,DI ; f orm destination offset
Sample Memory Fill Using the 8237. In order to fill an area of memory with the same data, the 0027 48 INC AX
channel 0 source register is programmed to point to the same address throughout the transfer. 0028 E6 72 OUT CH1_A,AL
002A 8A C4 MOV AL,AH
This is accomplished with the channel 0 hold mode. The controller copies the contents of this 002C E6 72 OUT CH1_A,AL
single memory location to an entire block of memory addressed by channel 1. This has many
002E 8B Cl MOV AX,CX ; program count
useful applications. 0030 48 DEC AX ; ad just count
For example, suppose that a video display must be cleared. This operation can be per- 0031 48 DEC AX
formed using the DMA controller with the channel 0 hold mode and a memory-to-memory 0032 E6 73 OUT CH1_C , AL
0034 8A C4 MOV AL,AH
transfer. If the video display contains 80 columns and 25 lines, it has 2000 display positions that 0036 E6 73 OUT CH1_C , AL
must be set to 20H (an ASCII space) to clear the screen.
Example 13-2 shows a procedure that clears an area of memory addressed by ES:DI. The 0038 BO 88 MOV AL,88H ; program mode
003A E6 7B OUT MODE , AL
CX register transfers the number of bytes to be cleared to the CLEAR procedure. Notice that this 003C BO 85 MOV AL, 85H
procedure is nearly identical to Example 13-1, except that the command register is programmed 003E E6 7B OUT MODE , AL
so the channel 0 address is held. The source address is programmed as the same address as 0040 BO 03 MOV AL,3 ,- enable block hold transfer
ES:DI, and then the destination is programmed as one location beyond ES:DI. Also note that this 0042 E6 78 OUT CMMD,AL
program is designed to function with the hardware in Figure 13-12 and will not function in the
0044 BO OE MOV AL,OEH ; unmask channel 0
personal computer unless you have the same hardware. 0046 E6 7F OUT MASKS , AL
EXAMPLE 13-2 0048 BO 04 MOV AL,4 ; start DMA transfer
004A E6 79 OUT REQ , AL
A procedure that clears an area of memory using the
8237A DMA controller in Figure 13-12. This is a .REPEAT ;wait until DMA complete
memory-to-memory block transfer with a channel 0 hold. 004C E4 78 IN AL , STATUS
.UNTIL AL &1
Calling parameters: RET
DI = offset address of area cleared
ES = segment address of area cleared
CX = number of bytes cleared
LATCHB EQU 10H latch B
DMA-Processed Printer Interface
CLEAR_F EQU 7CH F/L flip flop
CHO_A EQU 70H channel 0 address Figure 13-13 illustrates the hardware added to Figure 13-12 for a DMA-controlled printer inter-
CH1_A EQU 72H channel 1 address face. Little additional circuitry is added for this interface to a Centronics-type parallel printer. The
CH1_C EQU 73H channel 1 count latch is used to capture the data as it is sent to the printer during the DMA transfer. The write pulse
MODE EQU 7BH mode
CMMD EQU 78H command
passed through to the latch during the DMA action also generates the data strobe (DS) signal to the
MASKS EQU 7FH masks printer through the single-shot. The ACK signal returns from the printer each time it is ready for ad-
REQ EQU 79H request register ditional data. In this circuit, ACK is used to request a DMA action through a flip-flop.
STATUS EQU 78H status register
zero
Notice that the I/O device is not selected by decoding the address on the address bus.
ZERO EQU OH
During the DMA transfer, the address bus contains the memory address and cannot contain the
0000 CLEAR PROC FAR USES AX I/O port address. In place of the I/O port address, the DACK3 output from the 8237 selects the
latch by gating the write pulse through an OR gate.
0001 8C CO MOV AX,ES ; program latch B
0003 8A C4 MOV AL,AH Software that controls this interface is simple because only the address of the data and the
0005 CO E8 04 SHR AL,4 number of characters to be printed are programmed. Once programmed, the channel is enabled,
0008 E6 10 OUT LATCHB , AL and the DMA action transfers a byte at a time to the printer interface each time that the interface
OOOA E6 7C OUT CLEAR_F,AL ; clear F/L flip-flop receives the ACK single from the printer.
The procedure that prints data from the current data segment is illustrated in Exam-
OOOC 2E: AO 0000 MOV AL,CS:ZERO ple 13-3. This procedure programs the 8237, but doesn't actually print anything. Printing is ac-
0010 26: 88.05 MOV ES:[DI],AL ; save zero in first
complished by the DMA controller and the printer interface.

9. 512 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 513
0017 E6 76 OUT CH3_A, AL
FIGURE 13-13 DMA-
0019 8A C4 MOV AL,AH
processed printer interface. 001B E6 76 OUT CH3_A,AL
001D 8B Cl MOV AX,CX ; program count
001F 48 DEC AX ; adjust count
0020 E6 77 OUT CH3_C,AL
0022 8A C4 MOV AL,AH
0024 E6 77 OUT CH3_C,AL
ACK 0026 BO OB MOV AL,OBH ; program mode
0028 E6 7B OUT MODE , AL
002A BO 00 MOV AL, 0 ; enable block hold transfer
002C E6 78 OUT CMMD , AL
002E BO 07 MOV AL,7 ;unmask channel 3
0030 E6 7F OUT MASKS , AL
RET
A secondary procedure is needed to determine whether the DMA action has been com-
pleted. Example 13-4 lists the secondary procedure that tests the DMA controller to see whether
the DMA transfer is complete. The TEST_P procedure is called before programming the DMA
controller to see whether the prior transfer is complete.
EXAMPLE 13-4
;A procedure that tests for a complete DMA action
STATUS EQU 78H ;status register
TEST_P PROC NEAR USES AX
.REPEAT
0001 E4 78 IN AL,STATUS
.UNTIL AL &8
EXAMPLE 13-3
RET
A procedure that prints data via the printer interface
in Figure 13-13. 0009 TEST_P ENDP
Calling parameters:
BX = offset address of printer data Printed data can be double-buffered by first loading buffer 1 with data to be printed. Next,
DS = segment address of printer data the PRINT procedure is called to begin printing buffer 1. Because it takes very little time to pro-
CX = number of bytes to print
gram the DMA controller, a second buffer (buffer 2) can be filled with new printer data while the
= 0010 LATCHB EQU 10H latch B first buffer (buffer 1) is printed by the printer interface and DMA controller. This process is re-
= 007C CLEAR_F EQU 7CH F/L flif> flop peated until all data are printed.
= 0076 CH3_A EQU 76H channel 0 address
= 0077 CH3_C EQU 77H channel 1 count
= 007B MODE EQU 7BH mode
= 0078 CMMD EQU 78H command
= 007F MASKS EQU 7FH masks
= 0079 REQ EQU 79H request register 13-3 SHARED-BUS OPERATION
0000 PRINT PROC FAR USES AX CX BX
Complex present-day computer systems have so many tasks to perform that some systems are
0003 66| B8 00000000 MOV EAX, 0 using more than one microprocessor to accomplish the work. This is called a multiprocessing
0009 8C D8 MOV AX,DS program latch B
EAX, 4
system. We also sometimes call this a distributed system. A system that performs more than one
OOOB 66 | Cl E8 04 SHR
OOOF 50 PUSH AX task is called a multitasking system. In systems that contain more than one microprocessor,
0010 66| Cl E8 10 SHR EAX , 1 6 some method of control must be developed and employed. In a distributed, multiprocessing,
0014 E6 10 OUT LATCHB , AL multitasking environment, each microprocessor accesses two buses: (1) the local bus and (2) the
0016 58 ;program address remote or shared bus.

10. 514 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 515
the system's shared bus space. As mentioned, the shared bus in the personal computer is what we
often call the local bus in the personal computer because it is local to the microprocessor in the
personal computer.
Figure 13-15 shows an 8088 microprocessor that is connected as a remote bus master. The term
bus master applies to any device (microprocessor or otherwise) that can control a bus containing
READY READY
(Local) (Shared)
FIGURE 13-14 A block diagram illustrating the shared and local buses.
This section of the text describes shared bus operation for the 8086 and 8088 microproces-
sors using the 8289 bus arbiter. The 80286 uses the 82289 bus arbiter and the 80386/80486 uses
the 82389 bus arbiter. The Pentium-Pentium II directly support a multiuser environment, as de-
scribed in Chapters 16, 17, and 18. These systems are much more complex and difficult to illus-
trate at this point in the text, but their terminology and operation is essentially the same as for the
The local bus is connected to memory and I/O devices that are directly accessed by a single
microprocessor without any special protocol or access rules. The remote (shared) bus contains
memory and I/O that are accessed by any microprocessor in the system. Figure 13-14 illustrates
this idea with a few microprocessors. Note that the personal computer is also configured in the
same manner as the system in Figure 13-14. The bus master is the main microprocessor in the
personal computer. What we call the local bus in the personal computer is the shared bus in this
illustration. The ISA bus is operated as a slave to the personal computer's microprocessor as well
as any other devices attached to the shared bus.
Types of Buses Defined
The local bus is the bus that is resident to the microprocessor. The local bus contains the resident
or local memory and I/O. All microprocessors studied thus far in this text are considered to be
local bus systems. The local memory and local I/O are accessed by the microprocessor that is di- ADDRESS/DATA A
rectly connected to them. NT-
A shared bus is one that is connected to all microprocessors in the system. The shared bus
is used to exchange data between microprocessors in the system. A shared bus may contain
memory and I/O devices that are accessed by all microprocessors in the system. Access to the FIGURE 13-15 The 8088 operated in the remote mode, illustrating the local and shared bus
shared bus is controlled by some form or arbiter that allows only a single microprocessor to access connections.