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SR Flip-Flop




D Flip-Flop




JK Flip-Flop




T Flip-Flop
SR FLIP-FLOP
module sr_flipflop(s,r,clk,q,qbar);
input s,r,clk;
output q,qbar;
reg q,qbar;
always@(posedge clk)
begin
  case ({s,r})
          2'b00:q=q;
          2'b01:q=1'b0;
          2'b10:q=1'b1;
          2'b11:q=1'bx;
  endcase
          qbar=~q;
 end
 endmodule




D FLIP-FLOP
module D_FF (D,clk,reset,Q);
         input D,clk,reset;
         output Q;
         reg Q;
         always @ (posedge reset or negedge clk)
if (reset)
         Q = 1'b0;
else
         Q = D;
endmodule
JK FLIP-FLOP
module JK_FF (J,K,clk,reset,Q);
      input J,K,clk,reset;
      output Q;
      wire w;
      assign w = (J&~Q)|(~K&Q);
      D_FF dff1(w,clk,reset,Q);
endmodule

module D_FF (D,clk,reset,Q);
         input D,clk,reset;
         output Q;
         reg Q;
         always @ (posedge reset or negedge clk)
if (reset)
         Q = 1'b0;
else
         Q = D;
endmodule




T FLIP-FLOP
module T_FF (T,clk,reset,Q);
      input T,clk,reset;
      output Q;
      wire w;
      assign w = T^Q;
      D_FF dff1(w,clk,reset,Q);
endmodule

module D_FF (D,clk,reset,Q);
         input D,clk,reset;
         output Q;
         reg Q;
         always @ (posedge reset or negedge clk)
if (reset)
         Q = 1'b0;
else
         Q = D;
endmodule

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Sequential Circuits I VLSI 9th experiment

  • 1. SR Flip-Flop D Flip-Flop JK Flip-Flop T Flip-Flop
  • 2. SR FLIP-FLOP module sr_flipflop(s,r,clk,q,qbar); input s,r,clk; output q,qbar; reg q,qbar; always@(posedge clk) begin case ({s,r}) 2'b00:q=q; 2'b01:q=1'b0; 2'b10:q=1'b1; 2'b11:q=1'bx; endcase qbar=~q; end endmodule D FLIP-FLOP module D_FF (D,clk,reset,Q); input D,clk,reset; output Q; reg Q; always @ (posedge reset or negedge clk) if (reset) Q = 1'b0; else Q = D; endmodule
  • 3. JK FLIP-FLOP module JK_FF (J,K,clk,reset,Q); input J,K,clk,reset; output Q; wire w; assign w = (J&~Q)|(~K&Q); D_FF dff1(w,clk,reset,Q); endmodule module D_FF (D,clk,reset,Q); input D,clk,reset; output Q; reg Q; always @ (posedge reset or negedge clk) if (reset) Q = 1'b0; else Q = D; endmodule T FLIP-FLOP module T_FF (T,clk,reset,Q); input T,clk,reset; output Q; wire w; assign w = T^Q; D_FF dff1(w,clk,reset,Q); endmodule module D_FF (D,clk,reset,Q); input D,clk,reset; output Q; reg Q; always @ (posedge reset or negedge clk) if (reset) Q = 1'b0; else Q = D; endmodule