1. G.SAMBASIVA RAO 11KR1A0410
Project associated by
Under The Esteemed Guidance Of
2. Aim Of The Project
The main of our project is design a 32-bit
multiplier by using either CLAA and CSLA
based on area,delay time and power required
for the multiplier.
3. Digital computer arithmetic is an aspect of logic design
with the objective of developing appropriate algorithms in
order to achieve an efficient utilization of the available
The basic operation of additions implemented to the
operation of multiplication.
Multiplications and additions are most widely used arithmetic
computations performed in all digital signal processing
In this project we are going to the performance of different
adders implemented to the multipliers based on area and time
needed for calculation.
4. Carry Look A Head Adder:-
Carry Look Ahead Adder can produce carries faster due to
parallel generation of the carry bits by using additional circuitry. This
technique uses calculation of carry signals in advance, based on input
signals. The result is reduced carry propagation time. For example,
ripple adders are slower but use the least energy.
5. CARRY SELECT ADDER
This adder can be used for the construction of add and shift
multiplier which have lowest area, high speed and minimum
6. Algorithm for array multiplier
In this algorithm we are using two 4-bits one is multiplier second one is multiplicand.
1 0 1 0 multiplier”A”
1 0 1 1 multiplicand “B”
1 0 1 0
1 0 1 0
0 1 1 1 1
0 0 0 0
0 0 1 1 1
1 0 1 0
0 1 1 0 1
0 1 1 0 1 1 1 0
7. Array Multiplier Using CLA &CSA
product register size be 64
bits. Let the
multiplicand registers size be 32
bits. Store the multiplier in least
significant half of the product
Repat the following steps in for
A partial schematic of the
8. VHDL SIMULATIONS
The VHDL simulation of the two multipliers is presented
waveforms, timing diagrams and the design summary for both
the CLAA and CSLA based multipliers.
The VHDL code for both multipliers, using CLAA and CSLA,
11. Delay Analysis
The performance analysis for the delay time of CLAA and
CSLA based multipliers are represented in the form of the
Delay analysis chart
12. Area Delay Product Analysis:-
The performance analysis for the area delay product of CLAA and
CSLA based multipliers are represented in the form of the diagram.
Area delay product analysis chart
The analysis of the project in brief is given in
Delay(ns) Area Delay area
Cost effective compared to other proposed architectures .
High speed, Low power, Less area .
Modified CSLA Can be used to implement Wallace tree
Multiplier and Baug- Wooley multiplier.
Data paths in Microprocessors.
Digital Adders are the core block of DSP
Extensively used in processing units such as
Forming dedicated integer and floating point
In Multiply-accumulate (MAC) structures.
Digital Signal processing.
High speed Integrated circuit.
16. A design and implementation of a VHDL-based 32 bit unsigned
multiplier with CLAA and CSLA was presented.
VHDL was used to model and simulate our multiplier. Using CSLA
improves the overal performance of the multiplier.
Thus a 31 % area delay product reduction is possible with the use of
the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32
bit unsigned parallel multiplier.