5. Prerequisites
● GDB
○ A user-level program in GNU-Toolchain. It's for debug the
program with debug information.
● OpenOCD
○ A user-level program that help GDB to run each debug command
through the corresponding driver.
● Lattice Breakout Board
○ Lattice iCE40HX-8K low cost FPGA Board. Can work with whole
open-source solution, such as yosys, arachne-pnr, icestorm.
● PicoRV32
○ An open-source CPU written by Verilog and base on Risc-V spec.
It's small and only one file, so it'seasy for new learner.
6. Debug System
● DM(Debug Module)
○ The core of the debug system. There are two slave port for
DTM and CPU, and many configurable registers.
○ An Interrupt to make CPU trap into Debug Mode.
● DTM
○ Receive commands from PC through UART and transfer
them to read, write DM registers. (Choosing UART instead
of common JTAGS is because UART-USB device is much
cheaper)
● Debug Mode
○ In this additional CPU mode, actually CPU does not halt, instead, the
CPU keeps run the DM-ROM code and do the commands from
PC(From software view, the CPU is halted).
8. MazuV-Debug-System Implement
● Can do
○ Halt, resume cpu
○ Access general purpose register, and PC
○ Access memory
○ Single step
○ Set software breakpoint
○ Reset and halt at first instruction
● Cannnot do
○ Set hardware breakpoint
○ Set watchpoint
○ …...
9. Issue of MazuV-Debug-System on PicoRV32
● PicoRV32 are not completely match to RiscV spec, such
as no CSR instruction.
● Need independent debug interrupt port
● Walk around single step implementation