ASIC emulation methodology presentation to the UK Synopsys user group conference.

1. Andrew Gardner ASIC prototyping with Certify 12 th May2009

2. 1. Who are we? 2. Why do we prototype an ASIC? 3. A History of FPGAs in Lund and Basingstoke 4. The Process used in Lund and Basingstoke 5. Differences between ASIC and FPGA 6. ASIC partitioning example

11. The FPGA Design Flow PROTOTYPE VOB RTL CERTIFY EDIF NETLIST & CONSTRAINT FILES XILINX PLACE & ROUTE FPGA PROG. BIT-STREAMS 4 4 BOARD DESC. FILE 4 1 DELIVERY TIMING REPORTS Design Files Partition Zippering Timing Info. Pin Assigns … FPGA SPECIFIC VOB ASIC VOB 1 ASIC LEVEL VERIFICATION VOB Regression SW Encryption Keys SRS SRS SRS SRS PROTOTYPE HARDWARE TIMING FILES

13. ARM AHB Bus Matrix Partitioning

14. ARM AHB Bus Matrix Partitioning

15. ARM AHB Bus Matrix Partitioning

16. Example wide-band modem design partition FPGA WCDMA Subsystem A H B - L i t e 52 MHz ( 104 MHz ) 52 MHz MC RAM point to point links I / O Control bus CPU / DSP MMU I / F Memory AHB IF 26 MHz P o i n t t o p o i n t 2 6 M H z Internal Clock Frequency ( 5 ) + / / / - + + 3 . 84 MHz 7 . 68 Mhz 15 . 36 MHz 52 MHz Slot counter 16 chip strobe 16 chip counter ( 104 MHz ) 26 MHz AHB IF 26 MHz AHB IF 26 MHz All WCDMA interrupts 2 6 M H z XXXXXX XXXXXX 26 MHz XXXXXX Rx - stage 1 XXXXXXXXX XXXXXXXXX XXXXXX 52 MHz 15 . 36 MHz XX RAM XXXXXX 15 . 36 MHz 3 . 84 MHz XXXXXX 15 . 36 MHz Path Searcher 1 PS RAM 104 MHz 15 . 36 MHz XXXXXX XX RAM 15 . 36 MHz 7 . 68 MHz 3 . 84 MHz XXXXXX XX RAM 15 . 36 MHz XXXXXX 15 . 36 MHz XXXXXX 1 - XXXXXX XXXXXX 15 . 36 MHz 3 . 84 MHz XXXXXX XXXXXX XXXXXXXXX XXX RAM XXX RAM XXX RAM M M U 52 MHz Slot counter 16 chip strobe 16 chip counter & 8 bits I & Q XXXXXX XXXXXX 15 . 36 MHz 8 bits I & Q , 0 1 16 bits x 2 RSSI XXXXXX 26 MHz XXXXXX XXXXXX XX RAM 16 16 To DIGRF 32 , 2 32 , 2 AHB Bus Matrix 52 MHz Memory with retention Proprietary bus WSS Sub - block s XXXXXX 26 MHz 7 . 68 MHz XXXXXX 26 MHz 7 . 68 MHz XXXXXX 7 . 68 MHz XXXXXX 26 MHz 1 & & IOs TX 32 (+ 3 to DIIGRF ) XXXXXX 26 MHz 15 . 36 MHz 52 MHz 15 . 36 MHz To DIGRF XX RAM 15 . 36 MHz ( 208 MHz ) 52 MHz Dual interface 7 . 68 MHz FIFO ahb 26 to ahb 52 26 MHz 26 MHz 52 MHz 26 MHz 52 MHz 52 MHz 52 MHz 26 MHz 26 MHz FPGA specific FPGA D 3000 Ahb 26 to ahb 52 26 to 52 bridge Wb _ memory _ controller _ bridge _ rec _ play 26 to 52 bridge _ _ _ Wb _ memory _ controller _ bridge _ tx _ stage _ 3 26 to 52 bridge FPGA D2000 D 3000 D 2000 26 MHz 52 MHz 52 MHz 52 MHz ( 104 MHz ) ( 104 MHz ) mm _ ahb _ 26 to 52 _ bridge ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) ( 1 0 4 M H z ) ( 104 MHz ) 52 MHz ( 104 MHz ) _ _ ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) ( 104 MHz ) Psearch 0 _ ahb _ 26 to 52 _ bridge ( 104 MHz ) ( 104 MHz ) ( 208 MHz ) ( 104 MHz ) ( 208 MHz ) ( 52 MHz ) 26 MHz 52 MHz ( 104 MHz ) ( 104 MHz ) ( 1 0 4 M H z ) ( 104 MHz ) ahb 26 to ahb 52 ahb 26 to ahb 52 Strobe width comp . tx 3 _ strb _ width _ comp 3 R E M O V E D H assium _ prototype _ WCDMA _ _ _ / - Doc respons / Approved Product name Rev Date Prepared Reference Document no Sheet - 1 - FPGA D3000

18. 5. Differences between ASIC and FPGA

21. THANK YOU - Questions?