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MIPS 32-bit ALU Design in VHDL
1. Prof. A.B Department of Electrical and Computer Engineering Spring’10
EECE 321 – Computer Organization
Project – Machine Problem 2: MIPS 32-bit ALU [10 points]
In this machine problem, you are asked to implement a 32-bit Arithmetic and Logic Unit (ALU) which will be used later
in the MIPS processor datapath. Appendix C on the companion CD of the textbook includes a basic overview of logic
design, which is essentially a summary of combinational logic design that was covered in EECE 320.
First, review sections C.1 to C.4 in the appendix depending on your background in logic design.
Next, read section C.5, skipping the portions that refer to Verliog. The block diagram of the ALU that you will be
designing is shown in Fig. C.5.12, and the corresponding ALU operations are defined in Fig. C.5.13. The 32-bit ALU
shown in Fig. C.5.12 is a combinational block that does not include a clock signal. Given two 32-bit inputs A and B, the
ALU performs the desired operation according to the ALU function table in Fig. C.5.13 in one cycle. The ALU itself is
composed of 32 identical cells, referred to as 1-bit ALU’s, which are illustrated in Fig. C.5.10.
Your task is to implement a 32-bit combinational ALU as defined above using VHDL. You must use the structural
approach in designing your ALU. Follow the block diagram shown in Fig. C.5.12. First, implement a combinational 1-bit
ALU as shown in Fig. C.5.10. Call your entity ‘ALU1b’. Then assemble 32 copies of these cells to construct the overall
ALU using VHDL ‘generate’ statements. Call the corresponding entity ‘ALU32b’.
Remember that your design must be a combinational block and not a sequential block. Hence, you are not allowed to use
process statements in your VHDL code.
Deliverables:
1. “ALU1b.vhd” that contains the design of a 1-bit ALU.
2. “ALU32b.vhd” that contains the design of the 32-bit ALU. This file must use the 1-bit ALU defined in “ALU1b.vhd”.
3. A testbench file called “ALU32b_tb.vhd” that tests all the functions defined for the 32-bit ALU in Fig. C.5.13.
4. Submit the complete modelsim project file according to the directory structure described in machine problem 1. Your
top directory for this machine problem must be called “mp2”.
0a. mp2mti includes the modelsim project file (call it mp2.prj).
1
2b. Your vhdl source files must be included under mp2src.
3
5. Submit all your designs using Moodle. One member per group needs to submit the design in Moodle.
![Prof. A.B Department of Electrical and Computer Engineering Spring’10
EECE 321 – Computer Organization
Project – Machine Problem 2: MIPS 32-bit ALU [10 points]
In this machine problem, you are asked to implement a 32-bit Arithmetic and Logic Unit (ALU) which will be used later
in the MIPS processor datapath. Appendix C on the companion CD of the textbook includes a basic overview of logic
design, which is essentially a summary of combinational logic design that was covered in EECE 320.
First, review sections C.1 to C.4 in the appendix depending on your background in logic design.
Next, read section C.5, skipping the portions that refer to Verliog. The block diagram of the ALU that you will be
designing is shown in Fig. C.5.12, and the corresponding ALU operations are defined in Fig. C.5.13. The 32-bit ALU
shown in Fig. C.5.12 is a combinational block that does not include a clock signal. Given two 32-bit inputs A and B, the
ALU performs the desired operation according to the ALU function table in Fig. C.5.13 in one cycle. The ALU itself is
composed of 32 identical cells, referred to as 1-bit ALU’s, which are illustrated in Fig. C.5.10.
Your task is to implement a 32-bit combinational ALU as defined above using VHDL. You must use the structural
approach in designing your ALU. Follow the block diagram shown in Fig. C.5.12. First, implement a combinational 1-bit
ALU as shown in Fig. C.5.10. Call your entity ‘ALU1b’. Then assemble 32 copies of these cells to construct the overall
ALU using VHDL ‘generate’ statements. Call the corresponding entity ‘ALU32b’.
Remember that your design must be a combinational block and not a sequential block. Hence, you are not allowed to use
process statements in your VHDL code.
Deliverables:
1. “ALU1b.vhd” that contains the design of a 1-bit ALU.
2. “ALU32b.vhd” that contains the design of the 32-bit ALU. This file must use the 1-bit ALU defined in “ALU1b.vhd”.
3. A testbench file called “ALU32b_tb.vhd” that tests all the functions defined for the 32-bit ALU in Fig. C.5.13.
4. Submit the complete modelsim project file according to the directory structure described in machine problem 1. Your
top directory for this machine problem must be called “mp2”.
0a. mp2mti includes the modelsim project file (call it mp2.prj).
1
2b. Your vhdl source files must be included under mp2src.
3
5. Submit all your designs using Moodle. One member per group needs to submit the design in Moodle.](https://image.slidesharecdn.com/machineproblem2-100307233505-phpapp01/85/Machine-Problem-2-1-320.jpg)
