SlideShare a Scribd company logo
1 of 10
Download to read offline
Industrial Training
    (Six Months/One Semester)
                in
             VLSI Design
(RTL using Verilog & FPGA Design Flow)
                 (Live Project)
  An Initiative by Industry Experts
   from Cadence, Atrenta & Patni
       with qualification from
         IITs and BITS-Pilani

Training Partners of Cadence Design
   Systems and Mentor Graphics
       (Worldwide EDA Giants)




                 DKOP Labs Pvt. Ltd.
                        Knowledge, Operations and Practices

                  C-53, Lower Ground Floor, Sector – 2, Noida – 201301
     Tel: 0120-4276796, 0120-4203797; Tel/Fax: 0120-4274237; Mob: +91-9971792797
              Email: info@dkoplabs.com; Web: http://www.dkoplabs.com
MODULE TOPICS
                         MODULE 1: OPERATING SYSTEM - LINUX

1.   Introduction to Linux OS
2.   Managing Files and Directories
3.   ‘Vi’ Text Editor
4.   Managing Documents
5.   Securing Files in Linux


                               MODULE 2: SHELL SCRIPTING

1. Automating Tasks using Shell Scripts
2. Using Conditional Execution in Shell Scripts
3. Managing Repetitive Tasks Using Shell Scripts


                                 MODULE 3: PERL & TCL/TK

1. Introduction
2. Scalar Data
3. Lists and Arrays
4. Subroutines
5. Input and Output
6. Hashes
7. In the World of Regular Expressions
8. Matching with Regular Expressions
9. Processing Text with Regular Expressions
10. Project in TCL-Tk


                         MODULE 4: ADVANCED DIGITAL DESIGN

1. Design Concepts
2. Introduction to Logic
3. Optimized Implementation of Logic Functions
4. Number Representation and Arithmetic Circuits
5. Combinational-Circuits Building Blocks
6. Flip-Flops, Registers, Counters, and Simple Processor
7. Synchronous Sequential Circuits
8. Asynchronous Sequential Circuits
9. Digital System Design
10. Testing of Logic Circuits
11. Computer Aided Design Tools


                                  MODULE 5: VERILOG HDL

1.   Overview of Digital Design with VerilogHDL
2.   Hierarchical Modeling Concepts
3.   Basic Concepts
4.   Modules and Ports
5. Gate-Level Modeling
6. Dataflow Modeling
7. Behavioral Modeling
8. Tasks and Functions
9. Useful Modeling Techniques
10. Timing and Delays
11. Switch-Level Modeling
12. User Defined Primitives
13. Programming Language Interface
14. Advanced Verification Techniques


                              MODULE 6: FPGA DESIGN FLOW

1. FPGA Kit Introduction
2. Special FPGA Resources
      a. Block RAM
      b. DCM (Digital Clock Manager)
      c. Dedicated Arithmetic functions
3. FPGA Kit interfacing and configuration
      a. LCD
      b. PS2 Mouse
      c. VGA Controller
      d. A/D
4. Writing Synthesizable Verilog
5. FPGA Design Flow using Xilinx/Altera FPGA Kit and Xilinx/Altera Tools


                                        MODULE 7: CMOS

1.   Basic MOS Transistor Theory
2.   Combinational MOS Logic Circuits
3.   Sequential MOS Logic Circuits
4.   Layout Design & Rules


                                MODULE 8: PROJECT WORK

1.   Project Study
2.   Design & Implementation using Mentor Graphics/Cadence EDA tools
3.   Presentation
4.   Document submission
5.   Evaluation of Project


                                  MODULE 9: SOFT SKILLS

1.   Resume Writing
2.   Interview Facing Skills
3.   Presentation Preparation & Delivery
4.   Aptitude preparation




                                                                           3/10
PROGRAM DETAILS
Batch Commences on : July 4th, 2011 (Tentative)
Total Seats           : 48 ( 24 per batch )
Duration              : One Semester/Six Months
                        (5 days/week, Mon-Fri, 4 hours/day)
Fees                  : Rs 33,090/- (30,000 + 10.3% service tax) per student
                        (Rs 5,515/- for seat confirmation
                         Rs 16,545/- at the time of joining
                         Rs 11,030/- within 15 days of joining)


                                     TOOLS
State-of-the-art Industry version EDA Tools from Mentor Graphics and Cadence Design
Systems, Xilinx, Windows/Linux based OpenSource EDA tools and demo versions of
some industry tools.

  • Verilog Design & Simulation Tools
  • Schematic Capture & SPICE Simulation Tools
  • MATLAB
  • Xilinx & Altera FPGA Development Kits


                 BENEFITS FOR THE STUDENTS
  • Helps you in understanding the practical and industrial applications of academic
    curriculum

  • Build your knowledge to develop innovative projects during their final year of
    engineering

  • Enhances the Skill-Set in your resume for better placement prospects within the
    semiconductor industry
  • Helping build knowledge and expertise for the aspirants of higher studies abroad
    to face the stiff competition from students of other countries
  • Build your confidence through hands on exposure to various tools & technologies
                                                                                4/10
INFRASTRUCTURE FACILITIES
•   Latest Configuration PCs with TFT Screens
•   Linux Operating System
•   High Speed Internet
•   LAN connecting all the PCs for easy distribution of tutorials etc.
•   LCD & LED Projectors & White Screen
•   Library


                                   DKOP TEAM
• Manu Lauria:
       o Qualification: M.Tech. in Computer Science & Engineering from IIT Delhi (1989-90)
         and B.Tech. in Electrical Engineering from IIT Delhi (1980-1985)

       o Experience: More than 22 years in the Industry with 18 years in the Semiconductor
         industry at Cadence Design Systems and 4 years at ONGC. Rich experience in EDA
         software tools development - responsible for many products from concept to reality.
         Was part of the core leadership team of Cadence’s Noida Center for 13 years. Has
         managed or been part of teams that developed products in the areas of Synthesis,
         Simulation, Custom IC Design, Rule checking, Model Development & Web based
         component/design management.

• Sandeep Gupta:
       o Qualification: M.Tech. in Computer Applications from IIT Delhi and M.Sc.
         Mathematics from IIT Delhi

       o Experience: More than Eighteen years in Semiconductor industry with Thirteen years
         in Cadence Design Systems. Have worked in the R&D of HDL Simulation tools and
         Virtuoso platform. Highly experienced in developing Software for Engineering
         Applications in addition to EDA tools. Proficient in C,C++, Perl, TCL-Tk languages as well
         as HDLs like VHDL, Verilog & SystemVerilog.

• Devender Khari:
       o Qualification: M.E. Computer Science from BITS, Pilani and B.Tech in Computer
         Engineering from Shivaji University.

       o Experience: More than 11 years of experience in software and EDA industry with 8
         years in Cadence Design Systems. Have worked in the R&D of OrCAD suite of tools,
         Allegro Design Editor and Virtuoso Composer. Expert in developing Software for
         Engineering applications as well as Web Technology and Mobile based applications.
         Proficient in C, C++, PHP, .NET and JAVA Languages.

                                                                                              5/10
• Chandrakant Sakharwade:
        o Qualification: M.Tech. in Advanced Electronics from IIT Chennai (1978) and B.Tech.
          in Electronics & Communication Engineering from Visvesvaraya Regional College of
          Engineering (1976)

        o Experience: More than 31 years of professional experience. Have worked as
          Engineering Manager with increasingly responsible positions in Engineering Design,
          Project Management and Engineering Management in Telecom, Embedded Systems,
          Electronic Component Databases (Content), and Electronic Design Automation (EDA)
          and Product Engineering Services domains. Applied engineering principles for
          successful development of multiple products and content. Have worked at Patni
          Computer Systems, Cadence Design Systems, Aspect Development, C-DOT & Tata
          Institute of Fundamental Research.

  • Ajay Sharma:
        o Qualification: M.Sc. In Electronic Science from Electronic Science Department,
          Kurukshetra University(2003)

        o Experience: 6+ years of Research Experience in the field of ASIC Design. Spent 3 years
          in research on Smart Sensor ASICs at SRL, University of Warwick, UK. Contributed in
          the whole flow from Circuit Design to Tapeout. Handled MIT (Ministry of Information
          Technology) initiative project, SMDP-II, at NIT, Jalandhar for year and a half. Played an
          instrumental role in taking designs from Circuit to Layout. Guided Masters and Bachelors
          Projects.

  • Amitav Banerjee:
        o Qualification: B.Tech. In Information Technology from UPTU (2010), Mentor Graphics
          Certification in Electronic Design & Verification using SystemVerilog (2010)

        o Experience: Started his career at DKOP Labs as Software Engineer. Handling multiple
          projects in Web Technology and Systems Programming using C, PHP, .NET, MySQL.


                        INDUSTRY PARTNERSHIPS
CADENCE DESIGN SYSTEMS

     DKOP is Certified Training Partner of Cadence for whole of North India

MENTOR GRAPHICS CORPORATION

     DKOP is Vanguard Partner and HEP (Higher Education Program) Partner of Mentor Graphics
     Corporation.



                                                                                              6/10
AGNISYS

      DKOP is Spark Higher Education Program partner of Agnisys. DKOP students are given live projects from
      Agnisys to work and deliver in tight deadlines.


                                  DKOP PLACEMENTS
Companies where we have placed our students

ST MICROELECTRONICS, GREATER NOIDA

      Kavita Sharma, Banasthali Vidyapeeth

CADENCE DESIGN SYSTEMS, NOIDA

      Sorabh Dung, LIT, Lovely Professional University

      Ruchi Mittal, CDAC

      Rachna Raj, Banasthali University

      Saloni Goel, Banasthali University

      Sachin Kumar, LIT, Lovely Professional University

      Jupinder Kaur, LIT, Lovely Professional University

      Manvi Goel, Banasthali University

      Balveer Singh Koranga, GB Pant Engineering College, Pauri, Uttaranchal

MENTOR GRAPHICS, NOIDA

      Vikas Tomar, ITM, Gurgaon

      Jitendra Aggarwal, Amity University, Noida

AGNISYS, NOIDA

      Sandeep Thakur, Lovely Professional University

      Amit Kapoor, SSIET, Dera Bassi

      Nitin Ahuja, BSAITM, Faridabad

NSYS, DELHI

      Nidhi Gupta, M.P.C.T., Gwalior

      Prishkrit Abrol, DAVIET, Jalandhar


                                                                                                      7/10
Pankaj Talwar, LCET, Ludhiana

      Richa, Banasthali University

      Mamta Rana, Jiwaji University

CIRCUITSUTRA TECHNOLOGIES, NOIDA

      Parvinder Pal Singh, Lovely Professional University

DKOP LABS, NOIDA

      Rahul Kumar, Rai University

      Pushpinder Singh, SVIET – Banud

      Amitav Banerjee, UPTU

RF SILICON, NOIDA

      Nirmal Singh, UPTU

HP, BANGALORE

      Hariom Pandey, UPTU

SASKEN, BANGALORE

      Sumit Gupta, Thapar - Patiala

      Sumit Kumar, Thapar - Patiala

PHOENIX, NOIDA

      Akhilesh Singh, Jiwaji University

RELIANCE, PUNE

      Ajay Gupta, Jiwaji University

OM NANOTECHNOLOGY, GREATER NOIDA

      Mohammed Sharique, Jiwaji University

UNIVERSITIES IN USA, CANADA & GERMANY

      Smriti Gurung

      Subeg Singh

      Binipal Wadhwa
                                                            8/10
Hasan Karkara

Note: Our competitors also hire our graduates!


                               RECOMMENDATIONS
   1. Mr Jitin Sahni
      Manager, HR & Recruitment
      Freescale Semiconductors, Noida
   2. Mr. Harish Pandey
      Marketing Head
      AMDL, Bangalore
   3. Mr. Upender Bhati
      Marketing Head
      AEM India Pvt. Ltd., Noida
   4. Mr Anupam Bakshi
      CEO, AgniSys
      Noida
   5. Mr Umesh Sisodia
      CEO, CircuitSutra Technologies Pvt Ltd
      Noida
   6. Mr Sanjay Chakravarty
      VP, ITAAS Inc
      Noida
   7. Prof Dinesh Sarbahi
      HOD, Electronics & Communication
      VIET, Dadri
   8. Dr. S.N. Saran
      Director
      GNIT, Greater Noida


             DKOP TOUCHED FOLLOWING COLLEGES
We have conducted on-campus programs (Workshops/Trainings/Conferences) at following colleges:

   1.   LOVELY PROFESSIONAL UNIVERSITY, PHAGWARA
   2.   GREATER NOIDA INSTITUTE OF TECHNOLOGY, GREATER NOIDA
   3.   NIT, JALANDHAR
   4.   VISHWESHVARYA INSTITUTE OF ENGINEERING & TECHNOLOGY, DADRI
   5.   LIET ( LAXMI DEVI INSTITUTE OF ENGINEERING & TECHNOLOGY), ALWAR
   6.   SHEKHAWATI ENGINEERING COLLEGE
   7.   ST. MARGARET ENGG. COLLEGE, NEEMRANA
   8.   ITM, BHILWARA
   9.   YMCA, FARIDABAD
                                                                                                9/10
10. BANASTHALI VIDYAPITH
11. CHITKARA INSTITUTE OF ENGG & TECH, RAJPURA
12. DAV INSTITUTE OF ENGG & TECH, JALANDHAR
13. KUMAON ENGINEERING COLLEGE, DWARAHAT
14. GB PANT ENGG COLLEGE, PAURI
15. INSTITUTE OF TECHNOLOGY, PANTNAGAR
16. SACHDEVA COLLEGE OF ENGG, MATHURA
17. COLLEGE OF ENGG, ROORKEE
18. JSS, NOIDA
19. JIIT, NOIDA
20. BS ANANGPURIA, FARIDABAD
21. GRAPHICS ERA UNIVERSITY, DEHRADUN
22. MITRC, ALWAR
23. SIDDHI VINAYAK, ALWAR
24. NC COLLEGE OF ENGG, PANIPAT
25. BITS, BHIWANI
26. SRI SUKHMANI INSTITUTE, DERABASSI
27. SVIET, BANUD
28. LUDHIANA COLLEGE OF ENGG & TECH
29. DESHBHAGAT ENGG COLLEGE
30. SSIET, PATTI
31. RAI UNIVERSITY, FARIDABAD
32. COLLEGE OF ENGG & TECH, KAPURTHALA
33. RIET, JAIPUR
34. ITS, GREATER NOIDA




                                                 10/10

More Related Content

What's hot

AbbyBrownAB_Resume
AbbyBrownAB_ResumeAbbyBrownAB_Resume
AbbyBrownAB_ResumeAbby Brown
 
Announcement Letter Synopsys Summer Internship Program
Announcement Letter Synopsys Summer Internship ProgramAnnouncement Letter Synopsys Summer Internship Program
Announcement Letter Synopsys Summer Internship Programchairperson
 
Training report anish
Training report anishTraining report anish
Training report anishAnish Yadav
 
Core java report
Core java reportCore java report
Core java reportSumit Jain
 
Rubric-based Assessment of Programming Thinking Skills and Comparative Evalua...
Rubric-based Assessment of Programming Thinking Skills and Comparative Evalua...Rubric-based Assessment of Programming Thinking Skills and Comparative Evalua...
Rubric-based Assessment of Programming Thinking Skills and Comparative Evalua...Hironori Washizaki
 
Resume(Juhi Shrivastava)
Resume(Juhi Shrivastava)Resume(Juhi Shrivastava)
Resume(Juhi Shrivastava)25juhi25
 
Cs 1023 lec 1 big idea (week 1)
Cs 1023 lec 1   big idea (week 1)Cs 1023 lec 1   big idea (week 1)
Cs 1023 lec 1 big idea (week 1)stanbridge
 
Resume_Shivendra_Dubey (1)
Resume_Shivendra_Dubey (1)Resume_Shivendra_Dubey (1)
Resume_Shivendra_Dubey (1)Shivendra Dubey
 
vishal new resume
vishal new resumevishal new resume
vishal new resumepruthvi raj
 
Bob fugerer resume
Bob fugerer  resumeBob fugerer  resume
Bob fugerer resumeBob Fugerer
 
Summer Training report at TATA CMC
Summer Training report at TATA CMCSummer Training report at TATA CMC
Summer Training report at TATA CMCPallavi Srivastava
 

What's hot (20)

Satish resume
Satish resume Satish resume
Satish resume
 
Resume
ResumeResume
Resume
 
AbbyBrownAB_Resume
AbbyBrownAB_ResumeAbbyBrownAB_Resume
AbbyBrownAB_Resume
 
Announcement Letter Synopsys Summer Internship Program
Announcement Letter Synopsys Summer Internship ProgramAnnouncement Letter Synopsys Summer Internship Program
Announcement Letter Synopsys Summer Internship Program
 
Updated resume
Updated resumeUpdated resume
Updated resume
 
Modified sd profile june 30
Modified sd profile june 30Modified sd profile june 30
Modified sd profile june 30
 
Chaithra
ChaithraChaithra
Chaithra
 
Training report anish
Training report anishTraining report anish
Training report anish
 
Core java report
Core java reportCore java report
Core java report
 
Rubric-based Assessment of Programming Thinking Skills and Comparative Evalua...
Rubric-based Assessment of Programming Thinking Skills and Comparative Evalua...Rubric-based Assessment of Programming Thinking Skills and Comparative Evalua...
Rubric-based Assessment of Programming Thinking Skills and Comparative Evalua...
 
Subramanyam_Nalam
Subramanyam_NalamSubramanyam_Nalam
Subramanyam_Nalam
 
Resume(Juhi Shrivastava)
Resume(Juhi Shrivastava)Resume(Juhi Shrivastava)
Resume(Juhi Shrivastava)
 
mrg_cv
mrg_cvmrg_cv
mrg_cv
 
Cs 1023 lec 1 big idea (week 1)
Cs 1023 lec 1   big idea (week 1)Cs 1023 lec 1   big idea (week 1)
Cs 1023 lec 1 big idea (week 1)
 
Resume_Shivendra_Dubey (1)
Resume_Shivendra_Dubey (1)Resume_Shivendra_Dubey (1)
Resume_Shivendra_Dubey (1)
 
15
1515
15
 
vishal new resume
vishal new resumevishal new resume
vishal new resume
 
Bob fugerer resume
Bob fugerer  resumeBob fugerer  resume
Bob fugerer resume
 
MSalah_20161010
MSalah_20161010MSalah_20161010
MSalah_20161010
 
Summer Training report at TATA CMC
Summer Training report at TATA CMCSummer Training report at TATA CMC
Summer Training report at TATA CMC
 

Viewers also liked

Final
FinalFinal
Finaljls13
 
Affiliate Summit Vegas 2009
Affiliate Summit Vegas 2009Affiliate Summit Vegas 2009
Affiliate Summit Vegas 2009jtreiber
 
The Pedagogy of Video Marking or Teaching a Wastepaper Bin to Whistle
The Pedagogy of Video Marking or Teaching a Wastepaper Bin to WhistleThe Pedagogy of Video Marking or Teaching a Wastepaper Bin to Whistle
The Pedagogy of Video Marking or Teaching a Wastepaper Bin to Whistlegregorycanderson
 
Professional inquiry
Professional inquiryProfessional inquiry
Professional inquiryAngie Simmons
 
партизанский маркетинг
партизанский маркетингпартизанский маркетинг
партизанский маркетингNata Isaevich
 
Undertaking Cemetery Rehabilitation
Undertaking  Cemetery RehabilitationUndertaking  Cemetery Rehabilitation
Undertaking Cemetery Rehabilitationchicora
 
Media Management
Media ManagementMedia Management
Media ManagementDanielpaul
 
LWT Stage van Sabrina Kouw bij Manage Warnaar
LWT Stage van Sabrina Kouw bij Manage WarnaarLWT Stage van Sabrina Kouw bij Manage Warnaar
LWT Stage van Sabrina Kouw bij Manage WarnaarClusius
 
Policy Committee Training Powerpoint
Policy Committee Training PowerpointPolicy Committee Training Powerpoint
Policy Committee Training Powerpointyouthbuildusa
 
Creativ eby the sea retreat
Creativ eby the sea retreatCreativ eby the sea retreat
Creativ eby the sea retreatAngie Simmons
 
2012 mid year special ed programme report
2012   mid year special ed programme report2012   mid year special ed programme report
2012 mid year special ed programme reportAngie Simmons
 

Viewers also liked (20)

Final
FinalFinal
Final
 
Affiliate Summit Vegas 2009
Affiliate Summit Vegas 2009Affiliate Summit Vegas 2009
Affiliate Summit Vegas 2009
 
Cepre tema 01 ea 2016-ii
Cepre tema 01 ea 2016-iiCepre tema 01 ea 2016-ii
Cepre tema 01 ea 2016-ii
 
Easydeco Business Plan 2000
Easydeco Business Plan 2000Easydeco Business Plan 2000
Easydeco Business Plan 2000
 
Keynote whangerei
Keynote whangereiKeynote whangerei
Keynote whangerei
 
The Pedagogy of Video Marking or Teaching a Wastepaper Bin to Whistle
The Pedagogy of Video Marking or Teaching a Wastepaper Bin to WhistleThe Pedagogy of Video Marking or Teaching a Wastepaper Bin to Whistle
The Pedagogy of Video Marking or Teaching a Wastepaper Bin to Whistle
 
Presentació Caillou Cati
Presentació Caillou CatiPresentació Caillou Cati
Presentació Caillou Cati
 
IoT standardisation
IoT standardisationIoT standardisation
IoT standardisation
 
Professional inquiry
Professional inquiryProfessional inquiry
Professional inquiry
 
Gala08-09
Gala08-09Gala08-09
Gala08-09
 
партизанский маркетинг
партизанский маркетингпартизанский маркетинг
партизанский маркетинг
 
Undertaking Cemetery Rehabilitation
Undertaking  Cemetery RehabilitationUndertaking  Cemetery Rehabilitation
Undertaking Cemetery Rehabilitation
 
Media Management
Media ManagementMedia Management
Media Management
 
5 Slide Challange
5 Slide Challange5 Slide Challange
5 Slide Challange
 
LWT Stage van Sabrina Kouw bij Manage Warnaar
LWT Stage van Sabrina Kouw bij Manage WarnaarLWT Stage van Sabrina Kouw bij Manage Warnaar
LWT Stage van Sabrina Kouw bij Manage Warnaar
 
Ea Presentation
Ea PresentationEa Presentation
Ea Presentation
 
Policy Committee Training Powerpoint
Policy Committee Training PowerpointPolicy Committee Training Powerpoint
Policy Committee Training Powerpoint
 
BEAR In HOME
BEAR     In     HOMEBEAR     In     HOME
BEAR In HOME
 
Creativ eby the sea retreat
Creativ eby the sea retreatCreativ eby the sea retreat
Creativ eby the sea retreat
 
2012 mid year special ed programme report
2012   mid year special ed programme report2012   mid year special ed programme report
2012 mid year special ed programme report
 

Similar to Industrial trainingvlsi design-2011

DKOP Labs Profile
DKOP Labs ProfileDKOP Labs Profile
DKOP Labs Profiledkhari
 
Ankur_Sharma Resume
Ankur_Sharma Resume Ankur_Sharma Resume
Ankur_Sharma Resume Ankur Sharma
 
TedGervaisCEResume
TedGervaisCEResumeTedGervaisCEResume
TedGervaisCEResumeTed Gervais
 
CV_Virendra
CV_VirendraCV_Virendra
CV_Virendratiet
 
Sathish project mgmt_pmp_9+yrs
Sathish project mgmt_pmp_9+yrsSathish project mgmt_pmp_9+yrs
Sathish project mgmt_pmp_9+yrssathish kumar
 
Intake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SDIntake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SDRaNa HaSan
 
Intake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SDIntake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SDMohamed Bayomi
 
Intake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SDIntake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SDRaNa HaSan
 
Electronics Engineer Resume Foramt
Electronics Engineer Resume ForamtElectronics Engineer Resume Foramt
Electronics Engineer Resume ForamtMohammed Irshad S K
 
Rakesh kumar cv_2exp (embedded developer)
Rakesh kumar cv_2exp (embedded developer)Rakesh kumar cv_2exp (embedded developer)
Rakesh kumar cv_2exp (embedded developer)Rakesh Kumar
 

Similar to Industrial trainingvlsi design-2011 (20)

DKOP Labs Profile
DKOP Labs ProfileDKOP Labs Profile
DKOP Labs Profile
 
Anupriya_Mittal_resume
Anupriya_Mittal_resumeAnupriya_Mittal_resume
Anupriya_Mittal_resume
 
VENU_FV
VENU_FVVENU_FV
VENU_FV
 
Daya_CV
Daya_CVDaya_CV
Daya_CV
 
GP_Kashyap_Resume
GP_Kashyap_ResumeGP_Kashyap_Resume
GP_Kashyap_Resume
 
Ankur_Sharma Resume
Ankur_Sharma Resume Ankur_Sharma Resume
Ankur_Sharma Resume
 
AUK - CV WO Ref
AUK - CV WO RefAUK - CV WO Ref
AUK - CV WO Ref
 
resume_CMS
resume_CMSresume_CMS
resume_CMS
 
Resume-MingyangHou-5th
Resume-MingyangHou-5thResume-MingyangHou-5th
Resume-MingyangHou-5th
 
TedGervaisCEResume
TedGervaisCEResumeTedGervaisCEResume
TedGervaisCEResume
 
CV_Virendra
CV_VirendraCV_Virendra
CV_Virendra
 
Lasitha_Konara_CV
Lasitha_Konara_CVLasitha_Konara_CV
Lasitha_Konara_CV
 
Sathish project mgmt_pmp_9+yrs
Sathish project mgmt_pmp_9+yrsSathish project mgmt_pmp_9+yrs
Sathish project mgmt_pmp_9+yrs
 
Intake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SDIntake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SD
 
Intake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SDIntake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SD
 
Intake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SDIntake_35_Professional_Developer_Track_SD
Intake_35_Professional_Developer_Track_SD
 
Praveen Kumar S S.docx(1)
Praveen Kumar S S.docx(1)Praveen Kumar S S.docx(1)
Praveen Kumar S S.docx(1)
 
Electronics Engineer Resume Foramt
Electronics Engineer Resume ForamtElectronics Engineer Resume Foramt
Electronics Engineer Resume Foramt
 
Rakesh kumar cv_2exp (embedded developer)
Rakesh kumar cv_2exp (embedded developer)Rakesh kumar cv_2exp (embedded developer)
Rakesh kumar cv_2exp (embedded developer)
 
Rajendaran
RajendaranRajendaran
Rajendaran
 

Industrial trainingvlsi design-2011

  • 1. Industrial Training (Six Months/One Semester) in VLSI Design (RTL using Verilog & FPGA Design Flow) (Live Project) An Initiative by Industry Experts from Cadence, Atrenta & Patni with qualification from IITs and BITS-Pilani Training Partners of Cadence Design Systems and Mentor Graphics (Worldwide EDA Giants) DKOP Labs Pvt. Ltd. Knowledge, Operations and Practices C-53, Lower Ground Floor, Sector – 2, Noida – 201301 Tel: 0120-4276796, 0120-4203797; Tel/Fax: 0120-4274237; Mob: +91-9971792797 Email: info@dkoplabs.com; Web: http://www.dkoplabs.com
  • 2. MODULE TOPICS MODULE 1: OPERATING SYSTEM - LINUX 1. Introduction to Linux OS 2. Managing Files and Directories 3. ‘Vi’ Text Editor 4. Managing Documents 5. Securing Files in Linux MODULE 2: SHELL SCRIPTING 1. Automating Tasks using Shell Scripts 2. Using Conditional Execution in Shell Scripts 3. Managing Repetitive Tasks Using Shell Scripts MODULE 3: PERL & TCL/TK 1. Introduction 2. Scalar Data 3. Lists and Arrays 4. Subroutines 5. Input and Output 6. Hashes 7. In the World of Regular Expressions 8. Matching with Regular Expressions 9. Processing Text with Regular Expressions 10. Project in TCL-Tk MODULE 4: ADVANCED DIGITAL DESIGN 1. Design Concepts 2. Introduction to Logic 3. Optimized Implementation of Logic Functions 4. Number Representation and Arithmetic Circuits 5. Combinational-Circuits Building Blocks 6. Flip-Flops, Registers, Counters, and Simple Processor 7. Synchronous Sequential Circuits 8. Asynchronous Sequential Circuits 9. Digital System Design 10. Testing of Logic Circuits 11. Computer Aided Design Tools MODULE 5: VERILOG HDL 1. Overview of Digital Design with VerilogHDL 2. Hierarchical Modeling Concepts 3. Basic Concepts 4. Modules and Ports
  • 3. 5. Gate-Level Modeling 6. Dataflow Modeling 7. Behavioral Modeling 8. Tasks and Functions 9. Useful Modeling Techniques 10. Timing and Delays 11. Switch-Level Modeling 12. User Defined Primitives 13. Programming Language Interface 14. Advanced Verification Techniques MODULE 6: FPGA DESIGN FLOW 1. FPGA Kit Introduction 2. Special FPGA Resources a. Block RAM b. DCM (Digital Clock Manager) c. Dedicated Arithmetic functions 3. FPGA Kit interfacing and configuration a. LCD b. PS2 Mouse c. VGA Controller d. A/D 4. Writing Synthesizable Verilog 5. FPGA Design Flow using Xilinx/Altera FPGA Kit and Xilinx/Altera Tools MODULE 7: CMOS 1. Basic MOS Transistor Theory 2. Combinational MOS Logic Circuits 3. Sequential MOS Logic Circuits 4. Layout Design & Rules MODULE 8: PROJECT WORK 1. Project Study 2. Design & Implementation using Mentor Graphics/Cadence EDA tools 3. Presentation 4. Document submission 5. Evaluation of Project MODULE 9: SOFT SKILLS 1. Resume Writing 2. Interview Facing Skills 3. Presentation Preparation & Delivery 4. Aptitude preparation 3/10
  • 4. PROGRAM DETAILS Batch Commences on : July 4th, 2011 (Tentative) Total Seats : 48 ( 24 per batch ) Duration : One Semester/Six Months (5 days/week, Mon-Fri, 4 hours/day) Fees : Rs 33,090/- (30,000 + 10.3% service tax) per student (Rs 5,515/- for seat confirmation Rs 16,545/- at the time of joining Rs 11,030/- within 15 days of joining) TOOLS State-of-the-art Industry version EDA Tools from Mentor Graphics and Cadence Design Systems, Xilinx, Windows/Linux based OpenSource EDA tools and demo versions of some industry tools. • Verilog Design & Simulation Tools • Schematic Capture & SPICE Simulation Tools • MATLAB • Xilinx & Altera FPGA Development Kits BENEFITS FOR THE STUDENTS • Helps you in understanding the practical and industrial applications of academic curriculum • Build your knowledge to develop innovative projects during their final year of engineering • Enhances the Skill-Set in your resume for better placement prospects within the semiconductor industry • Helping build knowledge and expertise for the aspirants of higher studies abroad to face the stiff competition from students of other countries • Build your confidence through hands on exposure to various tools & technologies 4/10
  • 5. INFRASTRUCTURE FACILITIES • Latest Configuration PCs with TFT Screens • Linux Operating System • High Speed Internet • LAN connecting all the PCs for easy distribution of tutorials etc. • LCD & LED Projectors & White Screen • Library DKOP TEAM • Manu Lauria: o Qualification: M.Tech. in Computer Science & Engineering from IIT Delhi (1989-90) and B.Tech. in Electrical Engineering from IIT Delhi (1980-1985) o Experience: More than 22 years in the Industry with 18 years in the Semiconductor industry at Cadence Design Systems and 4 years at ONGC. Rich experience in EDA software tools development - responsible for many products from concept to reality. Was part of the core leadership team of Cadence’s Noida Center for 13 years. Has managed or been part of teams that developed products in the areas of Synthesis, Simulation, Custom IC Design, Rule checking, Model Development & Web based component/design management. • Sandeep Gupta: o Qualification: M.Tech. in Computer Applications from IIT Delhi and M.Sc. Mathematics from IIT Delhi o Experience: More than Eighteen years in Semiconductor industry with Thirteen years in Cadence Design Systems. Have worked in the R&D of HDL Simulation tools and Virtuoso platform. Highly experienced in developing Software for Engineering Applications in addition to EDA tools. Proficient in C,C++, Perl, TCL-Tk languages as well as HDLs like VHDL, Verilog & SystemVerilog. • Devender Khari: o Qualification: M.E. Computer Science from BITS, Pilani and B.Tech in Computer Engineering from Shivaji University. o Experience: More than 11 years of experience in software and EDA industry with 8 years in Cadence Design Systems. Have worked in the R&D of OrCAD suite of tools, Allegro Design Editor and Virtuoso Composer. Expert in developing Software for Engineering applications as well as Web Technology and Mobile based applications. Proficient in C, C++, PHP, .NET and JAVA Languages. 5/10
  • 6. • Chandrakant Sakharwade: o Qualification: M.Tech. in Advanced Electronics from IIT Chennai (1978) and B.Tech. in Electronics & Communication Engineering from Visvesvaraya Regional College of Engineering (1976) o Experience: More than 31 years of professional experience. Have worked as Engineering Manager with increasingly responsible positions in Engineering Design, Project Management and Engineering Management in Telecom, Embedded Systems, Electronic Component Databases (Content), and Electronic Design Automation (EDA) and Product Engineering Services domains. Applied engineering principles for successful development of multiple products and content. Have worked at Patni Computer Systems, Cadence Design Systems, Aspect Development, C-DOT & Tata Institute of Fundamental Research. • Ajay Sharma: o Qualification: M.Sc. In Electronic Science from Electronic Science Department, Kurukshetra University(2003) o Experience: 6+ years of Research Experience in the field of ASIC Design. Spent 3 years in research on Smart Sensor ASICs at SRL, University of Warwick, UK. Contributed in the whole flow from Circuit Design to Tapeout. Handled MIT (Ministry of Information Technology) initiative project, SMDP-II, at NIT, Jalandhar for year and a half. Played an instrumental role in taking designs from Circuit to Layout. Guided Masters and Bachelors Projects. • Amitav Banerjee: o Qualification: B.Tech. In Information Technology from UPTU (2010), Mentor Graphics Certification in Electronic Design & Verification using SystemVerilog (2010) o Experience: Started his career at DKOP Labs as Software Engineer. Handling multiple projects in Web Technology and Systems Programming using C, PHP, .NET, MySQL. INDUSTRY PARTNERSHIPS CADENCE DESIGN SYSTEMS DKOP is Certified Training Partner of Cadence for whole of North India MENTOR GRAPHICS CORPORATION DKOP is Vanguard Partner and HEP (Higher Education Program) Partner of Mentor Graphics Corporation. 6/10
  • 7. AGNISYS DKOP is Spark Higher Education Program partner of Agnisys. DKOP students are given live projects from Agnisys to work and deliver in tight deadlines. DKOP PLACEMENTS Companies where we have placed our students ST MICROELECTRONICS, GREATER NOIDA Kavita Sharma, Banasthali Vidyapeeth CADENCE DESIGN SYSTEMS, NOIDA Sorabh Dung, LIT, Lovely Professional University Ruchi Mittal, CDAC Rachna Raj, Banasthali University Saloni Goel, Banasthali University Sachin Kumar, LIT, Lovely Professional University Jupinder Kaur, LIT, Lovely Professional University Manvi Goel, Banasthali University Balveer Singh Koranga, GB Pant Engineering College, Pauri, Uttaranchal MENTOR GRAPHICS, NOIDA Vikas Tomar, ITM, Gurgaon Jitendra Aggarwal, Amity University, Noida AGNISYS, NOIDA Sandeep Thakur, Lovely Professional University Amit Kapoor, SSIET, Dera Bassi Nitin Ahuja, BSAITM, Faridabad NSYS, DELHI Nidhi Gupta, M.P.C.T., Gwalior Prishkrit Abrol, DAVIET, Jalandhar 7/10
  • 8. Pankaj Talwar, LCET, Ludhiana Richa, Banasthali University Mamta Rana, Jiwaji University CIRCUITSUTRA TECHNOLOGIES, NOIDA Parvinder Pal Singh, Lovely Professional University DKOP LABS, NOIDA Rahul Kumar, Rai University Pushpinder Singh, SVIET – Banud Amitav Banerjee, UPTU RF SILICON, NOIDA Nirmal Singh, UPTU HP, BANGALORE Hariom Pandey, UPTU SASKEN, BANGALORE Sumit Gupta, Thapar - Patiala Sumit Kumar, Thapar - Patiala PHOENIX, NOIDA Akhilesh Singh, Jiwaji University RELIANCE, PUNE Ajay Gupta, Jiwaji University OM NANOTECHNOLOGY, GREATER NOIDA Mohammed Sharique, Jiwaji University UNIVERSITIES IN USA, CANADA & GERMANY Smriti Gurung Subeg Singh Binipal Wadhwa 8/10
  • 9. Hasan Karkara Note: Our competitors also hire our graduates! RECOMMENDATIONS 1. Mr Jitin Sahni Manager, HR & Recruitment Freescale Semiconductors, Noida 2. Mr. Harish Pandey Marketing Head AMDL, Bangalore 3. Mr. Upender Bhati Marketing Head AEM India Pvt. Ltd., Noida 4. Mr Anupam Bakshi CEO, AgniSys Noida 5. Mr Umesh Sisodia CEO, CircuitSutra Technologies Pvt Ltd Noida 6. Mr Sanjay Chakravarty VP, ITAAS Inc Noida 7. Prof Dinesh Sarbahi HOD, Electronics & Communication VIET, Dadri 8. Dr. S.N. Saran Director GNIT, Greater Noida DKOP TOUCHED FOLLOWING COLLEGES We have conducted on-campus programs (Workshops/Trainings/Conferences) at following colleges: 1. LOVELY PROFESSIONAL UNIVERSITY, PHAGWARA 2. GREATER NOIDA INSTITUTE OF TECHNOLOGY, GREATER NOIDA 3. NIT, JALANDHAR 4. VISHWESHVARYA INSTITUTE OF ENGINEERING & TECHNOLOGY, DADRI 5. LIET ( LAXMI DEVI INSTITUTE OF ENGINEERING & TECHNOLOGY), ALWAR 6. SHEKHAWATI ENGINEERING COLLEGE 7. ST. MARGARET ENGG. COLLEGE, NEEMRANA 8. ITM, BHILWARA 9. YMCA, FARIDABAD 9/10
  • 10. 10. BANASTHALI VIDYAPITH 11. CHITKARA INSTITUTE OF ENGG & TECH, RAJPURA 12. DAV INSTITUTE OF ENGG & TECH, JALANDHAR 13. KUMAON ENGINEERING COLLEGE, DWARAHAT 14. GB PANT ENGG COLLEGE, PAURI 15. INSTITUTE OF TECHNOLOGY, PANTNAGAR 16. SACHDEVA COLLEGE OF ENGG, MATHURA 17. COLLEGE OF ENGG, ROORKEE 18. JSS, NOIDA 19. JIIT, NOIDA 20. BS ANANGPURIA, FARIDABAD 21. GRAPHICS ERA UNIVERSITY, DEHRADUN 22. MITRC, ALWAR 23. SIDDHI VINAYAK, ALWAR 24. NC COLLEGE OF ENGG, PANIPAT 25. BITS, BHIWANI 26. SRI SUKHMANI INSTITUTE, DERABASSI 27. SVIET, BANUD 28. LUDHIANA COLLEGE OF ENGG & TECH 29. DESHBHAGAT ENGG COLLEGE 30. SSIET, PATTI 31. RAI UNIVERSITY, FARIDABAD 32. COLLEGE OF ENGG & TECH, KAPURTHALA 33. RIET, JAIPUR 34. ITS, GREATER NOIDA 10/10