This document discusses challenges related to implementing a low power dual-mode GPS receiver. It begins with an overview of a startup company called Air and their goal of developing continuous adaptive GPS technology to offer both low power and position accuracy. It then discusses five major low power implementation challenges: determining when low power verification is complete, dealing with power management kits, predicting clock tree power consumption, handling multi supply voltage chips, and whether power and timing optimization are always aligned. The document emphasizes that low power must be considered from the earliest stages of design.

1. Implementation Methodology
for Dual-Mode GPS Receiver
David Tester, Founder & CTO, Air Semiconductor
Jon Young, Chris Atkinson & Tom Ryan, Synopsys
1

2. Overview of Presentation
- GPS 101
Quick overview of GPS
- Air
Glimpse into life inside a start-up
- Low Power Methodology Challenges
Aspects of low power IC implementation
that we care about that may interest you
2

3. GPS 101
Receive Power is -130dBm to -160dBm … 20dB to 50dB below the Thermal Noise Floor!
Earth radius 6 km
3578
6378 km
m
0 0k Geo-stationary
191
Regional geo-stationary
augmentation satellites
km
20200 WAAS
Wide Area Augmentation System – USA
EGNOS
23222 km European Geostationary Navigation Overlay
System – Europe
GPS
6 orbital planes; 55° to equator Galileo
Moon
Galileo Approx. 400000 km
3 orbital planes; 56° to equator
GLONASS
GPS
3 orbital planes; 65° to equator Orbit 11 hours 58 minutes
13900 km/h
GLONASS
3

4. GPS 101
Triangulation allows Receiver Position to be Calculated
r3
r2 r4
r1
4

5. GPS 101
Satellite transmits essential information required for Receiver Positioning
1µs 3x108 ms-1
MOBILE
300m 1_.@ DEF3
2ABC
4GHI MNO 6
5JKL
7PQRS WXYZ 9
8TUV
#
* 0+
5

6. Air Invents Continuous Adaptive GPS
… offers both Low-Power & Position Accuracy
Accuracy
Low-Power
Competitor
Air
6

7. airwave architecture enables useful geofences
A-GPS geofence
Air geofence
7

8. View from the office window of a start-up…
8

9. The A Development Team
Hugh Thomas
CEO
David Tester Andy Heaton Stephen Graham
Co-Founder & CTO VP Operations & Development Co-Founder & VP Marketing
RFIC Design System Design ASIC Design Software Design
Staff Staff Staff Staff
Employee #1 (20 years experience) Employee #3 (20 years experience) Employee #4 (10 years experience) Employee #7 (20 years experience)
Employee #2 (20 years experience) Employee #1 (20 years experience) Employee #5 (15 years experience) Employee #8 (15 years experience)
Employee #6 (15 years experience)
Contract Contract Contract
Contract #1 (15 years experience) Contract #3 (20 years experience) Contract #8 (20 years experience)
Contract #2 (15 years experience) Contract #4 (20 years experience) Contract #9 (15 years experience)
Contract #5 (20 years experience)
2x Synopsys IC layout contractors
Board of Directors
Support Staff
Hugh Thomas CEO ex-CEO TapRoot 1x General Admin
1x Finance Manager
David Tester CTO
ex-CEO Andromedia (acquired Macromedia ‘99)
Kent Godfrey Pond Ventures
ex-CEO Frictionless Commerce (acquired SAP ‘06)
Michael Gera Pond Ventures
ex-CEO PortalPlayer (NASDAQ: PLAY)
Gary Johnson Independent ex-CEO S3 (NASDAQ: SIII)
9

10. Concept to Engineering Sample Silicon
Air tracks GPS satellites with RFIC
March „08
RFIC + FGPA platform
May „08
Air tracks GPS satellites with RFIC + FPGA
A1225 RFIC (v1) June „08
April „07 Air first PVT, confirms lab in Swindon
June „08
A1225 RFIC (v2)
A1250 single die GPS receiver
February „08
January „09
J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D
2006 2007 2008 2009
J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D
Electra Start-Up of the Year 2008
November „08
Gary Johnson joins Board of Directors
2x NASDAQ CEO (PortalPlayer & S3) IET Start-Up of the Year 2008
May „07 November '08
Prof Izzet Kale joins Technical Advisory Board
October „08
Engage with TSMC for silicon
Sept „06
Demonstrate GPS technology
July „08
Development starts!
June „06 Recruit external CEO
May „08
Air Inc + Ltd incorporated
May „06 Red Herring 100 Europe 2008
April „08
Series-A Termsheet
April „06 Exit stealth mode
Announce 1st product
January „08
10

11. Concept to Engineering Sample Silicon
Dual-Mode GPS
system design
Dual-Mode GPS
software design
Acquisition DSP
Tracking DSP Architecture
Architecture
Tracking DSP
Tracking DSP Implementation
Implementation
Acquisition DSP
Implementation
J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D
Radio IC Radio IC A1250
A1250 silicon evaluation
Implementation Implementation IC design
Air tracks GPS satellites with RFIC
Tracking DSP
March „08
Architecture
RFIC + FGPA platform
PVT & May „08
Kalman Filter
Air tracks GPS satellites with RFIC + FPGA
A1225 RFIC (v1) June „08
April „07 Air first PVT, confirms lab in Swindon
June „08
A1225 RFIC (v2)
A1250 single die GPS receiver
February „08
January „09
J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D
2006 2007 2008 2009
J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D
Electra Start-Up of the Year 2008
November „08
Gary Johnson joins Board of Directors
2x NASDAQ CEO (PortalPlayer & S3) IET Start-Up of the Year 2008
May „07 November '08
Prof Izzet Kale joins Technical Advisory Board
October „08
Engage with TSMC for silicon
Sept „06
Demonstrate GPS technology
July „08
Development starts!
June „06 Recruit external CEO
May „08
Air Inc + Ltd incorporated
May „06 Red Herring 100 Europe 2008
April „08
Series-A Termsheet
April „06 Exit stealth mode
Announce 1st product
January „08
11

12. airwave1 system development platform
and engineering sample silicon module
BACK
12

13. airwave1 engineering silicon
QFN bonding photo
13

14. GPS with airwave1 silicon
14

15. Air Technical Demonstration Platform … in Japan
15

16. Low-Power Implementation Challenges
What is necessary for low-power silicon implementation of a system?
Disruptive products demand system-level optimizations
- - Low-Power is no exception and requires …
- Example: airwave1 and low-power GPS optimization
- Today we will not discuss GPS system implementation!
- Instead let‟s look at silicon methodology and challenges
Let‟s consider an alternative question:
“How did you create the silicon implementation of a
low power architecture? What are the challenges?”
Here are five … not in any order and not an exhaustive list …
Q1. Lazy is OK. How do you know when you‟re done?
Q2. Did you survive (or avoid) the pain a PMK can offer?
Q3. Can clock tree power consumption be predicted?
Q4. Multi-DVDD chips – Where EDA meets reality …
Q5. Is timing-optimized and power-optimized the same?
16

17. Optimize Power Everywhere, Earlier is Better
Efficient algorithms provide more power saving than optimized circuits
17

18. Simplified Air System + Silicon Design Flow
(Does not include any analog or custom IC aspects!)
System Logical Physical
Design & Design & Design &
Verification Verification Verification
System-Level Logic Level Top-Level Pad Ring
Architecture Architecture Pre-P&R Floorplan Design
Circuit Sim
System-Level Logic Level Trial Logic Trial P&R Trial CTS Trial STA
Simulation RTL Design Synthesis for blocks for blocks (Post-P&R)
Firmware
Logic Level Final Logic Final P&R Final CTS Final STA
Design
Simulation Synthesis for blocks for blocks (Post-P&R)
FPGA Pre-P&R
Logic Level Circuit Sim Trial P&R Trial CTS Trial STA
Prototype Verification (top level) (top-level) (top level)
Power
Firmware Domains
Design Power Level Final P&R Final CTS Final STA
Verification (top level) (top-level) (top level)
More
Firmware
DRC LVS
(top level) (top-level)
Silicon
Platform GDSII
18

19. airwave1 engineering silicon
QFN bonding diagram
19

20. airwave1 engineering silicon
Device Floorplan (No Global Routing)
20

21. airwave1 engineering silicon
Device Floorplan (with Global Routing)
21

22. airwave1 engineering silicon
44 independent digital power domains
2 3 4
5
6 7 8
1 9
10 11 12
13
14 15 16 17
42
43
44
39 40 41
18 19 20 21 22 23 24 25
34 35 36 37 38
26 27 28 29 30 31 32 33
22

23. airwave1 engineering silicon
Radio Macro + Analog Support Macro
23

24. Quick Review on Where Power is Consumed
Dynamic (switching) and static (leakage) power from DVDD to DVSS
Example circuit taken from:
Source: http://www.dti.unimi.it/~liberali/papers/c63.pdf
24

25. Routing Capacitance is the Enemy
Parasitic capacitance significantly alters logic switching power
How can you verify post-layout parasitic routing capacitance is acceptable?
25

26. Stop when “Low-Power” is low enough?
Products need to get to market …
Stop when you‟ve verified it‟s good enough
Can you spot the conflict between the following two statements?
“I‟d like the lowest possible power consumption, please”
“I‟d also like to get that product to market on time, please”
Do you have a power budget? When should verification STOP ?
Track and predict power performance at all levels of abstraction:
- Architecture / Algorithm / System Partitioning
- Pre-Synthesis RTL and Post-Synthesis Gates
- Pre-Layout and Post-Layout
“… but verification is never really complete…”
True
… what is the milestone for sufficient
confidence that power meets budget?
26

27. Less Complexity, Less Transitions = Low Power
Reduce depth of logic and switching activity to minimise power
How to verify switching
activity level on budget?
How to verify the original
complexity assumptions?
27

28. “Custom” Cells rather than “Standard” Cells?
„Optimized for Power‟ and „Optimized for Timing‟ might not be the same
- Knowledge of “use” offer options for power optimized gates
- Power optimized and timing optimized are not always the same
Example
- Custom flip-flop used in airwave1 datapath
- Relaxed timing enabled >40% power improvement!
- Also provided die area and P&R enhancements
28

29. What‟s Your Methodology to Build Clock Trees?
Not all clock tree‟s are low power … can you trust the tools?
- Power depends on conflicting constraints: skew, rise time, load, etc
- CTS tools build functional but over-designed, high-power clock trees
- Can‟t verify power until P&R started ... but is that too late for market?
- Clock tree can pass functional verification but fail power verification!
Example:
airwave1 contains
400+ clock domains
More a clock forest
than a clock tree ...
29

30. Power Management Kit - Handle Carefully!
… rather like a chainsaw with all the safety features removed …
- Standard cell library assumes single DVDD supply voltage
- Power management library enables multiple voltage domains
- Voltage domain control cells – DVDD and DVSS switch
- P&R “optimisation” can pull cells from PMK library by mistake!
- Can simulation identify these problems?…
- Signal isolation cells (for crossing voltage domains)
- Must verify P&R didn‟t “optimise” these!
- PMK also adds more back-end DRC and LVS
verification issues simulation can‟t solve…
30

31. Multi-DVDD Silicon: Where EDA meets Reality!
Circuit level functionality that needs to be verified at RTL level
- DVDD functionality in “HEAD” and “FOOT” cells
… but DVDD not represented in non-UPF flow logic simulation!
- How, and when, are cells instanced in the design?
- Manually by logic designer or layout team?
- Automatically by EDA tool? Do you trust it?
- Yet another task to verify before tape-out !!!
- Control signal active sense depends on cell used:
- Active low for PMOS but active high for NMOS
- Are control signal wired correctly?
- How many cells for each domain?
- “Power Aware” design flows try to plug the hole!
Example: … but don‟t address all the issues !!!
airwave1: 44x digital, 8x analog voltage domains
31

32. DVDD and DVSS power routing
metal5 and “thick” metal6 reserved for power routing
32

33. airwave1 engineering silicon
44 independent digital power domains
2 3 4
5
6 7 8
1 9
10 11 12
13
14 15 16 17
42
43
44
39 40 41
18 19 20 21 22 23 24 25
34 35 36 37 38
26 27 28 29 30 31 32 33
33

34. Power Domains - Some Issues to Watch
Don‟t forget substrate, N-well and control signal polarity
34

35. Power Domains - Some Issues to Watch
Don‟t forget substrate, N-well and control signal polarity
35

36. Automatic vs Manual Cell Placement
P&R placement algorithm is not always optimum
Manual Placement
Automatic Placement
36

37. Impact of UTM metal on P&R efficiency
Metal pitch + spacing rules directly impact P&R result
“thin”
metal5
“thick”
metal6
37

38. Post-P&R Optimization? Roll the Dice Again!
Development on-schedule and on-budget?
P&R “optimization” can solve that…
“Here‟s the final netlist,
it meets the power spec‟s
and just needs to go through P&R”
- Pre-Layout gate level power estimates are estimates
- Routing capacitance impacts both timing and power
- P&R optimization resizes gates to close timing
… almost certainly ignoring circuit power
… so power estimates on pre-P&R netlist
are exactly that, estimates
Verification Issue:
How to verify post-layout power still hits
the target specification …
… and hit your schedule
38

39. “Blind Faith and Ignorance”
or “Informed Decision”?
Don‟t forget to be paranoid about power, if you care about power
Low-Power can be broken anywhere:
- Architecture
- Hardware (RTL) or Software
- Logic Synthesis
- P&R and CTS
- Cell library and macros choices
- Process technology
Each step needs differing levels of implementation and verification
activity, but verification of power needs more than just logic
simulation and must include power budgets and circuit simulation
CPU power alone can‟t solve the problems, brain power is needed!
39

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