2. • Initially The o/p Q is HIGH
• Therefore o/p of 555(3 pin) is LOW
• The –Ve going input at pin 2(Trigger) is less than Vcc/3, the
output of Lower comparator goes to HIGH and sets the FF i.e.
Q=1
• If The voltage at pin 6(Threshold) is greater than 2Vcc/3
then the upper comparator goes high and resets the FF i.e.
Q=0
• The reset is effective when the i/p is less than 0.4 V.
• The Q2 serves as a buffer to isolate the reset input from The
FF and Q1.
4. • In stand by state FF holds Q1 on, Thus clamping the
external Capacitor to GND, i.e O/p =0.
• The –Ve going input at pin 2(Trigger) is less than Vcc/3,
the output of Lower comparator goes to HIGH and sets the
FF i.e. Q=1. Therefore Q1 is off, o/p is ON(1) and C is
unclamped
• The voltage across C rises exponentially through R
towards Vcc with the time constant of RC (T).
• The Voltage across C increases more than (2/3)Vcc the
upper comparator resets the FF i.e Q1 is on
• The C discharges to GND potential.
5. Vc=Vcc(1-e-t/RC)
At t=T Vc= (2/3)Vcc
Therefore (2/3)Vcc =Vcc(1-e-T/RC) OR T=RC ln(1/3)
OR T= 1.1 RC Sec therefore the timing interval is
independent of supply voltage.
• Once triggered, the output is remains high until T elapses (RC)
• If a –Ve going reset pulse applied at Pin-4 during the timing
cycle, Q2 and Q1 are On and C is immediately discharged.
• even if the reset is released, o/p remains LOW until a –Ve
going trigger is applied at pin-2.
