Designing at the 2x nanometer scale presents new challenges. Some key challenges include increased complexity, higher power consumption, and difficulties with lithography at smaller scales. Potential solutions explored include non-planar transistor structures, double patterning lithography, and 3D stacking through silicon interposers. Tools are being enhanced to support these new device structures and integration approaches to continue scaling to smaller nodes.

1. Designing At 2x Nanometers
Some New Problems Appear, and
Some Old Ones Remain
Marco Casale-Rossi
Synopsys, Inc.
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2. Designing At 2x Nanometers
What Are the Key Areas of Focus?
(1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Metal Gate; (3) Planar CMOS Source: ITRS 2011, AMSL 2010, IBS 2008
(1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Metal Gate; (3) Planar CMOS;
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3. More Complexity Challenges
Sheer Complexity Remains the #1 Challenge
Intel CE4200
45 nanometers (2010)
Intel CE3100, 90 nanometers (2008) 96mm2, ~ 300M transistors
208mm2, 150M transistors, 10W 7-9W
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4. Gigascale Design Implementation
Evolving Into Two, Closely Connected “Sub-Systems”
• The Initial “sub-system”
– Fast synthesis, floorplanning, and placement
– Used for design exploration, constraints clean-up, feasibility
– Findings – e.g. floorplan – will be “shared” with back-end
• The Full “sub-system”
– Takes over once “initial” done
– Full synthesis and place & route
– Heavy use of special “correction” techniques
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5. RTL Exploration
~ 6X Faster Than RTL Synthesis
Slack Distribution Comparison, Correlation ±8%
Slack Histogram Floorplan
DC-E DC-T DC-E w/ Floorplan Information
-1.3 -0.95 -0.55 -0.15 0.2 0.55 0.95 1.3 1.7 2.1
Source: Synopsys Research 2011
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6. Look-Ahead & Physical Guidance
Same Critical Paths, Correlation ±5%
Synthesis Place & Route
Source: Synopsys Research 2011
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7. Gigascale Design Implementation
Constraints Analysis, Design Exploration & Block Feasibility
• Initial Floorplan Partitions • Final Top Level Floorplan
• Final Chip Implementation
• Clean Top Level Routing • Block Level Floorplan
• Blocks Modeled as ILM/ETM
• Clean Top Level SDC • Timing Budgets
Feasibility Stage Implementation Stage
Chip
Design Exploration Design Planning Top Assembly
Level
Block
Block Feasibility Block Implementation
Level
• Clean Block Level SDC • Final Block Implementation
• Final Block Level Floorplan • Timing and Congestion Clean
Dirty Clean Final
Design Data
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8. Design Exploration
Heading Into the Right Direction ?
Standard Placement (Fully Legalized) Exploration Placement (Coarser)
Several Hours 27M Instances in 1 Hour
Source: Fujitsu, SNUG Japan 2010
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9. Block Feasibility
45 Nanometers, 4M Instances
Feasibility Implementation Feasibility Implementation
Runtime Runtime Performance Performance
Implementation
30 Results Improve w/
Cleaner SDC
200
Performance (MHz)
25
Runtime (Hours)
Feasibility
20 QOR Same As
Implementation
100
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10 0
No false paths or 17 false paths not 17 false paths + 3 All false paths and
Feasibility Feasibility Runtime
multi-cycle paths identified multicycle paths not multi-cycle paths
2X Faster Than Independent of SDC
Implementationidentified identified identified Dirtiness
Source: IDM, 2010
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10. Gigascale Design Implementation
Longer Term Evolution
• Until now :
– Mostly “preserve” the gates
– “Change” placement, and/or routing to close timing, power,
• Very, very time consuming, and
• Leads to a number of iterations
• In the future :
– Once the objective is “within reach”
– “Hold” placement and routing
– Systematically “change” the gates
• Same footprint, different timing, power, temperature inversion
point, etc.
• The richness of the library is fundamentally important
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11. ECO Flow
32 Nanometers, ~ 3M Instances, ~ 300 Macro Blocks
40 Scenarios, Runtime < 8 Hours, 99% Hold Fix Rate
1000000
TNS, No. of Violations, WNS
100000
10000
1000
100
10
1
1st SignOff ECO1 ECO2
Total Hold Slack (ps) 19558 102 34
No. Hold Violations 2382 49 6
WNS (ps) 116 6 15
Source: STMicroelectronics, PrimeTime SIG, 2012
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12. Leakage Recovery
32 Nanometers, ~ 3M Instances, ~ 300 Macro Blocks
Leakage = 1X Leakage = 0.77X, -23%
Source: Synopsys Research 2011
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13. More Performance Challenges
The Application Processors Race for “PP&A”
Maximum Clock Frequency @ Nominal Voltage, 125°C, 500mW
12X
10X
8X
6X
4X
2X
X
90 65 45/40 32/28 22/20
Source: Synopsys Research 2011
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14. High Speed And Low Power Flow
Better Quality-of-Results, Faster Time-to-Results
Targets Typical flow on Typical flow on high speed,
standard designs low power designs
100%
Better quality-of-results
90%
75%
High speed
and low power
(HSLP) flow
Typical flow
Faster time-to-results
HSLP flow
Design-specific
Time customization
Source: Synopsys Research 2011
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15. High Speed And Low Power Flow
ARM Cortex™-A9 MPCore™ Dual Core
Timing Closure Profile
110%
Performance (% of Target)
100%
90%
80%
Synthesis Placement CTS Routing
Additional Customization For High Speed
High Speed and Low Power Flow
RM (Baseline) Flow
Source: Global Unichip, SNUG Taiwan 2011
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16. More Performance Challenges
Besides Digital, Analog and Mixed-Signal
Digital
Analog & M/S
Source: R. Rutenbar, CMU, ICCAD 2006; H. Hiller, Infineon, DAC 2007
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17. Much More Than Just Interoperability
Shared Tasks Between Digital and Analog Environments
Source: Synopsys Research 2012
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18. Analog Pre-Routing
Matched Resistance Routing
Source: Synopsys Research 2012
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19. What Else Should We Look At?
Three “Revolutions” After Thirty Years of “Evolution”
Device Non-planar CMOS
Lithography Double patterning
Integration 3D-IC
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20. The Challenge: Planar CMOS
Insufficient Performance, Excessive Power
32 Nanometer Planar Not Enough “Headroom”
Source: K. Kuhn, Intel, IDF 2011
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21. The Solution: Non-Planar CMOS
The First “Revolution”
22 Nanometer Tri-Gate More “Headroom” !!!
Source: K. Kuhn, Intel, IDF 2011
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22. The Solution
SPICE Simulation, and Parasitic Extraction
Model/Compute Parasitics/Extract
M1
Contact Gate
Source Fin Fin Drain
Source: Synopsys Research 2011
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23. The Challenge: Single Exposure
“Last Pitch With Single Exposure ~ 80 Nanometers ”
We Can Print This, But We Cannot Print This
Source: M. van den Brink, ASML, ITF 2009; P. Magarshack, STMicroelectronics, 2010
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24. The Solution: Double Patterning
The Second “Revolution”
We Can Print This, and This, And Then This!
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25. The Solution
DPT Ready Logic Libraries and Placer
DPT-Aware Placement DPT Compliant Coloring
Source: Synopsys Research 2012
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26. The Solution
DPT Ready Router and DRC
Source: Synopsys Research 2012
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27. The Challenge: “> 2D-IC”
“More of Moore” Requires “More than Moore”
1 2
C4 Silicon Interposer
Memory (Wide I/O) Memory TSV 3D Stack µBump
“Cube” “Cube” on Logic
4
3
Source: Synopsys Research 2011
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28. The Solution: 3D-IC
The Third “Revolution”
Source: L. Madden, Xilinx, 2011
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29. The Solution
Side-by-Side, Passive Silicon Interposer,
Single-Sided (F2F), to Begin with
Source: Synopsys Research 2011
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30. The Solution
Silicon Interposer with P&G Grid, and
µBumps, TSV, and C4
Source: Synopsys Research 2011
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31. Leveraging Existing Tools
Silicon Interposer (Detail)
Source: Synopsys Research 2011
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32. Leveraging Existing Tools
Silicon Interposer (Detail) Routed
Source: Synopsys Research 2011
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33. ‫תּוֹדָ ה‬
May 2nd, 2012
Tel Aviv, Israel
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