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                 Start Group tutorial [2]


Prepared by
          Alaa Salah Shehata
          Mahmoud A. M. Abd El Latif
          Mohamed Mohamed Tala’t
          Mohamed Salah Mahmoud

                                             Version 02 – October 2011
                                          Copyright 2006 – Biz/ed
http://www.bized.co.uk




Outline   -Using Xilinx IP Cores
          -ISIM Simulator
          -Language Templates
                                             B

                                                 2
                                   Copyright 2006 – Biz/ed
http://www.bized.co.uk




Using Xilinx IP Cores




                     Copyright 2006 – Biz/ed
tutorial

                                                                   http://www.bized.co.uk

Why IP cores

 An IP (intellectual property) core is a block of logic or data that is used in FPGAs or ASIC
 for a product.

 Features

 1-Repeated use of previously designed components.
 2-Portable that is able to easily be inserted into any design methodology.




                                                                                     4
                                                                       Copyright 2006 – Biz/ed
tutorial

                                             http://www.bized.co.uk

First Step              Generating IP Core




                                                              5
                                                Copyright 2006 – Biz/ed
tutorial

           http://www.bized.co.uk




                            6
              Copyright 2006 – Biz/ed
tutorial

                                             http://www.bized.co.uk




In the IP selection window, find the IP to
customize.


                                                              7
                                                Copyright 2006 – Biz/ed
tutorial

                                 http://www.bized.co.uk




           For information about the customization
           options, click the Data Sheet button in the
           core customization GUI. The data sheet that
           appears explains all of the options.




                                                   8
                                     Copyright 2006 – Biz/ed
tutorial

                                           http://www.bized.co.uk




           Now, we generated an IP core and this core is on this
           project, before generating this code you must read the
           data sheet to deal with its GUI, know the timing diagram
           and pins I/O interface of this core.




                                                             9
                                               Copyright 2006 – Biz/ed
tutorial

             http://www.bized.co.uk




Data Sheet

                             10
                Copyright 2006 – Biz/ed
tutorial

                                  http://www.bized.co.uk

Second Step       Using IP Core




                                                  11
                                     Copyright 2006 – Biz/ed
tutorial

                                                             http://www.bized.co.uk

library IEEE;
                                   Now, we will make a project that adds two
use IEEE.STD_LOGIC_1164.ALL;       numbers using this IP core.
                                   VHDL code
entity add is
         port (
         in1      :   IN std_logic_VECTOR(14 downto 0);
         in2      :   IN std_logic_VECTOR(14 downto 0);
         clk      :   IN std_logic;
         enable   :   IN std_logic;
         result   :   OUT std_logic_VECTOR(15 downto 0));
end entity;

architecture Behavioral of add is

component adder_core
         port (
         a: IN std_logic_VECTOR(14 downto 0);
         b: IN std_logic_VECTOR(14 downto 0);
         clk: IN std_logic;
         ce: IN std_logic;
         s: OUT std_logic_VECTOR(15 downto 0));
end component;



                                                                             12
                                                                Copyright 2006 – Biz/ed
tutorial

                                          http://www.bized.co.uk


Begin

your_instance_name : adder_core
                 port map (
                          a => in1,
                          b => in2,
                          clk => clk,
                          ce => enable,
                          s => result);

end Behavioral;




                                                          13
                                             Copyright 2006 – Biz/ed
tutorial

                                                    http://www.bized.co.uk

Third Step                   Simulating IP Core




Click the device icon ..in Design Utilities click
on compile HDL Simulation libraries.

For simulation on Modelsim you should
generate some libraries for the ip core.




                                                                    14
                                                       Copyright 2006 – Biz/ed
http://www.bized.co.uk




[ISIM] ISE Simulator




                     Copyright 2006 – Biz/ed
tutorial

                   http://www.bized.co.uk

ISIM Simulator




                                   16
                      Copyright 2006 – Biz/ed
tutorial

                   http://www.bized.co.uk

ISIM Simulator




                                   17
                      Copyright 2006 – Biz/ed
tutorial

                   http://www.bized.co.uk

ISIM Simulator




                                   18
                      Copyright 2006 – Biz/ed
tutorial

                   http://www.bized.co.uk

ISIM Simulator




                                   19
                      Copyright 2006 – Biz/ed
tutorial

                   http://www.bized.co.uk

ISIM Simulator




                                   20
                      Copyright 2006 – Biz/ed
tutorial

                                             http://www.bized.co.uk



Download ISIM tutorial from Xilinx




http://www.xilinx.com/support/documentation/sw_manuals/xil
inx11/ug682.pdf




                                                             21
                                                Copyright 2006 – Biz/ed
http://www.bized.co.uk




Language Templates




                  Copyright 2006 – Biz/ed
tutorial

                                                                   http://www.bized.co.uk

Language Templates




 The ISE Language Templates provide predefined pieces of code and code syntax for
 use in your source files.

 These templates enable easy insertion of pre-built text structures into your VHDL file.

 Select Edit > Language Templates, or click the Language Templates toolbar button
 shown .



                                                                                    23
                                                                       Copyright 2006 – Biz/ed
tutorial

                                                              http://www.bized.co.uk

Language Templates




                  Click the plus (+) icon to expand the folders until you find the
                  template you want to use.
                  Select the template to display it in the right pane.
                  Insert the code in your source file.




                                                                               24
                                                                  Copyright 2006 – Biz/ed
tutorial

                                            http://www.bized.co.uk

Language Templates
 you can create your own custom templates
 as follows.

 1-Select the User Templates folder.
 2-Right Click : New Folder
           Type a name for your folder.
 3-Right Click : New Template.
           Type a name for your template.




                                                            25
                                               Copyright 2006 – Biz/ed
tutorial

                                             http://www.bized.co.uk

Language Templates
 4-Add your code to the right pane of the
 Language Templates window.

 5-Right Click on the template name : Save
 Template.

 6-Note To remove a template, select the
 template, and click the Delete toolbar
 button .




                                                             26
                                                Copyright 2006 – Biz/ed
tutorial

                       http://www.bized.co.uk




See You Next Session




                                       27
                          Copyright 2006 – Biz/ed

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Start group tutorial [2]

  • 1. http://www.bized.co.uk Start Group tutorial [2] Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
  • 2. http://www.bized.co.uk Outline -Using Xilinx IP Cores -ISIM Simulator -Language Templates B 2 Copyright 2006 – Biz/ed
  • 3. http://www.bized.co.uk Using Xilinx IP Cores Copyright 2006 – Biz/ed
  • 4. tutorial http://www.bized.co.uk Why IP cores An IP (intellectual property) core is a block of logic or data that is used in FPGAs or ASIC for a product. Features 1-Repeated use of previously designed components. 2-Portable that is able to easily be inserted into any design methodology. 4 Copyright 2006 – Biz/ed
  • 5. tutorial http://www.bized.co.uk First Step Generating IP Core 5 Copyright 2006 – Biz/ed
  • 6. tutorial http://www.bized.co.uk 6 Copyright 2006 – Biz/ed
  • 7. tutorial http://www.bized.co.uk In the IP selection window, find the IP to customize. 7 Copyright 2006 – Biz/ed
  • 8. tutorial http://www.bized.co.uk For information about the customization options, click the Data Sheet button in the core customization GUI. The data sheet that appears explains all of the options. 8 Copyright 2006 – Biz/ed
  • 9. tutorial http://www.bized.co.uk Now, we generated an IP core and this core is on this project, before generating this code you must read the data sheet to deal with its GUI, know the timing diagram and pins I/O interface of this core. 9 Copyright 2006 – Biz/ed
  • 10. tutorial http://www.bized.co.uk Data Sheet 10 Copyright 2006 – Biz/ed
  • 11. tutorial http://www.bized.co.uk Second Step Using IP Core 11 Copyright 2006 – Biz/ed
  • 12. tutorial http://www.bized.co.uk library IEEE; Now, we will make a project that adds two use IEEE.STD_LOGIC_1164.ALL; numbers using this IP core. VHDL code entity add is port ( in1 : IN std_logic_VECTOR(14 downto 0); in2 : IN std_logic_VECTOR(14 downto 0); clk : IN std_logic; enable : IN std_logic; result : OUT std_logic_VECTOR(15 downto 0)); end entity; architecture Behavioral of add is component adder_core port ( a: IN std_logic_VECTOR(14 downto 0); b: IN std_logic_VECTOR(14 downto 0); clk: IN std_logic; ce: IN std_logic; s: OUT std_logic_VECTOR(15 downto 0)); end component; 12 Copyright 2006 – Biz/ed
  • 13. tutorial http://www.bized.co.uk Begin your_instance_name : adder_core port map ( a => in1, b => in2, clk => clk, ce => enable, s => result); end Behavioral; 13 Copyright 2006 – Biz/ed
  • 14. tutorial http://www.bized.co.uk Third Step Simulating IP Core Click the device icon ..in Design Utilities click on compile HDL Simulation libraries. For simulation on Modelsim you should generate some libraries for the ip core. 14 Copyright 2006 – Biz/ed
  • 15. http://www.bized.co.uk [ISIM] ISE Simulator Copyright 2006 – Biz/ed
  • 16. tutorial http://www.bized.co.uk ISIM Simulator 16 Copyright 2006 – Biz/ed
  • 17. tutorial http://www.bized.co.uk ISIM Simulator 17 Copyright 2006 – Biz/ed
  • 18. tutorial http://www.bized.co.uk ISIM Simulator 18 Copyright 2006 – Biz/ed
  • 19. tutorial http://www.bized.co.uk ISIM Simulator 19 Copyright 2006 – Biz/ed
  • 20. tutorial http://www.bized.co.uk ISIM Simulator 20 Copyright 2006 – Biz/ed
  • 21. tutorial http://www.bized.co.uk Download ISIM tutorial from Xilinx http://www.xilinx.com/support/documentation/sw_manuals/xil inx11/ug682.pdf 21 Copyright 2006 – Biz/ed
  • 22. http://www.bized.co.uk Language Templates Copyright 2006 – Biz/ed
  • 23. tutorial http://www.bized.co.uk Language Templates The ISE Language Templates provide predefined pieces of code and code syntax for use in your source files. These templates enable easy insertion of pre-built text structures into your VHDL file. Select Edit > Language Templates, or click the Language Templates toolbar button shown . 23 Copyright 2006 – Biz/ed
  • 24. tutorial http://www.bized.co.uk Language Templates Click the plus (+) icon to expand the folders until you find the template you want to use. Select the template to display it in the right pane. Insert the code in your source file. 24 Copyright 2006 – Biz/ed
  • 25. tutorial http://www.bized.co.uk Language Templates you can create your own custom templates as follows. 1-Select the User Templates folder. 2-Right Click : New Folder Type a name for your folder. 3-Right Click : New Template. Type a name for your template. 25 Copyright 2006 – Biz/ed
  • 26. tutorial http://www.bized.co.uk Language Templates 4-Add your code to the right pane of the Language Templates window. 5-Right Click on the template name : Save Template. 6-Note To remove a template, select the template, and click the Delete toolbar button . 26 Copyright 2006 – Biz/ed
  • 27. tutorial http://www.bized.co.uk See You Next Session 27 Copyright 2006 – Biz/ed