3. PHYSICAL DESIGN
• Job Description
• Designation: Staff-II/Sr.Staff/Principal /Sr. Principal Engineer
• Experience level: 3-17yrs
Positioned in a growing LTE/4G market, and projecting a very aggressive processor roadmap, Broadcom is looking for Technical
Lead physical design engineers for the complex MultiMode wireless (4G,3G and 2G) modem baseband ASICs working on the latest
process technology nodes
Essential Functions:
Self driven individual will be responsible for activities related to full chip floor plan, power grid design, IO ring design, clock tree
design, place and route of full chip and critical blocks, cross talk analysis, IR drop analysis, timing optimization, physical
verification, and interfacing to cross functional teams for complex low power and hierarchical chips in advance technology
nodes.Candidate should have strong basic concepts to over challenges in the different part of Physical design and should be able
to overcome those based on different experiments and data. Should be able to technically lead the team for delivery of technical
milestones.
Experience in RTL to GDSII flow with involvement in multiple tapeouts. Should have handled full chip floor plan and timing closure
for multi-million gate designs. Should have been involved in tape-out the chip in the advance technology nodes like 28nm and
below/40nm. Should be able to come up with the ideas for the team for the better flow in advance node process. Any interaction
with foundry for the advance process node is a plus. A good hands on exposure to that big hier design is a required.
Good experience in technically leading a team of physical design engineers and interfacing with cross functional teams
Strong communication and analytical skills
4. SYNTHESIS & STA
• Job Description
• Designation: Staff-II/Sr.Staff/Principal /Sr. Principal Engineer
• Experience level: 3-17yrs
Positioned in a growing LTE/4G market, and projecting a very aggressive processor roadmap, Broadcom is looking for Technical
Lead in the timing and synthesis area for the complex MultiMode wireless (4G,3G and 2G) modem baseband ASICs working on
the latest process technology nodes
Essential Functions: Self driven individual will be responsible for activities related to full chip and block timing closure and sign-off,
synthesis, equivalence checks. The person should be able to work with design team and the physical design team to device the
multiple ways to close the timing of different timing critical sub design or functionalities. Person should also be able to see
synthesis and STA challenges with advance technology nodes and setup methodologies/guideline and sign-off criteria with enough
data and experiments. Should be able to technically lead the team for delivery of tasks as well as the interface with design and
Physical design
Desired Skills & Experience
Experience in timing/synthesis flow with involvement in multiple tape outs. Should have handled timing closure for multi-million
gate designs. Should have been involved in tape-out the chip in the advance technology nodes like 28nm and below/40nm. Should
be able to come up with the ideas for the team for the better flow in advance node process. Brief break-up of the skills is below
Work with RTL design teams in understanding the design and developing the timing constraints both at block and SOC level,
decision on timing modes and the corners
Should had Synthesized the blocks and SOC with best QOR. Knows synthesis concepts in and out, should had worked on the
synthesis methodology/recipes
Should have Worked out the sign-off constraints/modes/corners and come up with the sign-off timing closure methodology.
Should had worked on the signoff timing closure and aware.
Enough design knowledge to suggest the multiple type of design changes for better synthesis and timing closure.
Should know the 20/22/28nm process challenges and should be able to work with library team.
Should be able to run the spice simulation for qualifying the timing(SI) violation if required in the advance timing node
Good experience in technically leading a team of physical design engineers and interfacing with cross functional teams
Strong communication and analytical skills
5. Front end design manager
• Job Description
• Designation: Sr.Design Manager
• Experience level: 12-15yrs
Manage and lead a team of engineers to develop 4G(LTE)/3G/2G multimode cellular modem SoC’s and IP’s. You will lead your
team to partner and work with System Architects, Software Engineers and IP providers to define functional specifications,
Architecture and Micro-architecture of the next generation cellular wireless modems. You will drive logic design and verification of
the modem and SoC blocks. You will also work closely with the Physical Design team for floor planning, timing closure and tape
out quality assurance checks. You will also provide leadership to integrate the modem IP into other cellular baseband SoC’s.You
will Integrate Analog/Mixed Signal blocks like AFE and high speed PHY’s into the SoC. You will also drive DFT strategies, for yield
improvements, test cost reduction and lowest dppm achievement.Additionally, you will provide guidance and expertise in post-
silicon debug and production.
Education: MSEE + 15yrs or PhD + 12 years of industry experience
Experience in cellular wireless modem IC design
Experience in leading cross functional teams worldwide
Strong communication, analytical and documentation skills
Familiarity with logic simulation, emulation and debug environments.
Knowledge of Synthesis, STA and DFT and Physical design flows.
Experience with Post Silicon validation, qualification and production
6. RTL Design
• Job Description
• Designation: Staff-II/Sr.Staff/Principal /Sr. Principal Engineer
• Experience level: 4-12yrs
Will interact with system/software/Asic architects and IP providers to define functional specifications and architecture of SoC
interfaces.
Responsible for implementation and integration of high-speed SoC interfaces.
Responsibilities include -
Customizing and integrating high-speed interfaces like USB 2.0,HSIC, PCI Express,SDIO 2.0/3.0 etc.
Work with external/internal IP providers to specify analog/mixed-signal IP blocks like physical-layer for USB, PCIe etc.
Integration of analog/mixed-signal IP blocks, implementing testability, power modes etc.
Logic design and verification of key SoC functionality.
Closely work with the back-end team for floor planning and chip-level timing closure.
Post Silicon debug/characterization support of the designs on both ATE and lab environments.
Excellent micro-architecture, logic design and verification skills.
Experience in interfaces like USB 2.0/3.0,HSIC/SSIC, SD/SDIO 2.0/3.0, PCIe, Ethernet, MIPI etc.
Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments.
Knowledge of Synthesis, STA and DFT. Knowledge scripting desirable.
Experience with ARM based SoCs, AHB/AXI fabric and low power implementation is desirable.
Experience with post-silicon validation and debug. Should have strong communication, analytical and documentation skills
7. Asic package design
• Job Description
• Designation: Staff-II/Sr.Staff/Principal /Sr. Principal Engineer
• Experience level: 4-12yrs
ASIC Package, Hardware char and performance measurements.
Will be responsible for working with System Architects, Software Architects and ASIC Architects to provide
Package design support, Layout review, Multi-chip module netlist development., development of bump-map/ball-map for
packages, support engineering board design, Engineering functional test setup,
Support Pre and Post Silicon bring up of Embedded mobile SoCs.
Performance measurements of DDR interface, USB, SD interface and Analog and RF circuits is required.
Experience in pre-silicon and post-silicon functional validation is preferred.
Experience with silicon debug support of the design on both ATE and lab environments is preferred
Familiarity with IC package design or board design flow.
Experience with spice and/or analog simulations.
Experience with Hardware/board debug
Familiarity with FPGA based RTL Level Logic design, simulation and debug environments.
Experience with performance measurements of Digital, Analog and RF circuits.
Experience with development of automated instrument test setups using GPIB or Serial or Ethernet will be preferable.
Proficiency with c or assembly level coding. Knowledge in scripting desirable.
Should have strong communication, analytical and documentation skills
8. Physical Layer Design
• Job Description
• Designation: Staff-II/Sr.Staff/Principal /Sr. Principal Engineer
• Experience level: 2-15yrs
Broadcom is developing solutions supporting the next generation of 3G and 4G high-speed mobile technologies. In this role you
will be an integral member of the 4G System Design Engineering team in the mobile group. You will understand software product
requirements and translate them to production worthy software code. You will grow in this role to own several areas of domain
expertise. The ideal candidate will have deep level of understanding of digital/analog communication systems, embedded and real
time concepts, good programming skills and strong analytical skills with a systematic problem solving approach. The role involves:
1) Design, development, documentation, reviews, integration and testing of physical layer firmware and control modules on
DSP/RISC processors
2) Integration of software with Baseband and RF chipsets in an embedded environment, participating in interoperability test, field
trials and customer support
3) Cross-team interaction with Protocol software, chip design (baseband/RF), physical layer algorithms/simulation, hardware
reference design and customer interfacing teams Job Requirements
1) BE/B.Tech/ME/MS/M.Tech in Electrical, Electronics or Communication Engineering from reputed institutes
2 work experience in wireline/wireless domain in embedded product space
3) Strong fundamentals in digital and analog communication theory, embedded and real time firmware development
4) Strong programming skills (C/Assembly)
5) Knowledge of SCM tools and the entire life cycle software development process
6) Working knowledge of MATLAB for data analysis
7) Background in analysis and design of physical layer algorithms for real time embedded wireless products
8) Working knowledge of usage of lab tools, channel emulators and analyzers
9) Strong debugging skills in the embedded and real time environment using JTAG, oscilloscope and logic analyzers
9. FOR MORE INFORMATION PLEASE MAIL ME
Kathiravan | Sourcing Specialist, Human Resources
Broadcom Corporation | E-mail:kathirav@broadcom.com
