8051 microcontroller

Introduction
Block Diagram and Pin Description of the 8051
Registers
Memory mapping in 8051
I/O Port Programming
Timer
Interrupt
A.Azhagu Jaisudhan RIT ECE

 The microprocessor is the core of computer
systems.
 Nowadays many communication, digital
entertainment, portable devices, are
controlled by them.
 A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.

 Hardware :Interface to the real world
 Software :order how to deal with inputs

 CPU: Central Processing Unit
 I/O: Input /Output
 Bus: Address bus & Data bus
 Memory: RAM & ROM
 Timer
 Interrupt
 Serial Port
 Parallel Port

CPU
General-
Purpose
Micro-
processor
RAM ROM I/O
Port
Timer
Serial
COM
Port
Data Bus
Address Bus
General-Purpose Microprocessor System
 CPU for Computers
 No RAM, ROM, I/O on CPU chip itself
 Example：Intel’s x86, Motorola’s 680x0
Many chips on mother’s board
General-purpose microprocessor

RAM ROM
I/O
Port
Timer
Serial
COM
Port
Microcontroller
CPU
 A smaller computer
 On-chip RAM, ROM, I/O ports...
 Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X
A single chip
Microcontroller :

Microprocessor
 CPU is stand-alone, RAM,
ROM, I/O, timer are
separate
 designer can decide on the
amount of ROM, RAM and
I/O ports.
 expansive
 general-purpose
Microcontroller
• CPU, RAM, ROM, I/O and
timer are all on a single chip
• fix amount of on-chip ROM,
RAM, I/O ports
• Not expansive
• single-purpose
Microprocessor vs. Microcontroller

CPU
On-chip
RAM
On-chip
ROM for
program
code
4 I/O Ports
Timer 0
Serial
PortOSC
Interrupt
Control
External interrupts
Timer 1
Timer/Counter
Bus
Control
TxD RxDP0 P1 P2 P3
Address/Data
Counter
Inputs

 The Intel 8051 is a very popular general purpose microcontroller
widely used for small scale embedded systems.
 Many vendors such as Atmel, Philips, and Texas Instruments
produce MCS-51 family microcontroller chips.
 The 8051 is an 8-bit microcontroller with 8 bit data bus and 16-
bit address bus.
 The 16 bit address bus can address a 64K( 216) byte code
memory space and a separate 64K byte of data memory space.
 The 8051 has 4K on-chip read only code memory and 128 bytes
of internal Random Access Memory (RAM)

 Besides internal RAM, the 8051 has various Special Function Registers
(SFR) such as the Accumulator, the B register, and many other control
registers.
 34 8-bit general purpose registers in total.
The ALU performs one 8-bit operation at a time.
 Two 16 bit /Counter timers
 3 internal interrupts (one serial), 2 external interrupts.
 4 8-bit I/O ports (3 of them are dual purposed). One of them used for
serial port
 Some 8051 chips come with UART for serial communication and ADC
for analog to digital conversion.

40 pins on the 8051 chip.
Most of these pins are used to connect to I/O devices or external data
and code memory.
 4 I/O port take 32 pins(4 x 8 bits) plus a pair of XTALS pins for
crystal clock
 A pair of Vcc and GND pins for power supply (the 8051 chip
needs +5V 500mA to function properly)
 A pair of timer pins for timing controls, a group of pins (EA, ALE,
PSEN, WR, RD) for internal and external data and code memory
access controls
 One Reset pin for reboot purpose

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
30
29
28
27
26
25
24
23
22
21
31
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
XTAL 2
XTAL 1
GND
Vcc
P0.0(AD0)
P2.0(A8)
P2.1(A9)
P2.2(A10)
P2.3(A11)
P2.4(A12)
P2.5(A13)
P2.6(A14)
P2.7(A15)
PSEN
ALE/PROG
EA/VPP
P0.6(AD6)
P0.7(AD7)
P0.5(AD5)
P0.4(AD4)
P0.3(AD3)
P0.2(AD2)
P0.1(AD1)
(RD) P3.7
P1.7
(Serial)
interrupt
Timer
Ex M W/R
clock
Ext
Memory
Address
Ext Memory
Access Control
Ext Memory
Address
8051
Pin out Diagram of the 8051 MicrocontrollerA.Azhagu Jaisudhan RIT ECE

Port 0
(enable Ex. Memory)
Port 2
ALE Address Latch Enable
EA’
PSEN’
RD’
WR’ Ex.Data RAM write
OE’
A8 - A15
A0 – A7
D0 – D7
Ex. Data RAM Reade
Extensl Code Memory
ROM or EPROM
8051
adress
multiplex
latch
The Pin Connection for External Code and Data Memory

 The EA' (External Access) pin is used to control the internal or
external memory access.
The signal 0 is for external memory access and
signal 1 for internal memory access.
 The PSEN' (Program Store Enable) is for reading external
code memory when it is low (0) and EA is also 0.

 The ALE (Address Latch Enable) activates the port 0 joined with port 2 to
provide 16 bit external address bus to access the external memory. The
ALE multiplexes the P0:
1 for latching address on P0 as A0-A7 in the 16 bit address buss, 0
for latching P0 as data I/O.
 P0.x is named ADx because P0 is multiplexed for Address bus and Data
bus at different clock time.
WR' only provides the signal to write external data memory
RD' provides the signal to read external data and code memory.

 The 8051 requires an external oscillator circuit. The
oscillator circuit usually runs around 12MHz. the
crystal generates 12M pulses in one second. The pulse
is used to synchronize the system operation in a
controlled pace..
 A machine cycle is minimum amount time a simplest
machine instruction must take
 An 8051 machine cycle consists of 12 crystal pulses
(clock cycle).
 instruction with a memory operand so that it needs
multiple memory accesses.

The first 6 crystal pulses (clock cycle) is used to fetch
the opcode and the second 6 pulses are used to
perform the operation on the operands in the ALU.
This gives an effective machine cycle rate at 1MIPS
(Million Instructions Per Second).
XTAL!
XTAL2
GND
Crystal
Crystal to 8051 XTAL 1/2A.Azhagu Jaisudhan RIT ECE

 The 8031 requires external instruction memory.
◦ It can be as large as 64K Bytes.
◦ You lose 2 ports for interfacing to the external memory.
 You can replace these by interfacing the chip to an I/O
port controller like the 8255.
 The 8051 is the original member of the Intel MCS-51 family
of Microcontrollers.
◦ There are several varieties that differ slightly in the
available features.

 Programmer’s View
◦ Memory Organization
◦ Register Set
◦ Instruction Set
 Hardware Designer’s View
◦ Pin-out
◦ Timing characteristics
◦ Current / Voltage requirements

 Internal ROM and RAM
 I/O Ports with programmable Pins
 ALU
 Working Registers
 Clock Circuits
 Timers and Counters
 Serial Data Communication.

 The CPU has many important registers. The Program Count
(PC) always holds the code memory location of next
instruction.
 The CPU is the heart of any computer which is in charge of
computer operations.
 It fetches instructions from the code memory into the
instruction Register (IR), analyzes the opcode of the
instruction.
 updates the PC to the location of next instruction, fetches the
operand from the data memory if necessary, and finally
performs the operation in the Arithmetic-Logic Unit (ALU)
within the CPU.

 The B register is a register just for multiplication and
division operation which requires more register
spaces for the product of multiplication and the
quotient and the remainder for the division.
 The immediate result is stored in the accumulator
register (Acc) for next operation and the Program
Status Word (PSW) is updated depending on the
status of the operation result

 Commonly used as a temporary registe
 Used by two op-codes
◦ MUL AB, div AB
 B register holds the second operand and will hold
part of the result
◦ Upper 8 bits of the multiplication result
◦ Remainder in case of division.
 Bit addressable.

 Two 8-bit registers that can be combined into a 16-bit
DPTR – Data Pointer.
 Used by commands that access external memory
 Also used for storing 16bit values
mov DPTR, #data16
; setup DPTR with 16bit ext address
movx A, @DPTR
; copy mem[DPTR] to A
 Can be accessed as 2 separate 8-bit registers if needed.
 DPTR is useful for string operations and Look-Up-Table
(LUT) operations.

 SP is the stack pointer.
 SP points to the last used location of the stack.
◦ Push operation will first increment SP and then copy data.
◦ Pop operation will first copy data and then decrement SP.
 In 8051, stack grows upwards (from low memory to high
memory) and can be in the internal RAM only.
 On power-up, SP points to 07H.
◦ Register banks 2,3,4 (08H to 1FH) form the default stack
area.
 Stack can be relocated by setting SP to the upper memory
area in 30H to 7FH.
◦ mov SP, #32H

 Totally 34 general purpose registers or working registers.
 Two of these A and B hold results of many instructions,
particularly math and logical operations of 8051 cpu.
 The other 32 are in four banks,B0 – B3 of eight registers
each.
 A(accumulator) is used for
addition,subtraction,mul,div,boolean bit manipulation and
for data transfers.
 But B register can only be used for mul and div operations.

 Serial Port Data Buffer.
 2 registers at the same location
◦ One is read-only used for reading serial input data.
 Serial Data Receive Buffer.
◦ The other is write-only used for storing serial
output data.
 Serial Data Transmit Buffer.
A.Azhagu Jaisudhan RIT ECE Link: SFR address

 The high and low bytes of the 16-bit counting
register for timer/counter T0.
 There is also a TH1 / TL1 pair for the T1 timer.
 In the 8052, one more pair exists (TH2) / (TL2) for
the T2 timer.
 (RCAP2H) and (RCAP2L) exist only in the 8052 and
they are copies of the TH2 and TL2 registers.

 IP – Interrupt Priority.
 IE – Interrupt Enable.
 TMOD – Timer Mode.
 TCON – Timer Control.
 T2CON – Timer 2 Control (8052)
 SCON – Serial Port Control.
 PCON – Power Control (80C51).

 Program Status Word is a “bit addressable” 8-bit
register that has all the flags.
MSB LSB
CY AC F0 RS1 RS2 OV - P
Symbol Position Function
CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry Flag. For BCD
Operations
F0 PSW.5 Flag 0. Available to the user for general
purposes.
RS1 PSW.4 Register bank select bits. Set by
software to determine which register
bank is being used.
RS2 PSW.3
OV PSW.2 Overflow Flag
- PSW.1 Not used
P PSW.0 Parity Flag. Even Parity.

 PSW Register
CY AC F0 RS1 OVRS0 P--
CYPSW.7Carry flag
ACPSW.6Auxiliary carry flag
--PSW.5Available to the user for general purpose
RS1PSW.4Register Bank selector bit 1
RS0PSW.3Register Bank selector bit 0
OVPSW.2Overflow flag
--PSW.1User define bit
PPSW.0Parity flag Set/Reset odd/even parity
RS1 RS0 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH

There are 4 8-bit ports: P0, P1, P2 and P3. All of them are dual
purpose ports except P1 which is only used for I/O. The
following diagram shows a single bit in an 8051 I/O port.
Internal data bus(one bit)
D Q
CL Q’
Latch
Read latch Read pin
Vcc(5v)
Port pin
10k
FET
Single Bit In I/O Port

 PORT P1 (Pins 1 to 8): The port P1 is a port dedicated for general
I/O purpose. The other ports P0, P2 and P3 have dual roles in
addition to their basic I/O function.
 PORT P0 (pins 32 to 39): When the external memory access is
required then Port P0 is multiplexed for address bus and data
bus that can be used to access external memory in conjunction
with port P2. P0 acts as A0-A7 in address bus and D0-D7 for port
data. It can be used for general purpose I/O if no external
memory presents.
 PORT P2 (pins 21 to 28): Similar to P0, the port P2 can also play a
role (A8-A15) in the address bus in conjunction with PORT P0 to
access external memory.

 PORT P3 (Pins 10 to 17):
In addition to acting as a normal I/O port,
 P3.0 can be used for serial receive input pin(RXD)
 P3.1 can be used for serial transmit output pin(TXD)
in a serial port,
 P3.2 and P3.3 can be used as external interrupt
pins(INT0’ and INT1’),
 P3.4 and P3.5 are used for external counter input
pins(T0 and T1),
 P3.6 and P3.7 can be used as external data memory
write and read control signal pins(WR’ and RD’)read
and write pins for memory access.

The 8051 has separate address spaces for
program storage and data storage.
◦ Depending on the type of instruction, the same
address can refer to two logically and physically
different memory locations.

 After reset, the MCS-51 starts fetching instructions
from 0000H.
◦ This can be either on-chip or external depending
on the value of the EA input pin.
 If EA* is low, then the program memory is external.
 If EA* is high, then addresses from 0000 to 0FFF will
refer to on-chip memory and addresses 1000 up to
FFFF refer to external memory.
◦ Note that the 8031 must have its EA connected
low as all of its memory is external.
A.Azhagu Jaisudhan RIT ECE Link: EA connection

 Port 0 acts as a multiplexed address/data bus.
Sending the low byte of the program counter (PCL)
as an address.
 Port 2 sends the program counter high byte (PCH)
directly to the external memory.
 The signal ALE operates as in the 8051 to allow an
external latch to store the PCL byte while the
multiplexed bus is made ready to receive the code
byte from the external memory.
 Port 0 then switches function and becomes the
data bus receiving the byte from memory.
A.Azhagu Jaisudhan RIT ECE Link: H/w Interfacing

 The 8051 has 256 bytes of RAM on-chip.
◦ The lower 128 bytes are intended for internal
data storage.
◦ The upper 128 bytes are the Special Function
Registers (SFR).
 The lower 128 bytes are not to be used as standard
RAM.
◦ Internally 8051’s registers default to stack area,
and other features. [00-7FH]
A.Azhagu Jaisudhan RIT ECELink: Memory Organization

 The lowest 32 bytes of the on-chip RAM form 4
banks of 8 registers each.
 Only one of these banks can be active at any time.
 Bank is chosen by setting 2 bits in PSW
◦ Default bank (at power up) is bank 0 (locations 00 – 07).
 The 8 registers in any active bank are referred to as
R0 through R7
 Given that each register has a specific address, it can
be accessed directly using that address even if its
bank is not the active one.

 The next 16 bytes – locations 20H to 2FH – form a
block that can be addressed as either bytes or
individual bits.
◦ The bytes have addresses 20H to 2FH.
◦ The bits have addresses 00H to 7FH.
◦ Specific instructions are used for accessing
the bits.
 Locations 30H to 7FH are general purpose RAM.
A.Azhagu Jaisudhan RIT ECELink: Memory Organization

 The upper 128 bytes of the on-chip RAM are used to house
special function registers.
 In reality, only about 25 of these bytes are actually used.
The others are reserved for future versions of the 8051.
◦ These are registers associated with important functions in
the operation of the MCS-51.
◦ Some of these registers are bit-addressable as well as
byte-addressable.
 The address of bit 0 of the register will be the same as
the address of the register.

 ACC and B registers – 8 bit each
 DPTR : [DPH:DPL] – 16 bit combined
 PC (Program Counter) – 16 bits
 SP (Stack Pointer) – 8 bit
 PSW (Program Status Word)
 Port Latches
 Serial Data Buffer
 Timer Registers
 Control Registers
A.Azhagu Jaisudhan RIT ECE Link: SFR Elements

 When connecting an 8051 to an external memory, the 8051
uses ports to send addresses and read instructions.
◦ 16-bit address：P0 provides both address A0-A7, P2 provides address
A8-A15.
◦ Also, P0 provides data lines D0-D7.
 When P0 is used for address/data multiplexing, it is
connected to the 74LS373 to latch the address.
I/O Port Programming


Port 1（pins 1-8）
 Port 1 is denoted by P1.
◦ P1.0 ~ P1.7
◦ P1 as an output port (i.e., write CPU data to the external pin)
◦ P1 as an input port (i.e., read pin data into CPU bus)

 The ALE pin is used for de-multiplexing the address
and data by connecting to the G pin of the 74LS373
latch.
◦ When ALE=0, P0 provides data D0-D7.
◦ When ALE=1, P0 provides address A0-A7.
◦ The reason is to allow P0 to multiplex address and data.

 Although port 3 is configured as an output port upon reset,
this is not the way it is most commonly used.
 Port 3 has the additional function of providing signals.
◦ Serial communications signal：RxD, TxD
◦ External interrupt：/INT0, /INT1
◦ Timer/counter：T0, T1
◦ External memory accesses ：/WR, /RD

17RDP3.7
16WRP3.6
15T1P3.5
14T0P3.4
13INT1P3.3
12INT0P3.2
11TxDP3.1
10RxDP3.0
PinFunctionP3 Bit


 Immediate
 Register
 Direct
 Register Indirect
 Indexed
The way in which the instruction is
specified.

 Immediate Data is specified in the instruction itself
 Egs:
MOVA,#65H
MOVA,#’A’
MOVR6,#65H
MOVDPTR,#2343H
MOVP1,#65H

MOVRn, A ;n=0,..,7
ADD A, Rn
MOVDPL, R6
MOVDPTR, A
MOVRm, Rn

Although the entire of 128 bytes of RAM can be
accessed using direct addressing mode, it is most often
used to access RAM loc. 30 – 7FH.
MOVR0, 40H
MOV56H, A
MOVA, 4 ; ≡ MOV A, R4
MOV6, 2 ; copy R2 to R6
; MOV R6,R2 is invalid !

 In this mode, register is used as a pointer to the data.
MOV A,@Ri
; move content of RAM loc. Where address is held by Ri into
A
( i=0 or 1 )
MOV @R1,B
In other word, the content of register R0 or R1 is sources or
target in MOV, ADD and SUBB insructions.
 jump

 This mode is widely used in accessing data elements
of look-up table entries located in the program
(code) space ROM at the 8051
MOVC A,@A+DPTR
A= content of address A +DPTR from ROM
Note:
Because the data elements are stored in the program
(code ) space ROM of the 8051, it uses the
instruction MOVC instead of MOV. The “C” means
code.

[Instruction Set]

[ label: ] mnemonic[operands] [
;comment ]
Example:
MOV R1, #25H ; load data 25H into
R1

 Registers
MOV Instruction:
MOV destination, source
Example:
1. MOV A, $55H
2. MOV R0, A
3. MOV A, R3

 The 8051 has 255 instructions
◦ Every 8-bit opcode from 00 to FF is used except
for A5.
 The instructions are grouped into 5 groups
◦ Arithmetic
◦ Logic
◦ Data Transfer
◦ Boolean
◦ Branching

 ADD
◦ 8-bit addition between the accumulator (A) and a
second operand.
 The result is always in the accumulator.
 The CY flag is set/reset appropriately.
 ADDC
◦ 8-bit addition between the accumulator, a second
operand and the previous value of the CY flag.
 Useful for 16-bit addition in two steps.

 DA
◦ Decimal adjust the accumulator.
 Format the accumulator into a proper 2 digit packed BCD
number.
 Operates only on the accumulator.
 Works only after the ADD instruction.
 SUBB
◦ Subtract with Borrow.
 Subtract an operand and the previous value of the borrow
(carry) flag from the accumulator.
 A  A - <operand> - CY.
 The result is always saved in the accumulator.

 INC
◦ Increment the operand by one.
 The operand can be a register, a direct address, an
indirect address, the data pointer.
 DEC
◦ Decrement the operand by one.
 The operand can be a register, a direct address, an
indirect address.
 MUL AB / DIV AB
◦ Multiply A by B and place result in A:B.
◦ Divide A by B and place result in A:B.

 ANL / ORL
◦ Work on byte sized operands or the CY flag.
 ANL A, Rn
 ANL A, direct
 ANL A, @Ri
 ANL A, #data
 ANL direct, A
 ANL direct, #data
 ANL C, bit
 ANL C, /bit

 XRL
◦ Works on bytes only.
 CPL / CLR
◦ Complement / Clear.
◦ Work on the accumulator or a bit.
 CLR P1.2

 RL / RLC / RR / RRC
◦ Rotate the accumulator.
 RL and RR without the carry
 RLC and RRC rotate through the carry.
 SWAP A
◦ Swap the upper and lower nibbles of the
accumulator.
 No compare instruction.
◦ Built into conditional branching instructions.

 MOV
◦ 8-bit data transfer for internal RAM and the SFR.
 MOV A, Rn MOV A, direct
 MOV A, @Ri MOV A, #data
 MOV Rn, A MOV Rn, direct
 MOV Rn, #data MOV direct, A
 MOV direct, Rn MOV direct, direct
 MOV direct, @Ri MOV direct, #data
 MOV @Ri, A MOV @Ri, direct
 MOV @Ri, #data

 MOV
◦ 1-bit data transfer involving the CY flag
 MOV C, bit
 MOV bit, C
 MOV
◦ 16-bit data transfer involving the DPTR
 MOV DPTR, #data

 MOVC
◦ Move Code Byte
 Load the accumulator with a byte from program
memory.
 Must use indexed addressing
 MOVC A, @A+DPTR
 MOVC A, @A+PC

 MOVX
◦ Data transfer between the accumulator and a byte
from external data memory.
 MOVX A, @Ri
 MOVX A, @DPTR
 MOVX @Ri, A
 MOVX @DPTR, A

 PUSH / POP
◦ Push and Pop a data byte onto the stack.
◦ The data byte is identified by a direct address from
the internal RAM locations.
 PUSH DPL
 POP 40H

 XCH
◦ Exchange accumulator and a byte variable
 XCH A, Rn
 XCH A, direct
 XCH A, @Ri
 XCHD
◦ Exchange lower digit of accumulator with the lower digit of
the memory location specified.
 XCHD A, @Ri
 The lower 4-bits of the accumulator are exchanged with
the lower 4-bits of the internal memory location identified
indirectly by the index register.
 The upper 4-bits of each are not modified.

 This group of instructions is associated with the
single-bit operations of the 8051.
 This group allows manipulating the individual bits
of bit addressable registers and memory locations
as well as the CY flag.
◦ The P, OV, and AC flags cannot be directly
altered.
 This group includes:
◦ Set, clear, and, or complement, move.
◦ Conditional jumps.

 CLR
◦ Clear a bit or the CY flag.
 CLR P1.1
 CLR C
 SETB
◦ Set a bit or the CY flag.
 SETB A.2
 SETB C
 CPL
◦ Complement a bit or the CY flag.
 CPL 40H ; Complement bit 40 of the bit
addressable memory

 ORL / ANL
◦ OR / AND a bit with the CY flag.
 ORL C, 20H ; OR bit 20 of bit addressable
; memory with the CY flag
 ANL C, /34H ; AND complement of bit 34 of bit
addressable memory with the CY
flag.
 MOV
◦ Data transfer between a bit and the CY flag.
 MOV C, 3FH ; Copy the CY flag to bit 3F of the
bit addressable memory.
 MOV P1.2, C; Copy the CY flag to bit 2 of P1.

 JC / JNC
◦ Jump to a relative address if CY is set / cleared.
 JB / JNB
◦ Jump to a relative address if a bit is set / cleared.
 JB ACC.2, <label>
 JBC
◦ Jump to a relative address if a bit is set and clear the
bit.

 The 8051 provides four different types of
unconditional jump instructions:
◦ Short Jump – SJMP
 Uses an 8-bit signed offset relative to the 1st byte of the
next instruction.
◦ Long Jump – LJMP
 Uses a 16-bit address.
 3 byte instruction capable of referencing any location in
the entire 64K of program memory.

◦ Absolute Jump – AJMP
 Uses an 11-bit address.
 2 byte instruction
 The upper 3-bits of the address combine with the 5-bit
opcode to form the 1st byte and the lower 8-bits of the
address form the 2nd byte.
 The 11-bit address is substituted for the lower 11-bits of
the PC to calculate the 16-bit address of the target.
 The location referenced must be within the 2K Byte
memory page containing the AJMP instruction.
◦ Indirect Jump – JMP
 JMP @A + DPTR

 The 8051 provides 2 forms for the CALL instruction:
◦ Absolute Call – ACALL
 Uses an 11-bit address similar to AJMP
 The subroutine must be within the same 2K page.
◦ Long Call – LCALL
 Uses a 16-bit address similar to LJMP
 The subroutine can be anywhere.
◦ Both forms push the 16-bit address of the next
instruction on the stack and update the stack pointer.

 The 8051 provides 2 forms for the return instruction:
◦ Return from subroutine – RET
 Pop the return address from the stack and continue
execution there.
◦ Return from ISV – RETI
 Pop the return address from the stack.
 Restore the interrupt logic to accept additional
interrupts at the same priority level as the one just
processed.
 Continue execution at the address retrieved from
the stack.
 The PSW is not automatically restored.

 The 8051 supports 5 different conditional jump
instructions.
◦ ALL conditional jump instructions use an 8-bit signed
offset.
◦ Jump on Zero – JZ / JNZ
 Jump if the A == 0 / A != 0
 The check is done at the time of the instruction
execution.
◦ Jump on Carry – JC / JNC
 Jump if the C flag is set / cleared.

◦ Jump on Bit – JB / JNB
 Jump if the specified bit is set / cleared.
 Any addressable bit can be specified.
◦ Jump if the Bit is set then Clear the bit – JBC
 Jump if the specified bit is set.
 Then clear the bit.

 Compare and Jump if Not Equal – CJNE
◦ Compare the magnitude of the two operands and
jump if they are not equal.
 The values are considered to be unsigned.
 The Carry flag is set / cleared appropriately.
 CJNE A, direct, rel
 CJNE A, #data, rel
 CJNE Rn, #data, rel
 CJNE @Ri, #data, rel

 Decrement and Jump if Not Zero – DJNZ
◦ Decrement the first operand by 1 and jump to the
location identified by the second operand if the
resulting value is not zero.
 DJNZ Rn, rel
 DJNZ direct, rel
 No Operation
◦ NOP

MOV dest,source ; dest = source
MOV A,#72H ;A=72H
MOV R4,#62H ;R4=62H
MOV B,0F9H ;B=the content of F9’th byte of RAM
MOV DPTR,#7634H
MOV DPL,#34H
MOV DPH,#76H
MOV P1,A ;mov A to port 1
Note 1:
MOV A,#72H ≠ MOV A,72H
After instruction “MOV A,72H ” the content of 72’th byte of RAM will
replace in Accumulator.
Note 2:
MOV A,R3 ≡ MOV A,3

ADD A, Source ;A=A+SOURCE
ADD A,#6 ;A=A+6
ADD A,R6 ;A=A+R6
ADD A,6 ;A=A+[6] or A=A+R6
ADD A,0F3H ;A=A+[0F3H]
SUBB A, Source ;A=A-SOURCE-C
SUBB A,#6 ;A=A-6
SUBB A,R6 ;A=A+R6

 MUL AB ;B|A = A*B
MOV A,#25H
MOV B,#65H
MUL AB ;25H*65H=0E99
;B=0EH, A=99H
 DIV AB ;A = A/B, B = A mod B
MOV A,#25
MOV B,#10
DIV AB ;A=2, B=5

SETB bit ; bit=1
CLR bit ; bit=0
SETB C ; CY=1
SETB P0.0 ;bit 0 from port 0 =1
SETB P3.7 ;bit 7 from port 3 =1
SETB ACC.2 ;bit 2 from ACCUMULATOR =1
SETB 05 ;set high D5 of RAM loc. 20h
Note:
CLR instruction is as same as SETB
i.e.:
CLR C ;CY=0
But following instruction is only for CLR:
CLR A ;A=0

DEC byte ;byte=byte-1
INC byte ;byte=byte+1
INC R7
DEC A
DEC 40H ; [40]=[40]-1

RR – RL – RRC – RLC A
EXAMPLE:
RR A
RR:
RRC:
RL:
RLC:
C
C

DJNZ:
Write a program to clear ACC, then
add 3 to the accumulator ten time
Solution:
MOV A,#0
MOV R2,#10
AGAIN: ADD A,#03
DJNZ R2,AGAIN ;repeat until R2=0 (10 times)
MOV R5,A

Example:
Write a program to copy a block of 10 bytes from RAM location
starting at 37h to RAM location starting at 59h.
Solution:
MOV R0,#37h ; source pointer
MOV R1,#59h ; dest pointer
MOV R2,#10 ; counter
L1: MOV A,@R0
MOV @R1,A
INC R0
INC R1
DJNZ R2,L1

 ORG 0000H
 MOV A, #05H
 MOV R, #09H
 ADD A, R1
 MOV DPTR, #2050H
 MOV @ DPTR, A
 AGAIN: SJMP AGAIN

Example: Read the content of external RAM
locations 10F4H and 10F5H and place values in
R6 and R7, respectively.
MOV DPTR,#10F4H
MOVX, A,@DPTR
MOV R6,A
INC DPTR
MOVX A,@DPTR
MOV R7,A

 mov dptr,#4200h
 movx a,@dptr
 mov b,a
 mul ab
 inc dptr
 movx @dptr,a
 inc dptr
 mov a,b
 movx @dptr,a
 l:sjmp l

 mov dptr,#4200h
 movx a,@dptr
 cpl a
 add a,#01h
 inc dptr
 movx @dptr,a
 l:sjmp l

 mov dptr,#4200h
 movx a,@dptr
 mov b,a
 anl a,#0fh
 add a,#30h
 mov r0,a
 mov a,b
 swap a
 anl a,#0fh
 add a,#30h
 mov r1,a
 inc dptr
 mov a,r0
 movx @dptr,a
 inc dptr
 mov a,r1
 movx @dptr,a
 l:sjmp l

TEXT BOOKS:
 1. Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 /
8088 Family - Architecture, Programming and Design”, Second Edition,
Prentice Hall of India, 2007. (UNIT I- III)
 2. Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay, “The
8051 Microcontroller and Embedded Systems: Using Assembly and C”,
Second Edition, Pearson education, 2011. (UNIT IV-V
REFERENCE:
 1. Doughlas V.Hall, “Microprocessors and Interfacing, Programming and
Hardware”, TMH, 2012
 2. A.K.Ray,K.M.Bhurchandi,‖Advanced Microprocessors and Peripherals
―3rd edition, TataMcGrawHill,2012
 3. SK Mandal, “Microprocessor and Microcontroller”, Tata Mc Graw Hill
Education.
 4. NagoorKani, “Microprocessor and Microcontroller” Tata Mc Graw Hill
Education.


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