Project Reportfinal-black & white

Application of VHDL for the
Design Of a Traffic Light
Intersection & Car Alarm
System
A Project Report Submitted for the fulfillment of Summer Internship under the
Student Internship programme(SIP),NIT Rourkela.
By
Arnab Mitra
Kalinga Institute of Industrial Technology
B.Tech (EEE)
Department Of Electronics Engineering
National Institute of Technology
Rourkela
May-June 2014

Application of VHDL for the
Design Of a Traffic Light
Intersection & Car Alarm
System
A Project Report Submitted for the fulfillment of Summer Internship under the
Student Internship programme(SIP),NIT Rourkela.
By
Arnab Mitra
Kalinga Institute of Industrial Technology
B.Tech (EEE)
Under the supervision of
Ayas Kanta Swain
Department of Electronics And Communication
Department Of Electronics Engineering
Rourkela
May-June 2014

Summer Internship Programme, NIT Rourkela Page 3
Rourkela
CERTIFICATE
This is to certify that the Project Report entitled "Application of VHDL for the
Design of Traffic Light Intersection & Car Alarm System" submitted by Arnab
Mitra in fulfilment for the requirements for the completion of Summer Internship
under Student Internship Programme, NIT Rourkela(Deemed University) is a
authentic work carried out by him under my supervision and guidance.
To the best of my knowledge, the matter embodied in the thesis has not been
submitted to any other University / Institute for the award of any Degree or Diploma.
Date: Prof. Ayas Kanta Swain
Dept. of Electronics and Communication Engg
Rourkela-769008
Prof. Sukadev Meher
Head of Department
Dept. of Electronics and Communication Engg
Rourkela-769008

ACKNOWLEDGEMENT
I would like to articulate my deep gratitude to my project guide, Asst. Prof. Ayas
Kanta Swain who has been a motivation for carrying out the project. I would also take
the opportunity to thank SIP,NIT Rourkela for providing me such a great opportunity
to work in NIT Rourkela. An assemblage of this nature could never have been
attempted without reference to and inspiration from the works of others whose details
are mentioned in reference section. I acknowledge my indebtedness to all of them. It is
our pleasure to refer Microsoft Word exclusive of which the compilation of this report would
have been impossible.
Arnab Mitra

Table of Contents
Abstract ....................................................................................................................................6
Introduction ............................................................................................................................7
Motivation...............................................................................................................................9
Organization Of Work/Report...........................................................................................10
Study of VHDL................................................................................................11
Chapter 1:Introduction To VHDL.....................................................................................12
Introduction .................................................................................................................................... 13
Design of Combinational Circuits ...........................................................................................15
Simulation & Comparison of Adder Architecture ........................................................... 23
Design of Sequential Circuits ...........................................................................................26
Design of Counters and use of IP Cores............................................................... 28
FPGA implementation of Counters..........................................................31
Chapter 2:VHDL Implementation of Traffic Light Intersection ................................34
Introduction .................................................................................................................................... 35
Design Summary........................................................................................................................35
Problem Description............................................................................................................. 36
Design Problem Description............................................................................................36
Design ....................................................................................................................... 37
Design Summary.........................................................................................39
Chapter 3:VHDL Implementation of Car Alarm System.............................................41
Introduction .................................................................................................................................... 42
Problem Statement/Model Description .................................................................................42
Design..................................................................................................................................... 43
Design Summary...............................................................................................................58
Chapter 4:Circuit Implementation Of Digital Circuit Using Cadence......................59
Introduction .................................................................................................................................... 60
Cadence Environment...............................................................................................................61

Design of Basic Gates............................................................................................................ 62
Design of Combinational Circuits ..................................................................................68
Cadence Virtuoso Layout Suite ............................................................................. 71
Conclusion.............................................................................................................................72
Reference ...............................................................................................................................73

Abstract
2014
-:Abstract:-
In the times of exploding population religiously congested roads proper traffic intersection
system is the need of the hour. The Indian Traffic system has always been manually
controlled or semi automatic. In the present times there is a urgent need of a automatic
Traffic Intersection System which would gauge the density of traffic on a particular road and
switch accordingly. In the present system pedestrians face a lot of trouble crossing the roads
which often compel them to jaywalk leading to accidents.
The Car ' burglar ' Alarm system is a solution to the increasing number of car thefts.
The system has been so programmed that it can have varied applications such as it could be
even used as a locking system for houses.
The key advantage of VHDL when used for systems design is that it allows the behaviour of
the required system to be described (modelled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires) and information theory. To start
coding in VHDL, one needs a simulation tool. The simulation tool that we have used here is
Xilinx ISE13.1.First the required code for both the alarm system and traffic intersection
system was written in VHDL and simulated so as to obtain the required output waveforms.
After the coding was completed, VHDL model is translated into the "gates and wires" that are
mapped onto a programmable logic device(PLDs). The programmable logic device used here
is Spartan-3E.
Simultaneously the real time analysis of the model was performed by ChipScope Pro. We
provide the values of inputs for a particular instance the outputs for that particular instance
was displayed.
The above coding and dumping methods were completed and the output was observed on
FPGA kit. The traffic Intersection and Car Alarm code was implemented using VHDL while
dumping was done using Spartan-3E kit.

Introduction
2014
-:Introduction:-
The ever growing number of vehicles on the road provides distinct evidence of urbanization
and growth. But along with this positive side comes a negative implication. While it is true
that not 100% of automobiles get involved in accidents, along with the increasing number of
motor vehicles the number of traffic related mishaps have risen. In an urbanized place, it is
not uncommon to see a traffic light quickly switch from red to green or from green to amber
(orange or yellow in some devices). Traffic control has become partially automated in the last
decade but still there is a big segment of manual work in it. Although making the traffic
intersection system automatic means lesser jobs for traffic and safety policemen, it also
means better chances of people following traffic rules.
Car alarms consist of a host of sensors that are connected to a siren. Sensors consist of
switches, pressure sensors and motion detectors. These are connected to a computer which is
part of the vehicle’s alarm system.
When a vehicle is locked and the control unit detects an irregularity such as a door being
unlocked, etc the sensors and switches transmit a message to the control unit which then turns
the siren ON. Motion detectors consisting of mercury-based alarms turns the siren on when a
vehicle starts shaking or vibrating in case of a tow away theft. Apart from the main car
battery, the siren may also be connected to a hidden battery which powers the siren in case
thieves disconnect the car battery which is the siren’s primary source of power.
Generally speaking the traffic intersection system considers two roads, one a heavy density
traffic road(let road 1) and another a low density traffic road(let road 2). Along with that
there is a pedestrian crossing connecting two roads. Ideally the system would be set to allow
traffic at road 1. When there is traffic in road 2 the sensors(ideally pressure sensor) present on
the road would give a signal to the system. On receiving the signal the countdown timer on
road 1 would get started finally turning the signal from green to red. At that instant another
countdown timer at road 2 would get started allowing the traffic a stipulated amount of time
to pass, finally switching back to road 1.
The Car Alarm System consists of three states: armed, disarmed, intrusion. It has three inputs
sensors, remote, reset besides the clock. It is a simple code that would turn ON the siren when
the door is tried to be opened by wrong practices. The door would open only when remote is
operated otherwise Car Lock present inside would prevent opening of the door.

Introduction
2014
VHSIC Hardware Description Language(VHSIC is acronym for Very High Speed Integrated
Circuit) popularly known as VHDL was used for designing both the models.
The key advantage of VHDL, when used for systems design, is that it allows the behavior of
the required system to be described (modelled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires). Another benefit is that VHDL
allows the description of a concurrent system. VHDL is a dataflow language, unlike
procedural computing languages such as BASIC, C, and assembly code, which all run
sequentially, one instruction at a time.
Cadence Virtuoso is one of most popular applications used by engineers in the
semiconductor industry for completing various tasks related to a chip design project. Cadence
circuit design solutions enable fast and accurate entry of design concepts, which includes
managing design intent in a way that flows naturally in the schematic. Using this advanced,
parasitic-aware environment, you can abstract and visualize the many interdependencies of an
analog, RF, or mixed-signal design to understand and determine their effects on circuit
performance.

Motivation
2014
-:Motivation:-
VHDL allows the behavior of the required system to be described (modelled) and verified
(simulated) before synthesis tools translate the design into real hardware (gates and
wires).This feature enables it to be ideally used for applications relating to design of various
devices.
Traffic Accident has increased largely over the last decade. The problem which was non-
existent a few decades back has become a major problem nowadays. VHDL can be applied to
design of a real time traffic intersection controller.
Over the years different policies has been implemented to make roads safer. From the
introduction of traffic Police to Traffic lights a lot of advancements have been made over the
years. But, as the population has been increasing appropriate methods has not been
implemented to control the increase in traffic accidents.
The need of the hour would be a automatic traffic system which would reduce manual labour
and along with that its errors. A lot of automatic systems have been implemented abroad
which are quite efficient but at the other hand very costly. So, keeping the Indian perspective
in mind a simple, cost effective system which would address major of the traffic problems.
VHDL can be applied to design of a real time Car Alarm System. In spite of so many
different car alarms present in the market this code is a simpler and different approach in
designing a car alarm system which can be implemented real time.

Organisation Of Report
2014
-:Organisation of Work/Report:-
My work had been performed in two parts. First, had been the study of VHDL under which
work was majorly based on Traffic System Intersection and Car Alarm System. Second, there
had been a study of cadence virtuso tool.
Chapter 1 deals with the Study of VHDL.VHSIC Hardware Descriptive Language is a
hardware descriptive language used in electronic design automation to describe digital and
mixed signal system. VHDL is explained in brief and the different work done during the
study of VHDL.
Chapter 2 deals describes the Traffic Light Intersection System. It explains the problem,
process decided on to address the problem, VHDL coding along with its test bench and
simulation.
Chapter 3 deals describes the Car Alarm System. It explains the problem, process decided on
to address the problem, VHDL coding along with its test bench and simulation and finally its
real time visualisation on ChipScope Pro .
Chapter 4 introduces Cadence Virtuoso. It is a design tool which uses transistors for
designing various Combinational and Sequential circuits. A Set of designs has been created.

STUDY OF VHDL
 Design and Verification of Combinational Circuits
 Design and Verification of Sequential Circuits
 Design of Car Alarm System
 Design of Traffic Intersection System

2014

VHDL-Introduction
2014
1.1 Introduction:
VHDL is a technology and vendor independent hardware description language. The code
describes behavior or structure of an electronic circuit from which a compliant physical
circuit can be inferred by a compiler. Its main applications include synthesis of digital circuits
onto CPLD/FPGA chips and layout/mask generation for ASIC(application specific integrated
circuit) fabrication. VHDL can also be used as a general purpose parallel programming
language.
VHDL was originally developed at the behest of the U.S Department of Defense in order to
document the behavior of the ASICs that supplier companies were including in equipment.
The idea of being able to simulate the ASICs from the information in this documentation was
so obviously attractive that logic simulators were developed that could read the VHDL files.
The next step was the development of logic synthesis tools that read the VHDL, and output a
definition of the physical implementation of the circuit.
Due to the Department of Defense requiring as much of the syntax as possible to be based on
Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the
development of Ada, VHDL borrows heavily from the Ada programming language in both
concepts and syntax.
VHDL is a acronym for VHSIC Hardware Description Language(VHSIC is acronym for
Very High Speed Integrated Circuit)and resulted from an initiative funded by the U.S.
Department of Defence in the 1980s.It was the first hardware description standardized by the
IEEE, through the 1076 and 1164 standards.
VHDL allows circuit synthesis as well as circuit simulation. The former is the translation of a
source code into a hardware structure that implements the specified functionalities; the latter
is a testing procedure to ensure that such functionalities are achieved by the synthesized
circuit.Some of its features are:
 A language for describing the structural, physical and behavioral characteristics of
digital systems.
 Execution of a VHDL program results in a simulation of the digital system.
o Allows us to validate the design prior to fabrication.
o The definition of the VHDL language provides a range of features that support
simulation of digital systems.
 VHDL supports both structural and behavioral descriptions of a system at multiple
levels of abstraction.
 Structure and behavior are complementary ways of describing systems.

VHDL-Introduction
2014
o A description of the behavior of a system says nothing about the structure or
the components that make up the system.
o There are many ways in which you can build a system to provide the same
behavior.
VHDL Language can be regarded as an integrated amalgam of the following languages:
Sequential language, Concurrent language, net-list language, timing specifications, waveform
generation language.
The language not only defines the syntax but also defines very clear simulation semantics for
each language construct. Therefore, models written in this language can be verified using the
VHDL simulator. It is a strongly typed language and is often verbose to write.
The following are the examples of EDA(electronic design automation)tools for VHDL
synthesis and simulation: Quartus II from Altera, ISE from Xilinx, FPGA advantage,
Leonardo Spectrum(synthesis),and ModelSim(simulation) from Mentor Graphics, Design
Compiler RTL Synthesis from Synopsys, Synplify Pro from Synplicity, and Encounter RTL
from Cadence.
The key advantage of VHDL, when used for systems design,
 VHDL allows the behavior of the required system to be described (modelled) and
verified (simulated) before synthesis tools translate the design into real hardware
(gates and wires).
 VHDL allows the description of a concurrent system. VHDL is a dataflow language,
unlike procedural computing languages such as BASIC, C, and assembly code, which
all run sequentially, one instruction at a time.
 A VHDL project is multipurpose. Being created once, a calculation block can be used
in many other projects. However, many formational and functional block parameters
can be tuned (capacity parameters, memory size, element base, block composition
and interconnection structure).

VHDL-Combinational Circuits
2014
1.2 Design of Combinational Circuits
1.2.1 Combinational circuits: Combinational circuit is circuit in which
we combine the different gates in the circuit for example encoder, decoder, multiplexer and
de-multiplexer. Some of the characteristics of combinational circuits are following.
 The output of combinational circuit at any instant of time, depends only on the levels
present at input terminals.
 The combinational circuit do not use any memory. The previous state of input does
not have any effect on the present state of the circuit.
 A combinational circuit can have a n number of inputs and m number of outputs.
1.2.2 Hdl Implementation:
1.2.2.1 Describing Structure:
Figure 1.1:Example of Structural Description
A digital electronic system can be described as a module with inputs and/or outputs. The
electrical values on the outputs are some function of the values on the inputs. Figure1-1(a)
shows an example of this view of a digital system. The module F has two inputs, A and B,
and an output Y. Using VHDL terminology, we call the module F a design entity, and
theinputs and outputs are called ports. One way of describing the function of a module is to
describe how it is composed of sub-modules. Each of the sub-modules is an instance of some
entity, and the ports of the instances are connected using signals Figure1-1(b) shows how the
entity F might be composed of instances of entities G, H and I. This kind of description is
called a structural description. Note that each of the entities G, H and I might also have a
structural description

2014
1.2.2.2 Describing Behavior:
In many cases, it is not appropriate to describe a module structurally. One such case is a
module which is at the bottom of the hierarchy of some other structural description. For
example, if you are designing a system using IC packages bought from an IC shop, you do
not need to describe the internal structure of an IC. In such cases, a description of the
function performed by the module is required, without reference to its actual internal
structure. Such a description is called a functional or behavioral description. To illustrate this,
suppose that the function of the entity F in Figure1-1(a) is the exclusive-or function. Then a
behavioural description of F could be the Boolean function.
More complex behaviours cannot be described purely as a function of inputs. In systems with
feedback, the outputs are also a function of time. VHDL solves this problem by allowing
description of behaviour in the form of an executable program.
1.2.2.3 Architecture Body:
The architecture body can be modelled by any of the following modelling styles:
 As a set of interconnected components(to represent structure)
 As a set of concurrent assignment statements(to represent dataflow)
 As a set of sequential assignment statements(to represent behavior)
 As any combination of the above three(mixed modelling).
1.2.3 Tools used: For writing the code VHDL module is used and VHDL test
bench is used for observing the signals. All these are present inside the XILINX 13.1
software. After the coding, VHDL model is translated into the "gates and wires" that are
mapped onto a programmable logic device. The Programming Logic Device used here is
SPARTAN 3E.
1.2.4 A Quick example:
Many different designs of Adders, Subtractors, Encoders, Decoders and MUX were
performed in combinational circuits. A simple 4:1 MUX using dataflow modelling is being
shown here.
1.2.4.1 MUX: A multiplexer (MUX) is a device allowing one or more low-speed analog
or digital input signals to be selected, combined and transmitted at a higher speed on a single
shared medium or within a single shared device. Basically, a multiplexer (or mux) is a
device that selects one of several analog or digital input signals and forwards the selected
input into a single line. Following figure shows the general idea of a multiplexer with n input
signal, m control signals and one output signal.

2014
Figure 1.2:Design Multiplexer Pin Diagram
1.2.4.2 Boolean Expression: In digital circuit design, the selector wires are of
digital value. The number of selector pins is equal to where is the number of inputs.
For example, 9 to 16 inputs would require no fewer than 4 selector pins and 17 to 32 inputs
would require no fewer than 5 selector pins. The binary value expressed on these selector
pins determines the selected input pin.
A 2-to-1 multiplexer has a boolean equation where and are the two inputs, is the
selector input, and is the output:
1.2.4.3 Design Of a VHDL TESTBENCH FOr Simulation:
What is a Test Bench?
A Test Bench is a model that is used to exercise and verify the correctness of a hardware
model. VHDL language provides us with the capability of writing test bench models in the
same language.
What is its Purpose?
A Test Bench has three main purposes:
 To generate stimulus for simulation(waveforms)
 To apply the stimulus to the entity under test and collect the output responses
 To compare output responses with expected values
1.2.4.4 Example:
1.2.4.4.1 Design a 4:1 MUX using Dataflow style of Modelling:
Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

2014
entity LAB2_4isto1MUX_dataflow is
port(a,b,c,d,s0,s1:in std_logic;f:out std_logic);
end LAB2_4isto1MUX_dataflow;
architecture Behavioral of LAB2_4isto1MUX_dataflow is
signal x,y:std_logic;
begin
x<=not s0;
y<=not s1;
f<=(a and x and y)or(b and y and s0)or(c and x and s1)or(d and s0 and s1);
end Behavioral;
Rtl Schematic:
Figure 1.3 shows the RTL Schematic of 4:1 MUX(dataflow).
Figure 1.3:RTL Schematic

2014
Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LAB2_4isto1MUX_dataflow_testbench IS
END LAB2_4isto1MUX_dataflow_testbench;
ARCHITECTURE behavior OF LAB2_4isto1MUX_dataflow_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LAB2_4isto1MUX_dataflow
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
s0 : IN std_logic;
s1 : IN std_logic;
f : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';
signal d : std_logic := '0';
signal s0 : std_logic := '0';
signal s1 : std_logic := '0';
--Outputs
signal f : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LAB2_4isto1MUX_dataflow PORT MAP (
a => a,
b => b,
c => c,
d => d,
s0 => s0,
s1 => s1,
f => f
);
-- Stimulus process
stim_proc: process

2014
begin
-- hold reset state for 100 ns.
wait for 10 ns;
a <= '1'; b<='1';c<='0';d<='1';s0<='0';s1<='0';
wait for 10 ns;
a <= '1'; b<='0';c<='0';d<='0';s0<='0';s1<='0';
wait for 10 ns;
a <= '0'; b<='1';c<='1';d<='1';s0<='0';s1<='0';
wait for 10 ns;
a <= '0'; b<='0';c<='0';d<='0';s0<='0';s1<='0';
wait for 10 ns;
wait for 10 ns;
a <= '1'; b<='1';c<='0';d<='1';s0<='0';s1<='1';
wait for 10 ns;
a <= '1'; b<='0';c<='0';d<='0';s0<='0';s1<='1';
wait for 10 ns;
a <= '0'; b<='1';c<='1';d<='1';s0<='0';s1<='1';
wait for 10 ns;
a <= '0'; b<='0';c<='0';d<='0';s0<='0';s1<='1';
wait for 10 ns;
wait for 10 ns;
a <= '1'; b<='1';c<='0';d<='1';s0<='1';s1<='0';
wait for 10 ns;
a <= '1'; b<='0';c<='0';d<='0';s0<='1';s1<='0';
wait for 10 ns;
a <= '0'; b<='1';c<='1';d<='1';s0<='1';s1<='0';
wait for 10 ns;
a <= '0'; b<='0';c<='0';d<='0';s0<='1';s1<='0';
wait for 10 ns;
wait for 10 ns;
a <= '1'; b<='1';c<='0';d<='1';s0<='1';s1<='1';
wait for 10 ns;
a <= '1'; b<='0';c<='0';d<='0';s0<='1';s1<='1';
wait for 10 ns;
a <= '0'; b<='1';c<='1';d<='1';s0<='1';s1<='1';
wait for 10 ns;
a <= '0'; b<='0';c<='0';d<='0';s0<='1';s1<='1';
wait for 10 ns;
-- insert stimulus here
wait;
end process;
END;

2014
Simulation:
Figure 1.4 shows the Test Bench Simulation of 4:1 MUX(dataflow).
Figure 1.4:Test Bench Simulation
1.2.4.3.2 Design a 4:1 MUX using dataflow mixed style of modeling(use structural,
behavioral, dataflow).
Program:
library IEEE;
entity LAB2_mixedmodelling is
Port ( I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
Y : out STD_LOGIC);
end LAB2_mixedmodelling;
architecture Behavioral of LAB2_mixedmodelling is
component inva
port(l:in std_logic;m:out std_logic);
end component;
SIGNAL S0BAR,S1BAR:STD_LOGIC;
begin
IN1:INVA PORT MAP(S0,S0BAR);
IN2:INVA PORT MAP(S1,S1BAR);
process(I0,I1,I2,I3,S0,S1)
VARIABLE T0,T1,T2,T3:STD_LOGIC;
BEGIN
T0:=(S1BAR AND S0BAR AND I0 );
T1:=(S1BAR AND S0 AND I1 );
T2:=(S1 AND S0BAR AND I2 );
T3:=(S1 AND S0 AND I3 );
Y<=T0 OR T1 OR T2 OR T3;
END PROCESS ;
end Behavioral;

2014
INV Block:
library IEEE;
entity INVA is
Port ( l : in STD_LOGIC;
m : out STD_LOGIC);
end INVA;
architecture Behavioral of INVA is
begin
m <= not l;
end Behavioral;
1.2.4.4 Applications: An everyday example of an analog multiplexer is the source
selection control on a home stereo unit. Multiplexers are used in building digital
semiconductors such as CPUs and graphics controllers.
Another simple example of an non electronic circuit of a multiplexer is a single pole
multiposition switch.
Multiposition switches are widely used in many electronics circuits. However circuits that
operate at high speed require the multiplexer to be automatically selected.
Multiplexer handle two type of data that is analog and digital. For analog application,
multiplexer are built of relays and transistor switches. For digital application, they are built
from standard logic gates.
1.2.4.4 design summary:
Table 2 gives the design summary of 4:1 MUX Dataflow model and 4:1 MUX Mixed
Modelling.
Logic Utilization No. of Slices Used No. of Slices Available
4:1 MUX Dataflow Model:-
No of Slices LUTs 1 21000
No of fully used FF pairs 0 1
4:1 MUX Mixed Model:-
Table 1 Design Summary of MUX

VHDL-Adders
2014
1.3 Simulation & Comparison of Adder Architecture
1.3.1 Adder circuits: An adder or summer is a digital circuit that performs addition
of numbers. In many computers and other kinds of processors, adders are used not only in the
arithmetic logic unit, but also in other parts of the processor, where they are used to calculate
addresses, table indices, and similar operations.
The Figure 1.5 shows Schematic symbol for a 1-bit full adder with Cin and Cout drawn on
sides of block to emphasize their use in a multi-bit adder .
Figure 1.5:Symbolic representation of full adder
The different types of Adders are:
 Half Adder
 Full Adder
 Ripple Carry Adder
 Look Ahead Carry Adder
 Carry Save Adders
1.3.1.1 Ripple Carry Adder: Each full adder inputs is a Cin, which is the Cout of
the previous adder. This kind of adder is called a ripple-carry adder, since each carry bit
"ripples" to the next full adder. Note that the first (and only the first) full adder may be
replaced by a half adder.
1.3.1.2 Look Ahead Carry Adder: They create two signals (P and G) for each
bit position, based on whether a carry is propagated through from a less significant bit
position (at least one input is a '1'), generated in that bit position (both inputs are '1'), or killed
in that bit position (both inputs are '0'). In most cases, P is simply the sum output of a half-
adder and G is the carry output of the same adder. After P and G are generated the carries for
every bit position are created.
1.3.1.3 Carry Save Adder: If an adding circuit is to compute it can be
advantageous to not propagate the carry result. Instead, three input adders are used,
generating two results: a sum and a carry. The sum and the carry may be fed into two inputs
of the subsequent 3-number adder without having to wait for propagation of a carry signal.
After all stages of addition, however, a conventional adder (such as the ripple carry or the
lookahead) must be used to combine the final sum and carry results.

VHDL-Adders
2014
1.3.2 Example:
1.2.4.4.1 Design of a simple ALU:
What is an ALU?
ALU(Arithmetic Logic Unit) is a digital circuit which does arithmetic and logical
operations. Its a basic block in any processor.
Program:
library IEEE;
use IEEE.NUMERIC_STD.ALL;
entity LAB3_simple_ALU is
port( Clk : in std_logic; --clock signal
A,B : in signed(7 downto 0); --input operands
Op : in unsigned(2 downto 0); --Operation to be performed
R : out signed(7 downto 0) --output of ALU
);
end LAB3_simple_ALU;
architecture Behavioral of LAB3_simple_ALU is
signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0');
begin
Reg1 <= A; Reg2 <= B; R <= Reg3;
process(Clk)
begin
if(rising_edge(Clk)) then
case Op is
when "000" =>
Reg3 <= Reg1 + Reg2; --addition
when "001" =>
Reg3 <= Reg1 - Reg2; --subtraction
when "010" =>
Reg3 <= not Reg1; --NOT gate
when "011" =>
Reg3 <= Reg1 nand Reg2; --NAND gate
when "100" =>
Reg3 <= Reg1 nor Reg2; --NOR gate
when "101" =>
Reg3 <= Reg1 and Reg2; --AND gate
when "110" =>
Reg3 <= Reg1 or Reg2; --OR gate
when "111" =>
Reg3 <= Reg1 xor Reg2; --XOR gate
when others =>
NULL;
end case;
end if;
end process;
end Behavioral;

VHDL-Adders
2014
RTL Schematic:
Figure 1.6 shows the RTL representation of a simple Arithmetic Logic Unit(ALU).
Figure 1.6:RTL representation of a Simple ALU
1.3.2 Design summary:
Table 2 gives the design summary of Arithmetic Logic Unit(ALU).
4:1 MUX Dataflow Model:-
No of bonded IOBs 28 210
No of BUFG 1 32
Table 2 Design Summary of ALU

VHDL-Sequential Circuits
2014
1.4 Design of Sequential Circuits
1.4.1 Sequential circuits: Combinational circuits and systems produce an output
based on input variables only. Sequential circuits use current input variables and previous
input variables by storing the information and putting back into the circuit on the next clock
(activation) cycle. The Figure1.5 depicts combinational circuit added with memory element
is equivalent to Sequential Circuits.
Figure 1.5 Figure 1.6
1.4.2 Flip Flops : A flip-flop or latch is a circuit that has two stable states and can be used
to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to
change state by signals applied to one or more control inputs and will have one or two
outputs. Figure 2 depicts the traditional flip flop circuit based on BJTs. Figure 1.6 depicts a
general flip-flop using transistors.
1.4.3 Shift Registers : A shift register is a cascade of flip flops, sharing the same clock,
in which the output of each flip-flop is connected to the "data" input of the next flip-flop in
the chain, resulting in a circuit that shifts by one position the "bit array" stored in it.
A set of VHDL coding, TestBench generation, Simulation was done for all above ,but only
SIPO is presented.
1.4.4 A Quick Example:
1.4.4.1 Design of Serial-in parallel-out(SIPO) Registers:
Program:
library IEEE;
entity LAB4_DFF_SIPO is
port(clk,si: in std_logic;
po : inout std_logic_vector(7 downto 0));
end LAB4_DFF_SIPO;
architecture Behavioral of LAB4_DFF_SIPO is
begin
process(clk)
begin

VHDL-Sequential Circuits
2014
if (clk='1')then
po(7 downto 1) <= po(6 downto 0);
po(0) <= si;
end if;
end process;
end Behavioral;
Rtl Schematic:
Figure 1.7 shows the RTL Schematic of Serial In Parallel Out Shift Register.
Figure 1.7:RTL Schematic of SIPO
1.4.5. design summary:
Table 2 gives the design summary of Serial In Parallel Out Shift Register.
SIPO Model:-
Table 2 Design Summary of SIPO Register

VHDL-Counters & IP Cores
2014
1.5 Design of Counter and use of IP Cores
1.5.1 Counters: A counter is a device which stores (and sometimes displays) the number
of times a particular event or process has occurred, often in relationship to a clock signal.
1.5.2 A Quick Example:
1.5.2.1 Design of 4 bit up-down counters :
Program:
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity up4c is
port ( clk,rst,en : in std_logic;
count : out std_logic_vector(3 downto 0));
end up4c;
architecture Behavioral of up4c is
begin
process(clk,rst)
variable q : std_logic_vector(3 downto 0);
begin
if (rst='1') then
q:="0000";
elsif (clk' event and clk='1') then
if (en='1') then
q := q+1;
else
q := q-1;
end if;
end if;
count <= q;
end process;
end behavioral;

2014
Rtl Schematic:
Figure 1.7 shows the RTL Schematic of 4 Bit Up-Down Counter .
Figure 1.7:RTL Schematic of 4 bit Up-Down Counter
1.5.3. design summary:
4 BIT Up-Down Counter Model:-
1.5.4. WORKING WITH ip-cores:
1.5.4.1 What is a Core?
A Core is a readymade function that one can instantiate into one's design as a "Black Box".
1.5.4.2 What is IP Core?
Intellectual Property core(IP Core) are key building blocks of Xilinx Targeted Design
Platforms. Xilinx FPGA devices and tools are architected for easy creation of Plug-and-Play
IP; allowing Xilinx and its Alliance Program Members to provide an extensive catalog of
cores to address your general and market specific needs. This enables you to focus your
design efforts on where you differentiate your product from your competition and accelerate
your time to profit.

2014
1.5.4.3 To create Core Generator IP
1. Create IP as described in Creating a Source File, selecting IP as the source type.
2. After clicking Finish, an IP core customization tool appears in which one can define
one's IP.
3. After customize and generate the IP, the XCO file is added to the project and appears
in the Hierarchy pane of the Design panel.
1.5.4.4 Advantages of using IP Core
The advantages of using IP Cores are:
 Saves design time.
 Cores are created by expert designers having in-depth knowledge of
XILINX FPGA architecture.
 Guaranteed functionality saves time during simulation.
 Increases Design performance.
 Cores that contain mapping and placement information have
predictable performance that are constant over device size and
utilization.
 The data sheet for each core provides performance expectation.
Note In the New Source Wizard, CORE Generator IP and Architecture
Wizard IP are grouped together. CORE Generator IP is represented by the light
bulb icon .

VHDL-FPGA implementation
2014
1.6 FPGA Implementation of Counter
1.6.1Fpga Architecture(Spartan-3e):
The Spartan-3 platform was the industry’s first 90nm FPGA, delivering more functionality
and bandwidth per dollar than was previously possible, setting new standards in the
programmable logic industry. The Spartan-3E platform builds on the success of the earlier
Spartan-3 platform by adding new features that improve system performance and reduce the
cost of configuration. Because of their exceptionally low cost, Spartan-3 generation FPGAs
are ideally suited to a wide range of consumer electronics applications, including broadband
access, home networking, display/projection, and digital television equipment.
The SpartanTM-3E family of Field-Programmable Gate Arrays (FPGAs) is specifically
designed to meet the needs of high volume, cost-sensitive consumer electronic applications.
The five-member family offers densities ranging from 100,000 to 1.6 million system gates.
The Spartan-3E family has increased amount of logic per I/O, significantly reducing the cost
per logic cell. Because of their exceptionally low cost, Spartan-3E FPGAs are ideally suited
to a wide range of consumer electronics applications, including broadband access, home
networking, display/projection, and digital television equipment. The Spartan-3E family is a
superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also,
FPGA programmability permits design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs. - True LVDS, RSDS, mini-LVDS differential I/O
1.8V, 1.5V, and 1.2V signalling - Enhanced Double Data Rate (DDR) support Abundant,
flexible logic resources - Densities to 33,192 logic cells, including optional shift register or
distributed RAM support - Efficient wide multiplexers, wide logic - Fast look-ahead carry
logic - Enhanced x 18 multipliers with optional pipeline - IEEE 1149.1/1532 JTAG
programming/debug port Hierarchical Select RAMTM memory architecture to 648 Kbits of
fast block RAM to 231 Kbits of efficient distributed RAM Up to eight Digital Clock
Managers (DCMs) - Clock skew elimination (delay locked loop) - Frequency synthesis,
multiplication, division - High-resolution phase shifting - Wide frequency range (5 MHz to
over 300 MHz) Eight global clocks and eight clocks for each half of device, plus abundant
low-skew routing Configuration interface to industry-standard PROMs - Low-cost, space-
saving SPI serial Flash PROM or x8/x16 parallel NOR Flash PROM - Low-cost Xilinx
Platform Flash with JTAG Complete Xilinx ISETM, WebPACKTM development system
support MicroBlazeTM, PicoBlazeTM embedded processor cores Fully compliant 32-/64-bit
33/66 MHz PCI support Low-cost QFP and BGA packaging options - Common footprints
support easy density migration - Pb-free packaging options.

20142014
Figure 1.8:SPARTAN 3E Family architecture
Spartan-3E FPGAs are programmed by loading configuration data into robust,
reprogrammable, static CMOS configuration latches (CCLs) that collectively control all
functional elements and routing resources. The FPGA’s configuration data is stored
externally in a PROM or some other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the FPGA using any of seven different
modes:
• Master Serial from a Xilinx Platform Flash PROM
• Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash
• Byte Peripheral Interface (BPI) Up or Down from an industry-standard x8 or x8/x16
parallel NOR Flash
• Slave Serial, typically downloaded from a processor
• Slave Parallel, typically downloaded from a processor
• Boundary Scan (JTAG), typically downloaded from a processor or system tester.
Features
· Very low cost, high-performance logic solution for high-volume, consumer-oriented
applications Proven advanced 90-nanometer process technology Multi-voltage, multi-
standard Select IOTM interface pins to 376 I/O pins or 156 differential signal pairs -
LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards·
Equivalent Logic Cells CLB Array (One CLB = Four Slices) Rows Columns Total CLBs
Total Slices Distributed RAM 136K 231K Block RAM 504K 648K Maximum Differential
I/O Pairs.

20142014
These elements are organized as shown in Figure 1.8. A ring of IOBs surrounds a regular
array of CLBs. Each device has two columns of block RAM except for the XC3S100E,
which has one column. Each RAM column consists of several 18-Kbit RAM blocks. Each
block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The XC3S100E has only one DCM at
the top and bottom, while the XC3S1200E and XC3S1600E add two DCMs in the middle of
the left and right sides. The Spartan-3E family features a rich network of traces that
interconnect all five functional elements, transmitting signals among them. Each functional
element has an associated switch matrix that permits multiple connections to the routing.
1.6.2 Fpga Implementation(Spartan-3e):
Here listed are step to step procedure of FPGA implementation:
 Creating the UCF file by clicking on Implementation and Constraint in New Source
Wizard.
Sample Code for UCF file:
net "a" loc="113"; //a & b are inputs while l13 & l14 are the switches
net "b" loc="114";
net "sum" loc="f12";// sum & cy are inputs
net "cy" loc="e12";// while l13 & l14 are the o/p LEDs
 Then select run in "Implement Design", "Generate Programming File" and finally
"configure target file".
 A dialog box opens. On successful selection of the files in the box code would be
dumped in the SPARTAN-3E board.

20142014

VHDL-Traffic System
2014
2.1 Introduction:
We've all heard of traffic lights and chances are that most drivers hate them from the
bottom of their souls. They block you from reaching the destination faster, they make you
burn more gas and sometimes, they force you to wait for several minutes in a huge traffic jam
at a larger intersection.
But beyond these terrible scenarios, we must accept that traffic lights are playing a key role,
not only for the overall safety of traffic, but also for pedestrians who wish to cross a road
without putting their lives at risk.
Although in some regions authorities and various companies have started testing innovative
traffic light control systems, there are usually two different modes adopted by most nations
on the planet: fixed time and dynamic control. Let's take them one a time and see the
differences.
A fixed time traffic light control system is that boring and old-fashioned way in which traffic
lights are configured to turn on the green color after a given period of time, usually around 30
seconds, but this may very well vary depending on traffic values and region.
Dynamic traffic light control systems on the other hand are more appropriate for the crowded
traffic we're facing every morning, as they have been developed specifically to be able to
adapt their settings to traffic conditions. In case you're driving at a rush hour and you're
seeing green all the way from office to home, you're in luck: dynamic signals have turned all
traffic lights to green to maintain traffic flow.
As compared to fixed time control systems, the foundation of a dynamic system is actually a
detector, which is nothing more than a simple device that communicates with the traffic light
and informs it about traffic conditions in real time. This time, the traffic light can not only
adjust timing, but also solve traffic jams by turning red as soon as an intersection gets stuck
with cars.
That being said, it's pretty clear that traffic light systems are playing a vital role in the
automotive industry and although we all hate the red light, don't be so harsh on them. They're
here to make roads a better place.
2.2 Design Summary:
A traffic intersection is simulated on the FPGA, using a button press, KEY0, for a
pedestrian wanting to cross, a switch, SW0, to simulate a car waiting at the low priority
street. Unless there is a pedestrian or a car in the low priority street, the green light will be set
for the high priority street. Key1 is used to return the system to the initial default state, and 3
red and 3 green LEDs as well as three 7 segment displays are used to display the output of the
system.

VHDL-Traffic System
2014
2.3 Problem Description:
The traffic light control system will be implemented in a two street intersection that
allows pedestrians to cross on request. A cross-walk button, KEY 0, can be used to halt all
traffic to allow pedestrians to cross. Each traffic signal uses at two LED’s (green and red) per
traffic light or the pedestrian crossing point, one of the two streets has a priority over the
other. For the high priority street, the traffic signal will always remain green until the low
priority street car sensor has been tripped or a pedestrian has pressed a crosswalk button. The
occurrence of such an event gives the high priority street 5 seconds before the light changes
to red. Switch, SW0, to simulate a car sensor at the low priority street and a button KEY0 to
simulate the crosswalk request button for pedestrian use. Multiple button presses would be
treated as a single press until the pedestrian gets a WALK (green) signal. The duration of the
green light for the low priority street and the pedestrian crossing is 9 and 4 seconds,
respectively. The system utilizes a second button, KEY1, to reset the circuit, at which the
seven segment displays are set to their default values (5, 9, and 4) and the highest priority
street becomes a green light. At no time should there ever be more than one green light in the
system. Each traffic or pedestrian crossing light of this system will use seven segment
displays that will display the number of seconds left that the light will remain green. When
any of these seven segment displays reach zero they should reset to the default value (5, 9 and
4) and await the next countdown.
2.4 Design Problem Statement:
The Traffic Light system defaults to having the high priority street having the green
light unless the low priority street or the pedestrian are triggered. When this happens, the high
priority street HEX2 will count down to zero, and the pedestrian or the low priority street will
count down from 4 and 9 seconds, respectively. The state machine/FSM of the Traffic
Intersection System is given below in figure 2.1.

VHDL-Traffic System
2014
Figure 2.1:State Machine
2.5 Design:
2.5.1 Program:
The program has been divided into three subparts, namely:
 Edge_Detect-reads the clock & controls the enable,
 trafficControl-the main control unit of the traffic intersection system,
 DecodeHex-converting the Binary coded Decimal (BCD) output from trafficControl
to 7 Segment Display.
For the full code of the program refer to Appendix A.
2.5.2 Rtl Schematic:
Figure 2.2 give the RTL Schematic of Edge_Detect followed by figure 2.3 giving the RTL
Schematic of DecodeHex and finally figure 2.3 that gives the RTL Schematic of the entire
traffic intersection system.
Figure 2.2:RTL Schematic of Edge_detect

VHDL-Traffic System
2014
Figure 2.3:RTL Schematic of DecodeHex
Figure 2.4:RTL Schematic of Traffic Intersection System

VHDL-Traffic System
2014
2.5.3 Simulation:
The test bench has been created and the waveforms for different signals were observed and
verified accordingly as shown in figure 2.5.
Figure 2.5:TestBench Simulation of Traffic Intersection System
2.6 design summary:
Table 4 lists the number of slices, ffs, Input Output Blocks(IOBs),GCLKs in the design of the
traffic Intersection System.
Logic Utilization Used Available
Traffic Intersection Model:-
No of Slices 44 4656
No of Slices Flip Flops 30 9312
No of 4 input LUTs 82 9312
Number of GCLKs 2 24
Table 4:Design Summary of Traffic Intersection System

2014

VHDL Project- Car Alarm System
2014
3.1 Introduction:
The first documented case of car theft was in 1896, only a decade after gas-powered cars
were first introduced. From that early era to today, cars have been a natural target for thieves:
They are valuable, reasonably easy to resell and they have a built-in getaway system. Some
studies claim that a car gets broken into every 20 seconds in the United States alone.
Statistics show that a car is stolen every 10 seconds in the world!!!!
In light of this startling statistic, it's not surprising that millions of Americans have invested
in expensive alarm systems. Today, it seems like every other car is equipped with
sophisticated electronic sensors, blaring sirens and remote-activation systems. These cars are
high-security fortresses on wheels!
It's amazing how elaborate modern car alarms are, but it's even more remarkable that car
thieves still find a way to get past them.
So as my first summer internship project I decided to work on a car basic alarm system using
VHDL, dump it in SPARTAN 3E boards and observe the real time simulation using
ChipScope Pro.
3.2 Problem Statement/Model Description:
A Car alarm should have four inputs, called clk, rst, sensors and remote and one output,
called siren.
 For the FSM there should be atleast three states,
 disarmed,
 armed,
 and intrusion.
 If remote='1' occurs, the system must change form disarmed to armed or vice versa
depending on its current state.
 If armed, it must change to intrusion when sensors='1' happens, thus activating the
siren(siren='1').
 When in To disarm it, another remote='1' command is needed.
Figure 3.1 & 3.2 shows the Model & Schematic of a basic car alarm.
Figure 3.1:Model of a Basic Car Alarm

2014
Figure 3.2:Schematic of a Basic Car Alarm
3.3 Design:
The design of car alarm[5]
has taken place in three steps:
 Basic Alarm
 Alarm with Debounced Inputs
 Alarm with Debounced Inputs and ON/OFF chirps
3.3.1 Basic Alarm:
The drawn above would be designed in this case. The model designed below has a major flaw
which must be improved. The flaw being it does not require remote to go to '0' before being
valid again. Consequently when the system changes from disarmed to armed, it starts
flipping back and forth between these two states if a long remote='1' command is given(one
that lasts several clock cycles).this is a problem when turning the alarm off.
The machine can be fixed by introducing intermediate(temporary )states in which the system
waits until remote ='0' occurs.
Another solution (which we have used) would be to use some kind of flag that monitors the
signal remote to make sure that only after it returns to zero a new state transition is allowed to
occur.
A VHDL Code for the above option is shown below.
3.3.1.1 Program:
library IEEE;
entity prog is`
port(clk,rst,remote,sensors:in STD_LOGIC;

2014
siren:out STD_LOGIC );
end prog;
architecture fsm of prog is
Type alarm_state is(disarmed,armed,intrusion);
attribute enum_encoding:string;
attribute enum_encoding of alarm_state:type is "sequential";
signal pr_state,nx_state:alarm_state;
signal flag:std_logic;
begin
process(remote,rst)
begin
if(rst='1')then
flag<='0';
elsif(remote'event and remote='0')then
flag<=not flag;
end if;
end process;
process(clk,rst)
begin
if(rst='1')then
pr_state<=disarmed;
elsif(clk'event and clk='1')then
pr_state<=nx_state;
end if;
end process;
process(pr_state,flag,remote,sensors)
begin
case pr_state is
when disarmed =>
siren<='0';
if(remote='1' and flag='0')then
nx_state<=armed;
else
nx_state<=disarmed;
end if;
when armed =>
siren<='0';
if(sensors='1')then
nx_state<=intrusion;
elsif(remote='1' and flag='1')then
nx_state<=disarmed;
else
nx_state<=armed;
end if;
when intrusion =>
siren<='1';
if(remote='1' and flag='1')then
nx_state<=disarmed;
else
end if;
end case;
end process;
end fsm;

2014
3.3.1.2 Rtl Schematic:
Figure 3.3 shows the RTL Schematic of a basic car alarm.
Figure 3.3:RTL Schematic view of a Basic Car Alarm
3.3.1.3 Test Bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY basic_alarm IS
END basic_alarm;
ARCHITECTURE behavior OF basic_alarm IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT prog
PORT(
clk : IN std_logic;
rst : IN std_logic;
remote : IN std_logic;
sensors : IN std_logic;
siren : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal remote : std_logic := '0';
signal sensors : std_logic := '0';
--Outputs
signal siren : std_logic;

2014
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: prog PORT MAP (
clk => clk,
rst => rst,
remote => remote,
sensors => sensors,
siren => siren
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin rst<='1';
wait for 20 ns;
rst<='0';
remote<='0';sensors<='0';wait for 20 ns;
wait;
end process;
END;
3.3.1.4 Behavioral Model Simulation:
Figure 3.4 shows the Test Bench Simulation of a Basic Car Alarm having inputs clk, rst,
remote & sensors and siren as output.

2014
Figure 3.4:Test Bench Simulation of a Basic Car Alarm
3.3.1.4 ChipScope Pro Simulation:
Figure 3.6 shows the ChipScope Pro Simulation of a Basic Car Alarm having inputs clk,
rst, remote & sensors and siren as output. Rst is 0 in all the four cases while sensors
& remote is in the order of 00,01,10,11.While Figure 3.5 shows output when rst=1.
Figure 3.5:ChipScope Simulation of a Basic Car Alarm(rst=1)

2014
Figure 3.6:ChipScope Simulation of a Basic Car Alarm(rst=0)
3.3.2 Alarm with Debounced Inputs:
To protect the system against the noise, for any input signal transition to be considered as
valid the signal must remain in the new value for at least a certain amount of time(for
example, 5ms).In other words, the signals remote and sensors must be "debounced".
The debounced signals are called delayed_remote and delayed_sensors.The desired
debouncing time interval is entered using the GENERIC statement(the corresponding number
of clock cycles is also specified),so the code can be adjusted to any clock frequency.
Because debounce=3 was used, only inputs lasting three clock edges or longer are
considered(that is, transferred to delayed_remote and delayed_sensors).
The VHDL program for Debounced Inputs is shown below:

2014
3.3.2.1 Program:
library IEEE;
entity alarm_debounced is
generic(debounce:Integer:=3);
port(clk,rst,remote,sensors:in std_logic;
siren:out std_logic);
end alarm_debounced;
architecture Behavioral of alarm_debounced is
type alarm_state is(disarmed,armed,intrusion);
signal delayed_remote:std_logic;
signal delayed_sensors:std_logic;
signal flag:std_logic;
begin
process(clk,rst)
variable count:integer range 0 to debounce;
begin
if(rst='1') then
count:=0;
if(delayed_remote/=remote)then
count:=count+1;
if(count=debounce)then
count:=0;
delayed_remote<=remote;
end if;
else
count :=0;
end if;
end if;
end process;
process(clk,rst)
variable count:integer range 0 to debounce;
begin
if(rst='1')then
count:=0;
if(delayed_sensors/=sensors)then
count:=count+1;
if(count=debounce) then
count:=0;
delayed_sensors<=sensors;
end if;
else
count:=0;
end if;
end if;
end process;

2014
process(delayed_remote,rst)
begin
if(rst='1')then
flag<='0';
elsif(delayed_remote'event and delayed_remote='0')then
flag<=not flag;
end if;
end process;
process(clk,rst)
begin
if (rst='1')then
pr_state<=disarmed;
pr_state<=nx_state;
end if;
end process;
process(pr_state,flag,delayed_remote,delayed_sensors)
begin
case pr_state is
when disarmed=>
siren<='0';
if(delayed_remote='1' and flag='0')then
nx_state<=armed;
else
nx_state<=disarmed;
end if;
when armed=>
siren<='0';
if(delayed_sensors='1')then
elsif(delayed_remote='1' and flag='1')then
nx_state<=disarmed;
else
nx_state<=armed;
end if;
when intrusion =>
siren<='1';
nx_state<=disarmed;
else
end if;
end case;
end process;
end Behavioral;

2014
Figure 3.7 shows the RTL Schematic of a car alarm with debounced inputs.
Figure 3.7:RTL Schematic view of a Car Alarm
3.3.2.3 Behavioral Model Simulation:
Figure 3.8 shows the Test Bench Simulation of a Car alarm with debounced inputs.
Figure 3.8: Test Bench Simulation of a Car Alarm

2014
Figure 3.10:ChipScope Simulation of a Car Alarm(rst=1)
Figure 3.10:ChipScope Simulation of a Car Alarm(rst=0)
3.3.3 Alarm with Debounced Inputs and ON/OFF chirps:
Besides the basic circuit plus the debouncers, chirps are added to the system. When the alarm
is activated, the siren must emit one chirp(with duration chirpON~200ms), while during
deactivation it must produce two chirps(with separation chirpOFF~300ms).

2014
This FSM contains five additional states(chirp1 to chirp5) when compared to the original
FSM. Assuming that the is in the disarmed state, the occurence of remote='1' turns it
ON.However, before reaching the armed state, it must go through the chirp1 state, which
turns the siren ON and lasts chirpON clock cycles.
When in armed state,the occurence of sensors='1' moves the system to the intrusion state in
which the siren is turned ON and remains so until a command to disarm the
alarm(remote='1') is provided.
This is the most complete implementation.
The VHDL program for Debounced Inputs and ON/OFF chirps is shown below:
3.3.3.1 Program:
library IEEE;
entity onoffchirps is
generic(debounce:integer:=3;
chirpON:integer:=2;
chirpOFF:integer:=2;
max:integer:=2);
port(clk,rst,remote,sensors:in std_logic;
siren:out std_logic);
end onoffchirps;
architecture Behavioral of onoffchirps is
type alarm_state is(disarmed,armed,intrusion,chirp1,chirp2,chirp3,chirp4,chirp5);
signal delayed_remote:std_logic;
signal delayed_sensors:std_logic;
signal flag:std_logic:='0';
signal timer:integer range 0 to max;
begin
process(clk,rst)
variable count:integer range 0 to max;
begin
if(rst='1') then
count:=0;
if(delayed_remote/=remote)then
count:=count+1;
if(count=max)then
count:=0;
delayed_remote<=remote;
end if;
Note: The sequence of chirp states that the system must go through during the turn-off
procedure, some with the siren ON during chirpON clock cycles,others with it OFF during
chirpOFF clock periods.

2014
else
count :=0;
end if;
end if;
end process;
process(clk,rst)
variable count: integer range 0 to max;
begin
if(rst='1')then
count:=0;
if(delayed_sensors/=sensors)then
count:=count+1;
if(count=max) then
count:=0;
delayed_sensors<=sensors;
end if;
else
count:=0;
end if;
end if;
end process;
process(delayed_remote,rst)
begin
if(rst='1')then
flag<='0';
elsif(delayed_remote'event and delayed_remote='0')then
flag<=not flag;
end if;
end process;
process(clk,rst)
variable count:integer range 0 to max;
begin
if (rst='1')then
pr_state<=disarmed;
count:=count+1;
if(count=timer)then
pr_state<=nx_state;
count:=0;
end if;
end if;
end process;
process(pr_state,flag,delayed_remote,delayed_sensors)
begin
case pr_state is
when disarmed=>
siren<='0';
timer<=1;
nx_state<=chirp1;
else
nx_state<=disarmed;
end if;
when chirp1=>

2014
siren<='1';
timer<=chirpON;
nx_state<=armed;
when armed=>
siren<='0';
timer<=1;
if(delayed_sensors='1')then
elsif(delayed_remote='1' and flag='1')then
nx_state<=chirp3;
else
nx_state<=armed;
end if;
when intrusion =>
siren<='1';
timer<=1;
nx_state<=chirp2;
else
end if;
when chirp2=>
siren<='0';
timer<=chirpOFF;
nx_state<=chirp3;
when chirp3=>
siren<='1';
timer<=chirpON;
nx_state<=chirp4;
when chirp4=>
siren<='0';
timer<=chirpOFF;
nx_state<=chirp5;
when chirp5=>
siren<='1';
timer<=chirpON;
nx_state<=disarmed;
end case;
end process;
end Behavioral;

2014
Figure 3.8 shows the RTL Schematic of a final car alarm i.e. an basic car alarm with
debounced inputs and ON/OFF chirps.
Figure 3.11: RTL Scheamatic of a Final Car Alarm
3.3.3.3 Behavioral Model Stimualtion:
Figure 3.8 shows the test bench simulation of a final car alarm i.e. an basic car alarm
with debounced inputs and ON/OFF chirps.
Figure 3.12: Test Bench Simulation of a Final Car Alarm
Figure 3.13:ChipScope Simulation of Final Car Alarm(rst=1

2014
Figure 3.14:ChipScope Simulation of Final Car Alarm(rst=0)

2014
3.3.4 Design Summary:
Table 5 lists the number of slices, ffs, Input Output Blocks(IOBs),GCLKs in the design of the
Car Alarm System.
Logic Utilization Used Available
Basic Car Alarm Model:-
No of Slices 3 4656
Car Alarm Debounced I/Ps
Model:-
No of Slices 8 4656
Car Alarm Debounced I/Ps &
ON/OFF chirps Model:-
No of Slices 10 4656
Table 5:Design Summary of a Car alarm System

2014

Cadence-Introduction
2014
4.1 Introduction:-
Integrated circuit design is usually done by "paper and pencil" with very simple models in a
first stage. In the second stage the behavior of the circuit is verified by a simulation software
tool with more precise models and the circuit is then modified based on these results.
However, the results from the simulation software should more or less agree with the
considerations made in the first stage, when all components have been dimensioned.
Currently, the most sophisticated and wide-spread software package for the analysis and
synthesis of analog and digital integrated circuits is the Design Framework II(DFII) of
cadence Inc., which is popularly known as Cadence .
The Cadence tool kit consist of several programs for different applications such as schematic
drawing, layout, verification, and simulation. These applications can be used on various
computer platforms. The open architecture also allows for integration of tools from other
vendors or of own design. The integration of all this tools is done by a program called Design
Framework II (DFW). The DFW-application is the cornerstone in the Cadence environment.
It provides a common user interface and a common data base to the tools used. This makes it
possible to switch between different applications without having to convert the data base.
Figure 4.1 Design Process Flow Diagram
Cadence is a Electronic Design Automation(EDA) environment that allows integrating in a
single framework different applications and tools (both proprietary and from other vendors),
allowing to support all the stages of IC design and verification from a single environment.
These tools are completely general, supporting different fabrication technologies. When a
particular technology is selected, a set of configuration and technology-related files are
employed for customizing the Cadence environment. This set of files is commonly referred as
a design kit.

Cadence-Introduction
2014
Cadence Design Systems provides tools for different design styles. The Cadence suite is a
huge collection of programs for different CAD applications from VLSI design to high-level
DSP programming. The suite is divided into different "packages", and for VLSI design, the
packages I have been using are the IC package and the DSME package.
Cadence is a powerful tool that allows the user to design fully custom circuits and simulate
them. Programs very similar to Cadence, are extensively used in industry and research.
Cadence can be run only on unix terminals or PCs loaded with unix terminal emulators like
Exceed.
4.2 Cadence Environment:-
The Cadence custom integrated circuit design tool is a collection of tools ranging from
schematic capture, simulation, layout and physical verification. We would be using Cadence
IC 6.1.
The collection of tools and the configuration files in Cadence environment are illustrated in
Figure 4.2
Figure 4.2. Cadence environment overview
Virtuoso: The common product name for the schematic and layout entry tools.
CDB: The database where schematics and layouts is stored. The database is located within
the project directory. In Cadence version 6.1 CDB is replaced with a database called
OpenAccess.
Spectre: The analog simulator. It is an optimized version of Spice.
Assura: The physical verification tool provided by Cadence. Assura performs DRC (Design
Rule Check) and LVS (Layout Versus Schematic) of the layout, as well as parasitic
extraction.

Cadence-Design of Gates
2014
4.3 Design of Basic gates:-
4.3.1 Design of a Inverter(NOT gate) with W/L Ratio-100:240:
Inverter: The digital Logic NOT Gate is the most basic of all the logical gates and is
sometimes referred to as an Inverting Buffer or simply a Digital Inverter. It is a single
input device which has an output level that is normally at logic level “1” and goes “LOW” to
a logic level “0” when its single input is at logic level “1”, in other words it “inverts”
(complements) its input signal. The output from a NOT gate only returns “HIGH” again
when its input is at logic level “0” giving us the Boolean expression of: A = Q. The table
given below gives the symbol and truth table of XOR gate.
Symbol Truth Table
Inverter or NOT Gate
A Q
0 1
1 0
Boolean Expression Q = not A or A Read as inverse of A gives Q
Figure 4.3 NOT Gate circuit

2014
Figure 4.4 NOT gate plot
4.3.2 Design of a NAND gate with W/L Ratio-100:120:
Nand Gate : The Logic NAND Gate is a combination of the digital logic AND gate
with that of an inverter or NOT gate connected together in series. The NAND (Not – AND)
gate has an output that is normally at logic level “1” and only goes “LOW” to logic level “0”
when ALL of its inputs are at logic level “1”. The Logic NAND Gate is the reverse or
“Complementary” form of the AND gate we have seen previously. The table given below
gives the symbol and truth table of NAND gate.
Symbol Truth Table
2-input NAND Gate
B A Q
0 0 1
0 1 1
1 0 1
1 1 0
Boolean Expression Q = A.B Read as A AND B gives NOT Q

2014
Figure 4.5 NAND gate circuit
Figure 4.6 NAND gate plot

2014
4.3.3 Design of a OR gate with W/L Ratio-100:120:
Or Gate : A Logic OR Gate or Inclusive-OR gate is a type of digital logic gate that has
an output which is normally at logic level “0” and only goes “HIGH” to a logic level “1”
when one or more of its inputs are at logic level “1”. The output, Q of a “Logic OR Gate”
only returns “LOW” again when ALL of its inputs are at a logic level “0”. In other words for
a logic OR gate, any “HIGH” input will give a “HIGH”, logic level “1” output. The table
given below gives the symbol and truth table of OR gate.
Symbol Truth Table
2-input OR Gate
B A Q
0 0 0
0 1 1
1 0 1
1 1 1
Boolean Expression Q = A+B Read as A OR B gives Q
Figure 4.7 OR Gate circuit

2014
Figure 4.8 OR Gate plot
4.3.3 Design of a XOR gate with W/L Ratio-100:120:
XOR Gate : The XOR gate (sometimes EOR gate, or EXOR gate) is a digital logic
gate that implements an exclusive or; that is, a true output (1/HIGH) results if one, and only
one, of the inputs to the gate is true. If both inputs are false (0/LOW) or both are true, a false
output results. XOR represents the inequality function, i.e., the output is true if the inputs are
not alike otherwise the output is false. A way to remember XOR is "one or the other but not
both". The table given below gives the symbol and truth table of XOR gate.
Symbol Truth Table
2-input Ex-OR Gate
B A Q
0 0 0
0 1 1
1 0 1
1 1 0
Boolean Expression Q = A B A OR B but NOT BOTH gives Q

2014
Figure 4.9 XOR Gate circuit
Figure 4.10 XOR Gate plot

Cadence-Design of Combinational Circuits
2014
4.4 Design of Combinational Circuits:-
Combinational Circuits: Combinational circuit is circuit in which we combine the
different gates in the circuit for example encoder, decoder, multiplexer and demultiplexer.
Some of the characteristics of combinational circuits are following.
o The output of combinational circuit at any instant of time, depends only on the levels
present at input terminals.
o The combinational circuit do not use any memory. The previous state of input does
not have any effect on the present state of the circuit.
o A combinational circuit can have a n number of inputs and m number of outputs.
Modelling of different Combinational circuits such as adders, subtractors, MUX, Encoders
were done but only a few examples are being shown here.
4.4.1 Design of a Full Adder with W/L Ratio-100:240:
full adder(ckt):
Figure 4.11 Full Adder Circuit

2014
Figure 4.12 Full Adder plot
4.4.2 Design of a 2:1 MUX with W/L Ratio-100:240:
2x1 mux(ckt):
Figure 4.13 2X1 MUX circuit

2014
Figure 4.14 2X1 MUX plot

Cadence- Cadence Virtuoso Layout Suite
2014
4.5Cadence Virtuoso Layout Suite:-
Cadence Virtuoso Layout Suite supports custom digital, mixed-signal and analog designs at
the device, cell, and block levels. Its advanced features include automation to accelerate
custom block authoring, as well as industry-leading Cadence space-based routing technology
that automatically enforces 65/45nm process and design rules during interactive and
automatic routing. Working in concert with other components of the Virtuoso platform,
Virtuoso Layout Suite enables the creation of differentiated custom silicon that is both fast
and silicon-accurate.
4.5 Virtuoso Layout Editing(DRC,LVS):
The objective was to become familiar with Virtuoso layout Editor,the design rule checking(DRC),and
layout versus Schematic(LVS) verification process. The application was running without any
error.
Figure 4.15 PMOS Layer Figure 4.15 NMOS Layer
Figure 4.16 Inverter Circuit

Conclusion
2014
-:Conclusion:-
The improvement of the country's traffic system condition is largely dependent on the
modern ways of traffic management and control. Advanced traffic signal controllers and
control systems contribute to the improvement of the urban traffic problem. The intelligence
of the traffic signal controller is introduced in this project with powerful functions and
hardware interface. Good quality social benefit has been made through the application of the
intelligent traffic controller in practice, and the application results show that that the
intelligent traffic controller will improve.
With the exponential rise in the number of cars in India and the car locking system
making a transition from the normal locking system to the electronic locking system, my
effort was to design a car locking system that would address the problem in a easier manner.
Before designing the circuit and program it is important to identify the problem of the
system. First, a block diagram or structure for both the traffic controller system & car alarm
system must be designed. Referring an block diagram(both in traffic intersection system and
car alarm system), we know the inputs, outputs, types and the number of states are used in
this project. Using states machine, it is easy to design and it give the designer nice flexibility
when the designer needs to pathetic the design either for speed or area optimization.
In software implementations, it should be clear and the solution are understandable.
Design a traffic light using the state machine is very difficult compared to design using the
logic gates. VHDL text editor was chosen to write the program code for simulation only to
get a timing diagram. This is because it is easy to write and understand compare to other
languages. Simulation using gate logic is very difficult when there is a feedback output that
is, when the output becomes the input state.
This project has two main phases. The first stage is to design a program, which
consists of reading, research, planning and designing a program. The simulation is needed to
get a waveform and the output of this simulation must be a same value or data with the
waveform.
As a conclusion, the controller can control the traffic movement and detect a busy and
non busy road. The overall of this project is OK but the environment and equipments when
taken into account can affect the output.

References
2014
-:References:-
This project would have been nightmarish had would not have been possible without the
substantial help received from these sources.
 A VHDL Primer by J. Bhasakar.
 IEEE standard VHDL Language reference Manual.
 Cadence Analog design Enviorment User Guide.
 HKU EEE VLSI Lab Fully custom design flow
tutorials(http://www.eee.hku.hk/~culei/806_design_flow/Design%20Flow.htm)
 Traffic Light System by Jeneffier Estrada

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