Please write out VHDL code by hand... Thank you... Solution library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comapre32bit is Port ( A,B : in STD_LOGIC_VECTOR (31 downto 0); EQU,GR,LT : out STD_LOGIC); end comapre32bit; architecture Behavioral of comapre32bit is begin Process(A,B) begin If (A>B) then GR <=1; elsif(A=B) then EQU <=1; else LT <=1; end if; end process; end Behavioral;.

1. Please write out VHDL code by hand...
Thank you...
Solution
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comapre32bit is
Port ( A,B : in STD_LOGIC_VECTOR (31 downto 0);
EQU,GR,LT : out STD_LOGIC);
end comapre32bit;
architecture Behavioral of comapre32bit is
begin
Process(A,B)
begin
If (A>B) then
GR <=1;
elsif(A=B) then
EQU <=1;
else
LT <=1;
end if;
end process;
end Behavioral;