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By: Zakriua Gomma
Email: zakriua.gomma37@gmail.com
Introduction to ARM Architecture
ARM Ltd
 ARM
 Advanced RISC Machines
 Founded in November 1990
 Spun out of Acorn Computers
 Company headquarters in ...
ARM Offices Worldwide




 
In 2005 about 98 percent of all mobile phones use at
least one ARM-designed core on their motherboards,
accord...




• Motorola
• Panasonic
• Qualcomm
• Sharp
• Sanyo
• Sony
• Apple
• Toshiba
• Texas Instrument
• Wipro
…and many more
• 3co...





•


•
•
• Later Intel bought Strong
ARM From DEC & Changed
the name to Xscale .
• In 2006 Marvell Technology
Group bought Xsca...
Embedded ARM Cortex
Processors
• Cortex M0:
 Ultra low gate
count (less that 12
K). gates).
 Ultra low-power (3
μW/MHz )...
Embedded ARM Cortex
Processors
• Cortex M1:
 The first ARM
processor designed
specifically for
implementation in
FPGAs.
...
Embedded ARM Cortex
Processors• Cortex M3:
 The mainstream ARM
processor for
microcontroller
applications.
 High perform...
Embedded ARM Cortex
Processors• Cortex M4:
 Embedded processor for DSP.
 FPU (Floating Point Unit).
 Based on ARMv7E-M ...
Cortex M7
Architecture Diagram
Registers
 ARM has a load store (RISC) architecture.
 General purpose registers can hold data or
address.
 In Arm corte...
Registers
Registers
 All 13 general-purpose registers can be used to
store instruction ,data & addresses .
 These registers divide...
Registers
R13 is a Stack Pointer
Register (SPR) used to
store the current stack
address.
 In Cortex-M4 core, there are t...
Registers
 R14 is a Link Register (LR) : provides some
linking functions to set up a connection
between the main program ...
Registers
 (XPSR) The Program Status Register : can be
divided into three different status registers to
show the running ...
Registers
Registers
Registers
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r15 (pc)
cpsr
r13 (sp)
r14 (lr)
User mode
spsr
r13 (sp)
r14 (lr)
IRQ F...
Processor Modes
 ARM has seven basic operating modes
 Each mode has access to its own stack space and a different subset...
AMBA
 The Advanced Microcontroller Bus
Architecture
 Three distinct buses are defined within
the AMBA specification:
 t...
AMBA
High Performance
ARM processor
High-bandwidth
on-chip RAM
High
Bandwidth
External
Memory
Interface
DMA
Bus Master
APB...
AMBA
AMBA
Enable In Out
0 0 High impedance
0 1 High impedance
1 0 0
1 1 1
Memory
8 Bit Width=1
Byte
• Arm cortex-M4 has 32-bit Address
bus ,that allow to Access 4 Gb
location in memory.
• The bus ...
Memory
• The Cortex-M4 processors can work with either little endian or
big endian memory systems. Generally, the Cortex-M...
Stack Memory
• Stack is a kind of memory usage mechanism that allows a
portion of memory to be used as Last-In-First-Out d...
Stack Memory
Pipeline
• Cortex-M4 has 3-stage fetch-decode-execute pipeline
Introduction to arm architecture
Introduction to arm architecture
Introduction to arm architecture
Introduction to arm architecture
Introduction to arm architecture
Introduction to arm architecture
Introduction to arm architecture
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Introduction to arm architecture

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this presentation provides a very good information about ARM Company and ARM Architecture
Written By Eng: Zakriua Gomma

Veröffentlicht in: Ingenieurwesen

Introduction to arm architecture

  1. 1. By: Zakriua Gomma Email: zakriua.gomma37@gmail.com Introduction to ARM Architecture
  2. 2. ARM Ltd  ARM  Advanced RISC Machines  Founded in November 1990  Spun out of Acorn Computers  Company headquarters in Cambridge, UK  Processor design centres in Cambridge, Austin, and Sophia Antipolis  Sales, support, and engineering offices all over the world  Best known for its range of RISC processor cores designs  Other products – fabric IP, software tools, models, cell libraries - to help partners develop and ship ARM-based SoCs  ARM does not manufacture silicon
  3. 3. ARM Offices Worldwide
  4. 4.       In 2005 about 98 percent of all mobile phones use at least one ARM-designed core on their motherboards, according to research from the analyst firm the Linley Group
  5. 5.    
  6. 6. • Motorola • Panasonic • Qualcomm • Sharp • Sanyo • Sony • Apple • Toshiba • Texas Instrument • Wipro …and many more • 3com • Microsoft • IBM • Intel • Nokia • Atmel • NEC • Fijistu • Freescale • Altera • Epson • STM • NXP
  7. 7.  
  8. 8.   
  9. 9. •  
  10. 10. • • • Later Intel bought Strong ARM From DEC & Changed the name to Xscale . • In 2006 Marvell Technology Group bought Xscale from Intel .
  11. 11. Embedded ARM Cortex Processors • Cortex M0:  Ultra low gate count (less that 12 K). gates).  Ultra low-power (3 μW/MHz ).  32-bit processor.  Based on ARMv6- M architecture.
  12. 12. Embedded ARM Cortex Processors • Cortex M1:  The first ARM processor designed specifically for implementation in FPGAs.  Supports all major FPGA vendors.  Easy migration path from FPGA to ASIC.  Based on ARMv6-M architecture.
  13. 13. Embedded ARM Cortex Processors• Cortex M3:  The mainstream ARM processor for microcontroller applications.  High performance and energy efficiency.  Easy migration path from FPGA to ASIC.  Advanced3-Stage Pipeline.  Based on ARMv7-M architecture.
  14. 14. Embedded ARM Cortex Processors• Cortex M4:  Embedded processor for DSP.  FPU (Floating Point Unit).  Based on ARMv7E-M architecture.
  15. 15. Cortex M7
  16. 16. Architecture Diagram
  17. 17. Registers  ARM has a load store (RISC) architecture.  General purpose registers can hold data or address.  In Arm cortex-M4 there are 21 Registers Visible each 32bit wide:  Sixteen registers located in the register bank.  Five special registers located outside of the register bank.
  18. 18. Registers
  19. 19. Registers  All 13 general-purpose registers can be used to store instruction ,data & addresses .  These registers divided into :  Low Register from R0 to R7.  High Register from R8 to R12.  Most 16-bit data operations should be performed in the Low Register group.  Most 32-bit data operations should be processed in the High Register group.
  20. 20. Registers R13 is a Stack Pointer Register (SPR) used to store the current stack address.  In Cortex-M4 core, there are two kinds of stack pointers:  the Main Stack Pointer (MSP) : is used for the system program working in the Handler Mode .  Process Stack Pointer (PSP) : is used for the user’s program working in the Thread Mode.  Only one stack pointer is active at a time. The default Stack Pointer is the MSP after the system is reset.
  21. 21. Registers  R14 is a Link Register (LR) : provides some linking functions to set up a connection between the main program and the calling functions or subroutines.  When a function or subroutine is called, the returning address should be entered into the R14.  After the function or subroutine is done, the content of the Link Register R14, which is the returning address to the main program, is fed into the Program Counter (PC) to enable the processor to continue the work from the address stored in the PC.  R15 is the Program Counter :points to the address of the next instruction to be executed .
  22. 22. Registers  (XPSR) The Program Status Register : can be divided into three different status registers to show the running status of different units:  Application Program Status Register (APSR)  Execution Program Status Register (EPSR)  Interrupt Program Status Register (IPSR)
  23. 23. Registers
  24. 24. Registers
  25. 25. Registers r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) User mode spsr r13 (sp) r14 (lr) IRQ FIQ r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr spsr r13 (sp) r14 (lr) Undef spsr r13 (sp) r14 (lr) Abort spsr r13 (sp) r14 (lr) SVC
  26. 26. Processor Modes  ARM has seven basic operating modes  Each mode has access to its own stack space and a different subset of registers  Some operations can only be carried out in a privileged mode Mode Description Supervisor (SVC) Entered on reset and when a Supervisor call instruction (SVC) is executed Privileged modes FIQ Entered when a high priority (fast) interrupt is raised IRQ Entered when a normal priority interrupt is raised Abort Used to handle memory access violations Undef Used to handle undefined instructions System Privileged mode using the same registers as User mode User Mode under which most Applications / OS tasks run Unprivileged mode Exceptionmodes
  27. 27. AMBA  The Advanced Microcontroller Bus Architecture  Three distinct buses are defined within the AMBA specification:  the Advanced High-performance Bus (AHB)  the Advanced System Bus (ASB)  the Advanced Peripheral Bus (APB).
  28. 28. AMBA High Performance ARM processor High-bandwidth on-chip RAM High Bandwidth External Memory Interface DMA Bus Master APB Bridge Timer Keypad UART PIO AHB or ASB APB AHB  High performance  Pipelined operation  Burst Transfers  Multiple Bus Masters APB  Low power  Latched address/control  Simple interface  Suitable of many peripherals ASB  High performance  Pipelined operation
  29. 29. AMBA
  30. 30. AMBA Enable In Out 0 0 High impedance 0 1 High impedance 1 0 0 1 1 1
  31. 31. Memory 8 Bit Width=1 Byte • Arm cortex-M4 has 32-bit Address bus ,that allow to Access 4 Gb location in memory. • The bus interface between the MCU and external memory is the (AHB), which provides interfaces and connections to various 32/16/8-bit memory devices. • The following buses can be used to access memory or peripheral devices in parallel :  I-Code Bus: Fetch Opcode from the flash ROM.  D-Code Bus: Read constant data from flash ROM.  System Bus: Read/Write data from SRAM or I/O, fetch opcode from
  32. 32. Memory • The Cortex-M4 processors can work with either little endian or big endian memory systems. Generally, the Cortex-M4 is designed with just one endian configuration.
  33. 33. Stack Memory • Stack is a kind of memory usage mechanism that allows a portion of memory to be used as Last-In-First-Out data storage buffer. • PUSH to store data in stack . • POP to retrieve data from stack
  34. 34. Stack Memory
  35. 35. Pipeline • Cortex-M4 has 3-stage fetch-decode-execute pipeline

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