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1. CS3351-DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION
Two Marks Questions & Answers
UNIT-1
What are the limitations of Karnaugh map? [N/D ─17]
The limitations of Karnaugh map are:
i. It is limited to six variable map (i.e) more then six variable involvingexpression are
not reduced.
ii. The map method is restricted in its capability, since; they are useful forsimplifying
only Boolean expression represented in standard form.
Why NAND and NOR gates are called universal gates? [A/M ─18]
The NAND and NOR gates are called universal gates because; these gates are used toperform any
type of logic applications.
Define – Don’t Care Conditions
In some logic circuits, certain input conditions never occur; therefore, the corresponding output
never appears. In such cases, the output level is not defined, it can be either HIGHor LOW. These
output levels are indicated by ‘X’ or ‘d’ in the truth tables and are called don’t care outputs or
don’t care conditions or incompletely specified functions.
Discuss NOR operation with a truth table. [ N / D – 15 ]
In NOR operation, the output is high only when all the inputs are low. If any one orboth the
inputs are high, then the output is low. The truth table is as below
Input Output
A B Y = (
̅̅𝐴
̅̅̅+
̅̅𝐵
̅̅̅)
0 0 1
0 1 0
1 0 0
1 1 0
Define − Combinational circuits. [ M/ J – 16 ]
When logic gates are connected together to produce a specified output for certain specified
combinations of input variables with no storage is involved, the resulting circuit is called
combinational circuit.
What is primary encoder? [ N/D – 16 ]
A primary encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having priority will take
precedence.
What is priority encoder? [ A/ M – 17 ]
A priority encoder is an encoder circuit that includes the priority function. . In priorityencoder, if
2 or more inputs are equal to 1 at the same time, the input having prioritywill take precedence.

2. What are binary decoders? [ N/D – 17 ]
A decoder is a multiple input multiple output combinational circuit that convertsbinary
information from n input lines to a maximum of 2n
output lines.
State the modeling techniques used in HDL. [ A/M - 18 ]
The modeling techniques used in HDL are:
 Gate-level modeling
 Data-flow modeling
 Switch-level modeling
 Behavioral level modeling
Define − Combinational circuits. [ A/M– 08 ]
When logic gates are connected together to produce a specified output for certain specified
combinations of input variables with no storage is involved, the resulting circuit is called
combinational circuit.
A combinational circuit consists of input variables, logic gates and output variables. For
example, consider following Boolean expression,
Y = AB + BC + AC.
The combinational circuit for this would require 3 AND gates and 1 OR gate.
Define – Half adder and full Adder.
Half adder: The logic circuit which performs the arithmetic sum of two bits is called ahalf
adder.
Full adder: The logic circuit which performs the arithmetic sum of 3 bits ( bit1 : input1, bit2:
input2, bit3: carry from previous addition) is called a full adder.
Define – Half subtractor and full subtractor.
Half Subtractor: It is a combinational circuit that subtracts two bits and produces thatdifference
and borrow.
Full subtractor: The logic circuit which performs subtraction between 2 bits. It alsotakes
into account borrow of the lower significant stage.
What is meant by carry propagation delay?
In parallel adders, sum and carry outputs of any stage cannot be produced until the input
carry occurs. This time delay in the addition process is called carry propagation delay. This
delay increases with increase in the number of bits to be added in an addercircuit.
Suggest a solution to overcome the limitation on the speed of an adder. [ N/D – 09]
It is possible to increase speed of adder by eliminating inter-stage carry delay. This method
utilizes logic gates to look at the lower-order bits of the augend and addend tosee if a higher-
order carry is to be generated.
What is the difference between half adder and full adder? [ N/D – 07]
Half Adder Full Adder
Half adder takes two binary-inputs i.e.
augend and addend bits and gives out two
binary outputs as sum and carry.
Full-adder, along with augend and addend
takes third additional bit Cin as input. Cin
represents the carry from the previous lower
significant position.
Half-adder is not used in practice. Full-adder is used in practice.

3. What is meant by decoder?
A decoder is a multiple-input, multiple-output logic circuit which converts coded inputs into
coded outputs, where the input and output codes are different. In a binary decoder n-inputs
produce 2n
outputs. Usually, a decoder is provided with enable inputs to activate decoded
output.
What is meant by encoder? [M/J – 10]
An encoder is a digital circuit that performs the inverse operation of a decoder. Encoder has
2n
(or fewer) input and n output lines. Encoder has enable inputs to actuate encoded outputs.
What is meant by comparator? Or write a short note on 1-bit comparator.
Comparator is a special combinational circuit designed primarily to compare the relative
magnitudes of the two binary numbers. An n-bit comparator receives two n- bit numbers A
and B, outputs are A>B, A = B and A< B as per the magnitudes of the numbers, one of the
outputs will be high.
What will be the maximum number of outputs for a decoder with a 6 bit data word? [M/J – 09]
The maximum number of outputs for a decoder with a 6 bit data word is 26 = 64.
What is a data selector? Or what is multiplexer? Or Why MUX is called as dataselector?N/D –
06, M/J – 11]
 Multiplexer is a digital switch, particularly it has 2n input lines and n selectionlines
whose bit combinations determine which input line is selected and routed onto
available only single output line.
 Hence, multiplexer is a selector of one out of several data sources available at its
input lines, to connect it to output line. Simply it is a many to one device and also
called data selector.
Unit II
Synchronous Sequential Circuits
What is a ring counter? [A/M− 15]
A ring counter is one, in which a single ‘1’ is made to circulate around theregister. An
‘n’ bit ring counter has ‘n’ states.
Write short notes on propagation delay. [N/D− 15]
Propagation delay symbolized tpd is the time required for a digital signal to travel fromthe
input of the logic gate to the output. It is measured in microseconds, nanoseconds or
picoseconds.
Discuss the working of T flip-flop. [N/D − 15]
T flip-flop is also known as Toggle flip-flop.
• When T=0 there is no change in the output.
• When T=1 the output switch to the complement state (ie) the output toggles.
State the excitation table of JK flip flop. [ M/J − 16]
Present state
Qn
Next state
Qn+1
Input
J K

4. 0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
What is the operation of JK flip-flop? [N/D − 16]
The operation of JK flip-flop is as follows
When K input is low and J input is high the Q output of flip-flop is set.
• When K input is high and J input is low the Q output of flip-flop is reset.
• When both the inputs K and J are low the output does not change
• When both the inputs K and J are high it is possible to set or reset the flip-flop (ie)the
output toggle on the next positive clock edge.
What are the significances of state assignment? [M/J − 17]
Static assignment is assigning binary values to states that will create a reduced logic
equation.
Write any two applications of shift register. [M/J − 17]
The applications of shift register are as follows:
 Serial to parallel converter
 Parallel to serial converter
 As a counter
 To introduce delay in a digital circuit
How does synchronous circuit differ from asynchronous circuit? [ N/D – 17]
Asynchronous circuits Synchronous circuits
The output of the first flip-flop drives
simultaneously.
All the flip-flops are clocked the clock
for next flip-flop.
They are slow, because the clock is
propagated through number of flip-flops
before it reaches last flip flop.
As clock is simultaneously given to all
flip-flops there is no problem of
propagation delay.
Logic circuit is very simple even for more
number of states.
Design involves complex logic circuit as
number of states increases.
What is the drawback of SR flip-flop? How it is avoided in JK flip-flop? [A/M –18]
In SR flip-flop, when both inputs are 1, the output Q and Q’ will be equal. So this is
indeterminate state. In JK flip-flop, another feedback is given from output in input side, so
the output will be complement of the previous state, if the inputs are ‘1’.
List out the different types of shift registers. [A/M – 18]
The different types of shift registers are:
 Serial In Serial Out (SISO) shift register
 Serial In Parallel Out (SIPO) shift register
 Parallel In Serial Out shift register
 Parallel In Parallel Out shift register.
What are synchronous sequential circuits?
Synchronous sequential circuits are those in which signal can affect the memory element
only at discrete instants of time. Clocked flip-flops are examples of synchronous sequential
circuits.

5. Define – Sequential Logic Circuit. Write an example. [May/June – 08]
The circuits in which the output variables depend not only on the present input but they also
depend upon the past outputs, which are known as sequential logic circuits. Flip-flops,
counters and registers are the examples of sequential logic circuit.
Draw the logic diagram of SR flip-flop.
What are the classifications of sequential circuits?
The sequential circuits are classified on the basis of timing of their signals into two types.They are,
 Synchronous sequential circuit.
 Asynchronous sequential circuit.
Define Flip flop.
Flip flop is defined as a digital circuit which maintains its output state either at 1 or 0until
directed by an input signal to change its state.
(Or)
Flip - flop is a sequential device that normally samples its inputs and changes itsoutputs only
at times determined by clocking signal.
Give the comparison between combinational circuits and sequential circuits.
Combinational circuits Sequential circuits
Memory unit is not required. Memory unit is required.
Parallel adder is a combinational circuit. Serial adder is a sequential circuit.
What is meant by present state?
The information stored in the memory elements at any given time defines the presentstate of
the sequential circuit.
What is meant by next state?
The present state and the external inputs determine the outputs and the next state ofthe
sequential circuit.
What are shift registers?
The binary information in a register can be moved from stage to stage within the register or
into or out of the register upon application of clock pulses. This type of bit movement or
shifting is essential for certain arithmetic and logic operations used in microprocessors. This
gives rise to group of registers called shift registers.
What is a master-slave flip-flop?
A master-slave flip-flop consists of two flip-flops where one circuit serves as a masterand the
other as a slave.
What are the different types of flip-flop?
There are various types of flip flops. Some of them are mentioned below:

6. RS flip-flop
SR flip-flop
D flip-flop
JK flip-flop
T flip-flop
What is the operation of SR flip-flop?
 When R input is low and S input is high the Q output of flip-flop is Set.
 When R input is high and S input is low the Q output of flip-flop is Reset.
 When both the inputs R and S are low the output does not change.
 When both the inputs R and S are high the output is unpredictable.
What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and ifD=0, the
output is reset.
What is synchronous sequential circuit?
In synchronous sequential circuits, signals can affect the memory elements only atdiscrete
instant of time.
What is asynchronous sequential circuit?
In asynchronous sequential circuits change in input signals can affect memoryelement at
any instant of time.
What is synchronous counter? [Dec/Jan– 06]
When counter is clocked such that each flip-flop in the counter is triggered at the same time,
the counter is called synchronous counter.
What is a self-starting counter? [May/June – 10]
In a counter, if the next state of some unused state is again an unused state and if by chance,
the counter happens to find itself in the unused states and never arrived at a used state, then
the counter is said to be in the lockout conditions. The counter which never goes in lockout
condition is called self-starting counter.
What is the difference between serial transfer and parallel transfer? What is the
type of register used in each case?
When data is transferred one bit at a time, the process of transfer is known as serial transfer.
When multiple bits are transferred at a time, the process is known as parallel. For parallel
transfer, we can use parallel in and parallel out register. For serial transferwe can use left shift
or right shift register.
Compare asynchronous and synchronous sequential circuit. [A/M− 15]
Sl.No Synchronous sequential circuit Asynchronous sequential circuit
1 Memory elements are clocked flip-
flops.
Memory elements are either un-
clocked flip-flops or time delay
elements.
2 The change in input signals can
affect memory element upon
activation of clock signal.
The change in input signals can affect
memory element at any instant of time.
3 It is slower. It is faster.
4 It is easier to design. It is more difficult to design.

7. What is edge triggered flip-flop? [ A/M – 17] [ N/D – 17]
If the flip-flop changes its state when the clock is positive( High) or negative(Low) then, that
flip-flop is said to be level triggering flip-flop.
If the flip-flop changes its state either at the positive edge (rising edge) or negative edge (
falling edge) of the clock and is sensitive to its inputs only at this transition of the clock then
that flip-flop is said to be edge triggered flip-flop.
Define − Race Around Condition [N/D − 16] , [ A/M – 17]
In JK flip- flop, if both J and K are high and when clock is also 1, then the output toggles
continuously between set and reset state. This condition is known as race around condition.
List the various memory elements used in sequential machines.
The various memory elements used in sequential machines are D flip-flop, T flip-flop, SRflip-
flop, and J-K flip-flop.
What do you mean by the term ‘state table’? What does each row, column and entry
of the state table represent?
The state table is a tabular representation of the relationship between the present state, theinput,
the next state and the output. Each column of the state table corresponds to one input symbol, and
each row of the state table corresponds to one state. The entries corresponding to each
combination of the input symbols and the present state specify the output that will be generated
and the next state to which the machine will go.
Compare the state diagram and the state table.
Both the state diagram and the state table contain the same information and the choice
between the two representations is a matter of convenience. Both have the advantage of being
precise, unambiguous, and thus more suitable for describing theoperation of a sequential machine
than that by any verbal description. The succession of states through which a sequential machine
passes and the output sequence which it produces in response to a known input sequence are
specified uniquely by the state diagram or by the state model and the initial state.
What is an excitation table? What information does it give?
An excitation table is a table which lists the present states, the excitations and the next states. It
gives information about the excitations or inputs required to be applied to the memory elements
in the sequential circuit to bring the sequential machine from the present state to the next state.
It also gives information about the outputs of the machine after application of the present inputs.
What is the Mealy model of the state diagram of a memory element?
In the Mealy model of the state diagram each node in the state diagram represents a particular
state of the FF (0 or 1). The labels on the arcs indicate the input/output, i.e. the input that is given
when the FF is in a particular state and the corresponding output. The directions of the arrows
point to the next state the FF will go after the input is applied.
By how many models are synchronous sequential circuits represented? Name them.
Synchronous or clocked sequential circuits are represented by two models.
 They are:
o Moore circuit (or model)
o Mealy circuit (or model)
What is a Mealy machine?
o The Mealy machine (circuit or model) is a sequential circuit in which the output
depends onboth the present state of the flip-flops and on the inputs

8. What is a Moore machine?
The Mealy machine (circuit or model) is a sequential circuit in which the output depends only on the present
state of the flip-flops.
UNIT III
1.Classify the instructions based on the observations they perform and give one example to
each
category
2. What are the components of a computer system?
Input, Output, Memory, Datapath and control
3. How to represent Instruction in a computer system?
Instructions are represented in a computer using three formats
R Type for Register (or) R Format
I Type for Immediate (or) I Format
J Type for Jump (or) J Format

9. 4. Distinguish between auto increment and auto decrement addressing mode.
Auto Increment mode Auto Decrement mode
In this mode the effective
address of the operand is the
content of a register specified
in the instruction.
After accessing the operand
the content of this register are
automatically incremented to
point to the next item in a list
In this mode the content of a register
specified in the instruction are first
automatically decremented and then
used effectively.
It can be written as (Ri)+ It can be written as - (Ri)
5. What are the addressing modes?
 The different ways in which the location of an operand is specified in an instruction is
known as addressing modes
 It is a rule for interpreting or translating address field of an instruction into an effective
address from where the operand is actually referenced
The addressing modes are the following:
1. Immediate addressing, where the operand is a constant within the instruction itself
2. Register addressing, where the operand is a register
3. Base or displacement addressing, where the operand is at the memory location whose
address is the sum of a register and a constant in the instruction
4. PC-relative addressing, where the branch address is the sum of the PC and a constant in
the instruction
5. Pseudo direct addressing, where the jump address is the 26 bits of the instruction
concatenated with the upper bits of the PC
6. State the Need for indirect addressing mode. Give an example.
In mode, where the operand is at the memory whose address is the sum of register and
constant in the instruction. Ex: lw sto, 32 (ss3)
7. What is an instruction register (IR)?
An IR is the part of a CPU’s control unit that holds the instruction currently being
executed or decoded.
8. What is instruction set architecture (ISA)?
ISA is a well-defined hardware/software interface. The contract b/w software & hardware ISA is the part of
the computer architecture related to programming including the data types, registers and addressing
modes.Give the formula for CPU execution time for a program?
CPU execution time for program=CPU clock cycles for a program x clock cycle time.
9. List out the methods used to improve system performance.
The methods used to improve system performance are 1. Processor clock 2. Basic Performance

10. Equation 3. Pipelining 4.Clock rate 5.Instruction set 6.Compiler.
10. Define Opcode and Operand .
Opcode is the portion of a machine language instruction that specifies the operation to be
performed.
Ex: MOV AX, 1000H ; here MOV specifies the movement of 1000H in the AX register.
Operand is a quality on which operation is performed. Here AX and 1000H are the
operands.
11. Define MIPS Rate and Throughput Rate.
MIPS Rate: The rate at which the instructions are executed at a given time.
Throughput: The total amount of work done in a given time.
Throughput rate: The rate at which the total amount of work done at a given time.
12. State Amdhal’s law.
Amdahl's law, also known as Amdahl's argument, is used to find the maximum expected
improvement to an overall system when only part of the system is improved. It is often used in
parallel computing to predict the theoretical maximum speedup using multiple processors.
13. Define CPI
The term Clock Cycles Per Instruction Which is the average number of clock cycles each
instruction takes to execute, is often abbreviated as CPI. CPI= CPU clock cycles/Instruction
count.
14. State and explain the performance equation?
The average number of basic steps needed to execute one machine instruction is S, where
each basic step is completed in one clock cycle. If the clock cycle rate is R cycles per second, the
program execution time is given by T = (N x S) / R This is often referred to as the basic
performance equation.
15. How CPU execution time for a program is calculated?
CPU execution time for a program= CPU clock cycles for a program*Clock Cycle Time
CPU execution time for a program =CPU Clock cycles for a program
Clock Rate
16. How to represent Instruction in a Computer System?
The Instruction has three fields:
1. Opcode
2. Operand Address 1
3. Operand Address 2
Opcode Operand Address 1 Operand Address 1

11. 4 Bits 6 Bits 6 Bits
19. Define MAR.
MAR: Memory address register is used to hold the address of the location to or from which data
are to be transferred.
20. Define Word length.
The number of bits in each word is often referred to as the word length of the computer. Word
length ranges from 16 to 64 bits.
1.Define Computer Architecture
Computer Architecture Is Defined As The Functional Operation Of The Individual H/W Unit In A
Computer System And The Flow Of Information Among The Control Of Those Units.
2.Define Computer H/W
Computer H/W Is The Electronic Circuit And Electro Mechanical Equipment that Constitutes the
Computer
3. What are the functions of control unit ?
The memory arithmetic and logic ,and input and output units store and process information and
perform i/p and o/p operation, the operation of these unit must be co ordinate in some way this is the
task of control unit the cu is effectively the nerve center that sends the control signal to other units and
sence their states.
4.What is an interrupt?
An interrupt is an event that causes the execution of one program to be suspended and
another program to be executed.
5. What are the uses of interrupts?
• Recovery from errors
• Debugging
• Communication between programs
• Use of interrupts in operating system
6. Differentiate between RISC and CISC
RISC CISC
Reduced Instruction Set Computer 1. Complex Instruction set computer
Simple instructions take one cycle per
Operation
Complex instruction take multiple
Cycles per operation.
Few instructions and address modes areUsed. Many instruction and address
Modes.

12. Fixed format instructions are used. Variable format instructions are used
Instructions are compiled and then executed by
hardware.
Instructions are interpreted by the
Microprogram and then executed.
RISC machines are multiple registerset. CISC machines use single registerSet.
Complexity in the compiler Complexity in the microprogram
RISC machines are higly piplined CISC machines are not piplined.
7. Specify three types of data transfer techniques.
• Arithmetic data transfer
• Logical data transfer
• Programmed control data transfer
8. What is the role of MAR and MDR?
The MAR (memory address register) is used to hold the address of the location to or from which data
are to be transferred and the MDR(memory data register) contains the data to be written intoor read out
of the addressed location.
9. What are the various types of operations required for instructions?
• Data transfers between the main memory and the CPU registers
• Arithmetic and logic operation on data
• Program sequencing and control
• I/O transfers
10. What is the role of IR and PC?
Instruction Register (IR) contains the instruction being executed. Its output is availableto the control
circuits, which generate the timing signals for controlling the processing circuitsneededto execute the
instructions.The Program Counter (PC) register keeps track of the execution of theprogram. It contains
the memory address of the instruction currently being executed . During the execution of the current
instruction, the contents of the PC are updated to correspond to the address of the next instructions to
be executed.
11.What are the various units in the computer?
• Input unit
• Output unit
• Control unit
• Memory unit
• Arithmetic and logical unit

13. 12. What is an I/O channel?
An I/O channel is actually a special purpose processor, also called peripheral processor. The main
processor initiates a transfer by passing the required information in the input output channel. The
channel then takes over and controls the actual transfer of data.
13.What is a bus?
A collection of wires that connects several devices is called a bus.
Explain the following the address instruction?
• Three-address instruction-it can be represented as add a,b,c Operands a,b are called source operand and c
is called destination operand.
• Two-address instruction-it can be represented as Add a,b
• One address instruction-it can be represented as add a
State and explain the performance equation?
Suppose that the average number of basic steps needed to execute one machine instruction is S, where each
basic step is completed in one clock cycle. If the clock cycle rate is R cycles per second, the program
execution time is given by
T = (N x S) / R This is often referred to as the basic performance equation.
UNIT IV PROCESSOR & CONTROL UNIT
Define MIPS .
MIPS:One alternative to time as the metric is MIPS(Million Instruction Per Second) MIPS=Instruction
count/(Execution time x1000000). This MIPS measurement is also called Native MIPS todistinguish it from some
alternative definitions of MIPS.
Define MIPS Rate
The rate at which the instructions are executed at a given time.
Define a data path in a CPU.
A unit used to operate on or hold data within a processor. In the MIPS implementation, the data
path elements include the instruction and data memories, the register file, the ALU, andadders.
Name the control signals required to perform arithmetic operations.
(a) Reg Not (b) Reg write (c) ALL src (d) PCsrc (e) Mem Read (f) Mem to Reg
Define pipelining.
Pipelining is a technique of decomposing a sequential process into sub operations with
each sub process being executed in a special dedicated segment that operates concurrently with all other
segments.
Define parallel processing.
Parallel processing is a term used to denote a large class of techniques that are used to
provide simultaneous data-processing tasks for the purpose of increasing the computational speed of a
computer system. Instead of processing each instruction sequentially as in a conventional computer, a
parallel processing system is able to perform concurrent data processing to achieve faster execution time.
Define hazard. Give an example for data hazard.
Any condition that causes the pipeline to stall is called a hazard. Data hazards occur
when the pipeline must be stalled because one step must wait for another to complete.
add $s0, $t0, $t1
sub $t2, $s0, $t3

14. What is meant by pipeline bubble?
Pipeline bubble or pipeline stall is a delay in execution of an instruction in an instruction
pipeline in order to resolve the hazard. During the decoding stage, the control unit will
determine if the decoded instruction reads from a register that the instruction currently in the
What is the ideal CPI of a pipelined processor?
The ideal CPI on a pipelined processor is almost always 1. Hence, we can compute the
pipelined CPI:
CPIpipelined=IdealCPI+Pipelinestal clockcyclesperinstruction=1+Pipelinestallclockcyclesperinstruction
Mention the various types of pipelining.
It is divided into 2 categories:
 Arithmetic Pipeline
 Instruction Pipeline
Mention the various phase in executing an instruction.
 Fetch
 Decode
 Execute
 Memory
 Write Back
Define instruction pipeline.
The transfer of instructions through various stages of the CPU instruction cycle.,including
fetch opcode, decode opcode, compute operand addresses. Fetch operands, execute Instructions and store results. This
amounts to realizing most (or) all of the CPU in the form of multifunction pipeline called an instruction pipelining
What are the advantages of pipelining?
The cycle time of the processor is reduced, thus increasing instruction issue rate in most
cases. Some combinational circuits such as adders or multipliers can be made faster by adding
more circuitry. If pipelining is used instead it can save circuitry and also a more complex
combinational circuit.
What is meant by branch prediction?
Branch prediction, Predict the next fetch address. There are two branch prediction
techniques:
 Static branch prediction
 Dynamic branch prediction
The performance of branch prediction technique depends on
 Accuracy
 Cost
Give the features of the addressing modes suitable for pipelining.
The addressing modes used in modern processors often have the following features:
 Access to an operand does not require more than one access to the memory
 Only load and store instructions access memory operands
The addressing modes used do not have side effects
What is the role of cache memory in pipeline?
The use of cache memory is to solve the memory access problem. When cache is included in the
processor the access time to the cache is usually the same time needed to perform other basic
operation inside the processor.

15. Name the methods for generating the control signals.
The methods for generating the control signals are:
1) Hardwired control
2) Microprogrammed control
What are the two main approaches to hardware multithreading?
There are two main approaches to hardware multithreading. Fine-grained multithreading
switches between threads on each instruction, resulting in interleaved execution of
multiple threads. This interleaving is often done in a round-robin fashion, skipping any
threads that are stalled at that clock cycle. Coarse-grained multithreading is an alternative
to fine-grained multithreading. It switches threads only on costly stalls, such as last-level
cache misses.
State different types of hazards that can occur in pipeline.
The types of hazards that can occur in the pipelining were, 1. Data hazards. 2. Instruction hazards. 3.
Structural hazards.
Define Data hazards
A data hazard is any condition in which either the source or the destination operands of an instruction are
not available at the time expected in pipeline. As a result some operation has to be delayed, and the
pipeline stalls.
Define Instruction hazards
The pipeline may be stalled because of a delay in the availability of an instruction. For example, this
may be a result of miss in cache, requiring the instruction to be fetched from the main memory. Such
hazards are called as Instruction hazards or Control hazards.
Define Structural hazards?
The structural hazards is the situation when two instructions require the use of a given hardware resource at
the same time. The most common case in which this hazard may arise is access to memory.
What are the classification of data hazards?
Classification of data hazard: A pair of instructions can produce data hazard by referring reading or writing
the same memory location. Assume that i is executed before J. So, the hazards can be classified as, 1. RAW
hazard 2. WAW hazard 3. WAR hazard
Define RAW hazard :
( read after write) Instruction ‘j’ tries to read a source operand before instruction ‘i’ writes it.
Define WAW hazard :
( write after write) Instruction ‘j’ tries to write a source operand before instruction ‘i’ writes it.
Define WAR hazard :
( write after read) Instruction ‘j’ tries to write a source operand before instruction ‘i’ reads it.
List out the methods used to improve system performance.
The methods used to improve system performance are 1. Processor clock 2.Basic Performance
Equation 3.Pipelining 4.Clock rate 5.Instruction set 6.Compiler

16. UNIT V
What is meant by exception? Give one example of MIPS exception.
Exception is an unscheduled event that disrupts program execution; used to detect overflow.
Or
An exception or interrupt is essentially an unscheduled procedure call. The address of the
instruction that overflowed is saved in a register, and the computer jumps to a predefined
address to invoke the appropriate routine for that exception. The interrupted address is saved so
that in some situations the program can continue after corrective code is executed.
add $S1, $S2, $S1,
What is meant by address mapping?
Address mapping is defined as the smallest unit of addressed data that can be mapped
independently in an area of the virtual address space.
Protein string matching code has four days execution time on current machinedoing integer
instructions in 20 % of time, doing I/O in 35% of time and other operations in the
remaining time. Which is the better trade off among the following two proposals? First:
Compiler optimization that reduces number of integer instructions by 25% (assumeeach
integer instruction takes the same amount of time); Second: Hardware optimization that
reduces the latency of each I/O operations from 6µs to 5 µs.
Solution:
4 days execution time on current machine
20% of time doing integer instructions
35% of time doing I/O
Speed up integer ops
X=0.2
S= (1/1-0.25)=1.33
Sint =1/(0.2/1.133+0.8) = 1.052
Speed up IO
X=0.35
S=6µs/5 µs = 1.2
Speeding Up IO is better
Give example for each class in Flynn’s classification.
SISD: Traditional Uniprocessor
SIMD: The intel Pentium 3
MISD: Multiple Frequency filters operating on a single signal stream
MIMD: Sun Ultra Services
Give the key characteristics of GPUs from CPUs:
 GPUs are accelerators that supplement a CPU, so they do not need be able to perform
all the tasks of a CPU. This role allows them to dedicate all their resources to
graphics. It’s fine for GPUs to perform some tasks poorly or not at all, given that in a
system with both a CPU and a GPU, the CPU can do them if needed.
 The GPU problems sizes are typically hundreds of megabytes to gigabytes, but not
hundreds of gigabytes to terabytes.

17. What is Cluster?
Clusters are generally collections of computer connected to each other over their I/O
interconnect via standard network switches and cables. Clusters are the best example of
message passing parallel computer.
What are the three major distinctions Warehouse Scale computers have?
 Ample, easy parallelism
 Operational Costs Count
 Scale and the Opportunities/Problems Associated with Scale
What are the classifications made by Flynn’s?
The classifications defined by Flynn are based upon the number of concurrent instruction (or
control) and data streams available in the architecture.
1. Single Instruction, Single Data stream (SISD)
2. Single Instruction ,Multiple data stream(SIMD)
3. Multiple Instruction, Single Data stream (MISD)
4. Multiple Instruction, Multiple Data streams (MIMD)
single program, multiple data (SPMD)
what is the basic philosophy of Vector Architecture?
The basic philosophy of vector architecture is to collect data elements from memory, put them in
order into a large set of registers, operate on them sequentially in registers using pipelined
execution units, and then write the results back to memory.
Define task level parallelism.
High performance can mean high throughput for independent task. Utilizing multiple processors
by running independent programs simultaneously is called as task level parallelism or process-
level parallelism.
What are the various memory technologies?
 Main memory-SRAM semiconductor memory
 Main memory-DRAM semiconductor memory
 Flash semiconductor memory
 Magnetic disk
Define Hit Ratio.
Hit Ratio is the fraction memory access found in the upper level .It is often used as a measure of
the performance of the memory hierarchy.
Distinguish SRAM and DRAM.
SRAMs are simply integrated circuits that are memory arrays with the single access port
that can provide either read or a write. SRAMs have a fixed access time to any datum. SRAMs
don’t need to refresh and so the access time is very close to the cycle time. SRAMs typically
use 6 to 8 transistors per bit to prevent the information from being disturbed when read. SRAM
needs only minimal power to retain the charge in standby mode.
In a DRAM the value kept in a cell is stored as a charge in a capacitor. A single transistor
is then used to access this stored charge, either to read the value or to over write the charge
stored there. Because DRAMs use only a single transistor per bit of storage, they are much
denser and cheaper per bit than SRAM. As DRAM store charge on a capacitor, it cannot be kept
indefinitely and must periodically be refreshed.

18. What is virtual memory?
A technique that uses main memory as a “cache” for secondary storage. Two major
motive for Virtual Memory
 To allow efficiency and safe sharing of memory among multiple programs
 To remove the programming burdens of a small, limited amount of main memory
Define memory hierarchy.
In computer architecture memory hierarchy is a concept used for storing and discussing
performance issues in computer architectural design, algorithm predictions and the lower level
programming constructs such as involving locality of reference. The memory hierarchy in
computer storage distinguishes each level in the hierarchy by response time. Since response
time, complexity and capacity are related, the levels may also be distinguished by their
performance and controlling technologies.
State the advantages of virtual memory
 Easier memory management
 Provides memory isolation/ protection
What is cache memory?
Cache memory is random access memory (RAM) that a computer microprocessor can
access more quickly that it can access regular RAMs
Define memory interleaving.
Memory Interleaving is a design made to compensate for the relatively slow speed of
dynamic RAM by spreading memory address evenly across memory banks.
Summarize the sequence of the events involved in handling an interrupt request
from a single device.
 The device raises an interrupt request
 The processor interrupts the program currently being executed
 Interrupts are disabled by changing the control bits in the PS
 The action requested by the interrupts is performed by ISR
 Interrupts are enabled and execution of the interrupted program is resumed
How many total bits are required for a direct map cache with 16KB of data and 4-
word blocks, assuming a 32bit address?
Solution:
We know that 16KB is 4096, 4K words is 212
words.
Block size of 4 words (22
), there are 1024 (210
) blocks.
Each block has 4 x 32 = 128 bits of data plus a tag.
Thus the total catch size is: 210 x (128+(32-10-2-2)+1) = 210 x 147 = 147 bits
What is the use of DMA controller?
 Used for high speed I/O devices
 Device interface transfers data directly to or from the memory
 Processor not continuously involved
What is miss rate?
The miss rate (1−hit rate) is the fraction of memory accesses not found in the upper level.
State the advantages of the Virtual Memory.
1. Virtual memory makes application programming easier by hiding fragmentation of
physical memory.

19. 2. We can run more applications at once.
Specify the three types of the DMA transfer techniques?
--Single transfer mode(cyclestealing mode)
--Block Transfer Mode(Brust Mode)
--Demand Transfer Mode
--Cascade Mode
Why program controlled I/O is unsuitable for high-speed data transfer?
In program controlled i/o considerable overhead is incurred..because several program instruction
have to be executed for each data word transferred between the external devices and MM.Many high
speed peripheral; devices have a synchronous modes of operation.that is data transfer are controlled by a
clock of fixed frequency, independent of the cpu.
What are the steps taken when an interrupt occurs?
*Source of the interrupt
*The memory address of the required ISP
* The program counter &cpu information saved in subroutine
*Transfer control back to the interrupted program
Define interface.
The word interface refers to the boundary between two circuits or devices
What is programmed I/O?
Data transfer to and from peripherals may be handled using this mode. Programmed I/O
operations are the result of I/O instructions written in the computer program.
What is DMA?
A special control unit may be provided to enable transfer a block of data directly between an
external device and memory without contiguous intervention by the CPU. This approach is called DMA.
Differentiate Programmed I/O and Interrupt I/O
Sl.
No
Programmed I/O Interrupt I/O
1 During polling processor is
busy and therefore have
serious and decremental
effect on system throughput.
Here the processor is allowed to
execute its instruction in sequence
and only stop to service I/O device
when it is told to do so by the device
itself. This increase system
throughput.
2 It is implemented without
interrupt hardware support
It is implemented using interrupt
hardware support.
3 It does not depend on
interrupt status.
Interrupt must be enabled to process
4 It does not need
initialization of stack
It needs initialization of stack
5 System throughput
decreases as number of I/O
devices connected in the
system increases
System throughput does not depend
on number of I/O devices connected
in the system.

20. What do you mean by memory mapped I/O?
In Memory mapped I/O, there is no specific input or output instructions. The CPU can
manipulate I/O data residing in interface registers with the same instructions that are used to
manipulate memory words.
Draw Memory Hierarchy in a typical computer system