CAD of digital circuits has been a topic of great importance. Topics in CAD includes design synthesis & optimization of some figure of merits like area,performance.

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2.  To understand the need for optimization and
dimensions of optimization for digital circuits.
 To introduce students to basic optimization
techniques used in circuits design.
 To introduce students to advanced tools and
techniques in digital systems design. These include
Hardware Modeling and Compilation Techniques.
 To introduce in details Logic-Level synthesis and
optimization techniques for combinational and
sequential circuits.
 To introduce the students to the concept of
scheduling and resource binding for optimization.
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3.  Understand the process of synthesis and
optimization in a top down approach for digital
circuits models using HDLs.
 Understand the terminologies of graph theory and
its algorithms to optimize a Boolean equation.
 Apply different two level and multilevel
optimization algorithms for combinational circuits.
 Apply the different sequential circuit optimization
methods using state models and network models.
 Apply different scheduling algorithms with
resource binding and without resource binding for
pipelined sequential circuits and extended
sequencing models.
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4. 1. Introduction to synthesis & optimization
2. Hardware Modeling
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5. 1. Introduction to synthesis & optimization
 Introduction to microelectronics
 Design of Microelectronic Circuits
 Computer-Aided Synthesis & Optimization.
2. Hardware Modeling
 Introduction to Hardware Modeling Languages
 HDLs for Synthesis
 Abstract models
 Compilation and Behavioral Optimization.
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6. 1. Introduction to synthesis & optimization
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8.  Last two factors can be achieved using
computer-Aided Design (CAD) techniques.
 Computer-aided techniques have provided the
enabling methodology to design efficiently and
successfully large-scale high-performance
circuits for a wide spectrum of applications,
ranging from information processing (e.g.,
computers) to telecommunication,
manufacturing control, transportation, etc.
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9.  Semiconductor technologies
 CMOS
 BICMOS
 SOS
It affects mainly physical design of circuit
 Circuit type
 Analog & Digital circuits
 Synchronous & asynchronous.
It affects overall design of the circuit.
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10.  Design styles
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Custom
design style
Semicustom
design style
1. High quality circuits 1. Quality circuits
2. Design effort is high 2. Design effort required is less
3. Cost required is high 3. Depends
4. Flexibility is very high 4. Flexibility is high
5. Design time required is very high. 5. Design time required is less

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12.  Circuit models
 Synthesis
 Optimization
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13.  A model of a circuit is an abstraction, i.e., a representation that
shows relevant features without associated details.
 Models can be classified in terms of levels of abstraction and
views.
 Three main abstractions namely:
Architectural level : performs a set of operation.
Logic level: evaluates set of logic function.
Geometrical level: performs set of geometrical entities.
 Three views of a model namely:
Behavioral view : describes function of circuit.
Structural views : describes interconnection of components.
Physical views : relates to physical object of design.
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Three abstraction
levels
1.a-level
(architectural-level)
2. l-level
(logic-level)
3. g-level
(geometrical-level)
Three views
1. b-view
(Behavioral –view)
2. s-view
(structural-view)
3. p-view
(physical-view)

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HDL
Intercon
nection
of gates
Mask
layout
Levels of abstraction Levels of abstraction & corresponding views

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17.  Synthesis is the generation of a circuit model,
starting from a less detailed one.
 Synthesis techniques speed up the design cycle
and reduce the human effort.
 Synthesis can be seen as a set of
transformations between two axial views
namely
 Architectural –level synthesis
 Logic –level synthesis
 Geometrical-level synthesis
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19.  Also known as high-level synthesis or structural synthesis.
 It determines macroscopic structure of the circuit.
 It determines resources , as well as their interconnection & timing of their
execution.
 Example :Architectural synthesis tasks: data path with two resources
multiplier & ALU performs +,-,comparison. Also contains registers,
steering logic, control unit.
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Behavioral view of
architectural model
Structural veiw of
architectural model

20.  Also known as gate-level synthesis.
 It determines microscopic structure of the circuit.
 A logic-level model of a circuit can be provided by a state transition diagram of a
finite-state machine, by a circuit schematic or equivalently by an HDL model.
 Example : control unit uses one state for reading data s1,one for writing data
s9,seven states for executing the loop, signal r is reset signal.
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Behavioral view at logic level of
control unit
Structural
view at
logic level
of control
unit

21.  Also known as physical design -level synthesis.
 It consists of creating a physical view at the
geometric level.
 It entails the specification of all geometric
patterns defining the physical layout of the chip,
as well as their position.
 Physical design depends much on the design
style.
 The major tasks in physical design are placement
and wiring, called also routing.
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22.  Optimization techniques enhance the design quality.
 Circuit optimization is often performed in conjunction
with synthesis.
 Optimization is motivated not only by the desire of
maximizing the circuit quality, but also by the fact that
synthesis without optimization would yield
noncompetitive circuits at all, and therefore its value
would be marginal.
 Optimization of two quality measures, namely: area and
performance.
 Design optimization as the combined minimization of
area and maximization of performance.
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23.  The different feasible structural implementations of a
circuit using design optimization define its design space.
 The design space is a finite set of design points.
Associated with each design point, there are values of the
area and performance evaluation functions.
 Design evaluation space is the multidimensional space
spanned by design objectives such as area, latency, cycle-
time and throughput.
 A point of the design space is called a Pareto point if
there is no other point (in the design space) with at least
an inferior objective, all others being inferior or equal.
 A Pareto point corresponds to a global optimum in a
monodimensional design evaluation space.
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Taking 1 multiplier,1 ALU a1=1,a2=1
a1-multiplier,a2-ALU
Area required is
5 units of area for 1 multiplier
1 units of area for 1 ALU
1 units of area for Controlunit,steering,memory.
Total area = 5+1+1=7 units
Multiplier
Latency required is
1 cycle= 3* x , x+dx = * , +
2 cycle=3*x*u, x1<a = * , <
3cycle=3*x*u*dx = *
4cycle=3*y , u-(3*x*u*dx)= * , -
5cycle=3*y* dx = *
6cycle=u* dx, [u-(3*x*u* dx) -3*y* dx]
= * , -
7cycle=y+u*dx = +
Total 7 cycles to execute

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Taking 2 multipliers , 2 ALUs
a1=2 , a2=2
Area required is
5 units of area for 1 multiplier= 2*5 =10 units
1 units of area for 1 ALU= 2*1= 2 units
1 units of area for Control unit, steering,memory.
Total area = 10+2+1=13 units
multiplier
multiplier
Latency required is
1 cycle= 3* x , u*dx,3*y, x+dx
= * , +,*
2 cycle=3*x*u*dx, x1<a , 3*y* dx,
y+u*dx = * , <,*,+
3cycle=u-(3*x*u*dx) = -
4cycle= [u-(3*x*u* dx) -3*y* dx]
= -
Total 4 cycles to execute

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Taking 2 multipliers , 1 ALUs
a1=2 , a2=1
Area required is
5 units of area for 1 multiplier= 2*5 =10
units
1 units of area for 1 ALU= 1= 1 units
1 units of area for Control unit,
steering,memory.
Total area = 10+1+1=12 units
Latency required is
1 cycle= 3* x , u*dx,3*y, x+dx
= * , +,*
2 cycle=3*x*u*dx, 3*y* dx,
y+u*dx = * , *,+
3cycle=u-(3*x*u*dx) = -
4cycle= [u-(3*x*u* dx) -3*y* dx] = -
5cycle=x1<a= <
Total 5 cycles to execute

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Taking 1 multiplier,1 ALU a1=1,a2=2
a1-multiplier,a2-ALU
Area required is
5 units of area for 1 multiplier
1 units of area for 1 ALU=2*1=2
1 units of area for Control
unit,steering,memory.
Total area = 5+2+1=8 units
Latency required is
1 cycle= 3* x , x+dx = * , +
2 cycle=3*x*u, x1<a = * , <
3cycle=3*x*u*dx = *
4cycle=3*y , u-(3*x*u*dx)= * , -
5cycle=3*y* dx = *
6cycle=u* dx, [u-(3*x*u* dx) -3*y* dx]
= * , -
7cycle=y+u*dx = +
Total 7 cycles to execute

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1. a1=2,a2=2
Area=13,latency=4
2. a1=2,a2=1
Area=12,latency=5
3. a1=1,a2=2
Area=8,latency=7
4. a1=1,a2=1
Area=7,latency=7
3rd
one only increases area
compared to 4th
one. so it is not a
pareto point. The remaining
points {(1,1):(2,1):(2,2)} are
pareto points.

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30. SODC[As per VTU M.Tech IV Sem]
For notes & slides contact to:
s.tutorials04@gmail.com
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