4_BIT_ALU

ABSTRACT
An Arithmetic Logic Unit (ALU) is a digital circuit that performs arithmetic and logical
operations. The ALU is a fundamental building block of the central processing unit
(CPU) of a computer, and even the simplest microprocessors contain one for
purposes such as maintaining timers. The processors found inside modern CPUs
and graphics processing units (GPUs) accommodate very powerful and very
complex ALUs; a single component may contain a number of ALUs. In this project, I
have developed a 4-bit ALU. I have designed the ALU in hardware description
language – VHDL. The functionality of the design is verified by Test Bench
Waveform that produces the simulation results to detect whether the design
functions correctly or not.
OBJECTIVES
The purpose of this project is:
 To design a 4-bit ALU
 Each input to produce a required output based on the output selector line.
 The possible outputs to be OR, AND, NOR, NOT, XOR, NAND, XNOR, ADDER,
INCREMENT, SUBTRACTOR, DECREMENT AND TRANFER SAME.
 Our task is also to design and implement the 4-bit ALU using the Xilinx
Foundation tools.
 To implement the ALU on a FPGA
An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and
arithmetic micro-operations on a pair of n-bit operands (ex. A [3:0] and B [3:0]). The
operations performed by an ALU are controlled by a set of function-select inputs. Finally the
functionality of the design is verified by Test Bench Waveform that produces the simulation
results to detect whether the design functions correctly or not.

INTRODUCTION
An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and
arithmetic micro-operations on a pair of n-bit operands (ex. A [3:0] and B [3:0]). The
operations performed by an ALU are controlled by a set of function-select inputs. The
processors found inside modern CPUs and graphics processing units (GPUs) accommodate
very powerful and very complex ALUs; a single component may contain a number of ALUs.
The ALU has a number of selection lines to select a particular operation in the unit. The
selection lines are decoded within the ALU so that K selection variables can specify up to 2^k
distinct operations. Here is an example of a simple 4-bit ALU.
The 4 data inputs from A combined with 4 data inputs from B to generate an operation at the
F outputs. The mode select input S3 distinguishes between arithmetic and logic operations.
The three function select inputs S2, S1 and S0 specify the particular arithmetic and logic
operation to be generated. With 4 selection variables, it is possible to specify eight arithmetic
operations (with S3 in one state) and eight logical operations (with S3 in another state). The
input and output carries have meaning only during an arithmetic operation. The input carry
is the least significant position of an ALU. The design of a typical ALU will be carried out in
three stages. First, the design of arithmetic section will be undertaken. Second, the design of
logic section will be considered. Finally, the arithmetic section and logic section will be
combined to form an ALU.
In this project a 4-bit ALU has been designed using the hardware description language –
VHDL by Xilinx ISE 8.2i software. Each lower level component of the ALU is designed using
VHDL and verified by creating test bench waveform that produces the simulation results to
determine to determine whether the design functions properly or not.
2 | P a g e

INTRODUCTION TO XILINX (INTRODUCTION TO FPGA TECHNOLOGY)
Xilinx (an Electronics Company) is the world’s largest supplier of programmable logic
devices and the inventor of the field programmable gate array (FPGA). Today Xilinx is the
worldwide leader of complete programmable logic solutions.
Xilinx has two main FPGA families – the high performance video Virtex series and the high
volume Spartan series. Each model series has been released in multiple generations since its
launch. The latest Virtex-6 and Spartan-6 FPGA families are said to consume 50 % less power ,
cost 20 % less , and have up to twice the logic capacity of previous generations of FPGAs. The
Spartan series targets applications with low power footprint, extremes cost sensitivity and high
volume e.g. displays, set top boxes wireless routers and other applications.
The ISE Design Suite is the central electronic design automation (EDA) product family sold
by Xilinx .The ISE Design Suite features include design entry and synthesis supporting
Verilog or VHDL, place and route (PAR), completed verification and Chipscope pro tools,
and creation of the bit files that are used to configure the chip.
Xilinx designs, develops and markets programmable logic products including integrated
circuits (ICs), software design tools and services. Xilinx sells both FPGAs and CPLDs
(Complex Programmable Logic Devices) for electronic equipment manufacturers.
XILINX ISE 8.2i (The Integrated Software Environment)
Xilinx ISE (Integrated Software Environment) 8.2i tool is the latest release of Xilinx’s widely
used design solutions. Xilinx delivers ISE 8.2i- a complete logic design solution for the next
Virtex-5 FPGA family. The ISE 8.2i design environment enables 30% faster performance
than previous generation FPGAs. The ISE 8.2i design suite is accompanied by the release of
Chip Scope 8.2 debug and verification software. Available as an add-on option, the Chip
Scope Pro 8.2 solution reduces verification cycles by up to 50%. ISE software offers
programmable logic design solution to over 3,00,000 users worldwide with an intuitive,
front-to-back design environment for all Xilinx product families, including Spartan-3
Generation FPGAs. All versions of ISE 8.2i software packages support Windows 2000 and
Windows XP and Linux Red Hat Enterprise 3.0.
3 | P a g e

Spartan-3E FPGA
Starter Kit Board

Spartan-3E FPGA Features and Embedded Processing Functions
The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA
family and provides a convenient development board for embedded processing applications.
The board highlights these features:
• Spartan-3E FPGA specific features
♦ Parallel NOR Flash configuration
♦ MultiBoot FPGA configuration from Parallel NOR Flash PROM
♦ SPI serial Flash configuration
• Embedded development
♦ MicroBlaze™ 32-bit embedded RISC processor
♦ PicoBlaze™ 8-bit embedded controller
♦ DDR memory interfaces
Key Components and Features
The key features of the Spartan-3E Starter Kit board are:
• Xilinx XC3S500E Spartan-3E FPGA
♦ Up to 232 user-I/O pins
♦ 320-pin FBGA package
♦ Over 10,000 logic cells
• Xilinx 4 Mbit Platform Flash configuration PROM
4 | P a g e

Xilinx 64-macrocell XC2C64A CoolRunner™ CPLD
• 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
• 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
♦ FPGA configuration storage
♦ MicroBlaze code storage/shadowing
• 16 Mbits of SPI serial Flash (STMicro)
♦ FPGA configuration storage
♦ MicroBlaze code shadowing
• 2-line, 16-character LCD screen
• PS/2 mouse or keyboard port
• VGA display port
• 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
• Two 9-pin RS-232 ports (DTE- and DCE-style)
• On-board USB-based FPGA/CPLD download/debug interface
• 50 MHz clock oscillator
• SHA-1 1-wire serial EEPROM for bitstream copy protection
• Hirose FX2 expansion connector
• Three Digilent 6-pin expansion connectors
• Four-output, SPI-based Digital-to-Analog Converter (DAC)
• Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain
Pre-amplifier
• ChipScope™ SoftTouch debugging port
• Rotary-encoder with push-button shaft
• Eight discrete LEDs
• Four slide switches
• Four push-button switches
• SMA clock input
• 8-pin DIP socket for auxiliary clock oscillator.
5 | P a g e

FPGA – Field-programmable gate array
A field-programmable gate array (FPGA) is a semiconductor device that can be
configured by the customer or designer after manufacturing—hence the name "field-
programmable". FPGAs are programmed using a logic circuit diagram or a source
code in a hardware description language (HDL) to specify how the chip will work.
They can be used to implement any logical function that an application-specific
integrated circuit (ASIC) could perform, but the ability to update the functionality after
shipping offers advantages for many applications.
FPGAs contain programmable logic components called "logic blocks", and a
hierarchy of reconfigurable interconnects that allow the blocks to be "wired
together"—somewhat like a one-chip programmable breadboard. Logic blocks
can be configured to perform complex combinational functions, or merely
simple logic gates like AND and XOR. In most FPGAs, the logic blocks also
include memory elements, which may be simple flip-flop or more complete
blocks of memory.
FPGA – Architecture
The most common FPGA architecture consists of an array of configurable logic
blocks (CLBs), I/O pads, and routing channels. Generally, all the routing
channels have the same width (number of wires). Multiple I/O pads may fit into
the height of one row or the width of one column in the array.
An application circuit must be mapped into an FPGA with adequate resources.
While the number of CLBs and I/Os required is easily determined from the
design, the number of routing tracks needed may vary considerably even among
designs with the same amount of logic.
A classic FPGA logic block consists of a 4-input lookup table (LUT),
and a flip- flop, as shown below. In recent years, manufacturers have started
moving to 6-input LUTs in their high performance parts, claiming increased
performance.
Typical logic block
There is only one output, which can be either the registered or the unregistered
LUT output. The logic block has four inputs for the LUT and a clock input. Since

clock signals (and often other high-fan-out signals) are normally routed via
special-purpose dedicated routing networks in commercial FPGAs, they and other
signals are separately managed.
For this example architecture, the locations of the FPGA logic block pins are
shown below.
6 | P a g e

Logic Block Pin Locations
Each input is accessible from one side of the logic block, while the output pin can
connect to routing wires in both the channel to the right and the channel below the
logic block.
Each logic block output pin can connect to any of the wiring segments in the
channels adjacent to it.
Similarly, an I/O pad can connect to any one of the wiring segments in the
channel adjacent to it. For example, an I/O pad at the top of the chip can
connect to any of the W wires (where W is the channel width) in the horizontal
channel immediately below it.
Generally, the FPGA routing is unsegmented. That is, each wiring segment
spans only one logic block before it terminates in a switch box. By turning on
some of the programmable switches within a switch box, longer paths can be
constructed. For higher speed interconnect, some FPGA architectures use
longer routing lines that span multiple logic blocks.
Whenever a vertical and a horizontal channel intersect, there is a switch box. In
this architecture, when a wire enters a switch box, there are three
programmable switches that allow it to connect to three other wires in adjacent
channel segments. The pattern, or topology, of switches used in this architecture
is the planar or domain-based switch box topology. In this switch box topology,
a wire in track number one connects only to wires in track number one in
adjacent channel segments, wires in track number 2 connect only to other wires
in track number 2 and so on. The figure below illustrates the connections in a
switch box.

Switch box topology
Modern FPGA families expand upon the above capabilities to include higher
level functionality fixed into the silicon. Having these common functions
embedded into the silicon reduces the area required and gives those functions
increased speed compared to building them from primitives. Examples of these
include multipliers, generic DSP blocks, embedded processors, high speed IO
logic and embedded memories.
7 | P a g e

VHDL
VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description
language) is commonly used as a design-entry language for field-programmable
gate arrays and application- specific integrated circuits in electronic design
automation of digital circuits.
VHDL was originally developed at the behest of the US HYPERLINK
"http://en.wikipedia.org/wiki/United_States_Department_of_Defense" Department
of Defense in order to document the behavior of the ASICs that supplier companies
were including in equipment. That is to say, VHDL was developed as an alternative
to huge, complex manuals which were subject to implementation-specific details.
The idea of being able to simulate this documentation was so obviously attractive
that logic simulators were developed that could read the VHDL files. The next step
was the development of logic synthesis tools that read the VHDL, and output a
definition of the physical implementation of the circuit. Modern synthesis tools can
extract RAM, counter, and arithmetic blocks out of the code, and implement them
according to what the user specifies. Thus, the same VHDL code could be
synthesized differently for lowest area, lowest power consumption, highest clock
speed, or other requirements.
VHDL borrows heavily from the Ada programming language in both concepts (for
example, the slice notation for indexing part of a one-dimensional array) and syntax.
VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such
as Xilinx or Quartus) to produce the RTL schematic of the desired circuit. After that, the
generated schematic can be verified using simulation software (such as ModelSim)
which shows the waveforms of inputs and outputs of the circuit after generating the
appropriate test bench. To generate an appropriate test bench for a particular circuit or
VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop
process or an iterative statement is required.
The key advantage of VHDL when used for systems design is that it allows the
behavior of the required system to be described (modelled) and verified (simulated)
before synthesis tools translate the design into real hardware (gates and wires).
Another benefit is that VHDL allows the description of a concurrent system (many
parts, each with its own sub-behavior, working together at the same time). VHDL is
a Dataflow language, unlike procedural computing languages such as BASIC, C,
and assembly code, which all run sequentially, one instruction at a time.
A final point is that when a VHDL model is translated into the "gates and wires" that
are mapped onto a programmable logic device such as a CPLD or FPGA, then it is
the actual hardware being configured, rather than the VHDL code being "executed"
as if on some form of a processor chip.

TOOLS / ENVIRONMENT USED
HARDWARES:
1
. Computer : IBM or compatible
2
. Hard disk : 20 GB or higher
3
. Processor
: PENTIUM– IV 2 GHz or
above
4
. Ram : 512 Mb and above
5
. VDU : VGA
6
. Xilinx Spartan–3E FPGA Starter Kit Board
SOFTWARES:
1
. OPERATING SYSTEM : Windows XP
2
.
DEVELOPMENT
SOFTWARE : Xilinx ISE 8.2i

PROJECT PLANNING
Estimating some basic attributes of the project-
 Cost: 100 INR
 Duration: 1 WEEK
 Effort: 7 hrs. of Group Discussion and at least 5 hrs. of studying per day.
The effectiveness of the subsequent planning activities is based on the accuracy of these
estimations.
 Scheduling manpower and other resources
 Staff organization and staffing plans
 Risk identification and analysis
 Miscellaneous plans such as quality assurance plan, configuration management
plan etc.
Developing a system requires planning and coordinating resources within a given time. More
importantly, effective project management is required to organize the available resources,
schedule the events and establish standards.
The following figure shows the order in which the important planning activities may be
undertaken. Size estimation is the first of all activities. It is also the most fundamental
parameter based on which all other planning activities are carried out. Other activities such
as estimation of effort, cost, resources and project duration are also important components of
project planning.

Project planning involves plotting project activities against a time frame. One of the first
steps in planning is development of the road map structure or a network based analysis of the
tasks that must be performed to complete the project.
10 | P a g e

DESIGN
When designing the ALU we will follow the principle "Divide and Conquer" in order to use a
modular design that consists of smaller, more manageable blocks, some of which can be re-used.
Instead of designing the 4-bit ALU as one circuit we will first design one bit OR, AND, NOR,
NOT, XOR, NAND, XNOR, ADDER, SUBTRACTOR AND TRANFER SAME. These bit-slices can
then be put together to make a 4-bit OR, AND, NOR, NOT, XOR, NAND, XNOR, ADDER,
INCREMENT, SUBTRACTOR, DECREMENT AND TRANFER SAME.
The approach used here is to split the ALU into two modules, one Logic and one
Arithmetic module. Designing each module separately will be easier than designing a bit-
slice as one unit. A possible block diagram of the ALU is shown in Figure. It consists of one
module: 2:1 MUX, two 8:1 MUX, a Logic unit and an Arithmetic unit.
Here the logic unit is made up of an 8:1 MUX. Each input to the logic unit is the output from
2:1 MUX of OR, AND, NOR, NOT, XOR, NAND and XNOR.
In the same way the arithmetic unit is made up of another 8:1 MUX. Each into to the MUX is
the output from 2:1MUX of ADDER, INCREMENT, SUBTRACTOR, DECREMENT and
TRANFER SAME.
11 | P a g e

VHDL Code Listing for Every Component of the ALU
---------------------------------------------------------------------------------
-
- Company:
- Engineer:
-
- Create Date: 18:30:35 10/7/2013
- Design Name:
- Module Name: ALU - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
- Revision 0.01 - File Created
- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
- Uncomment the following library declaration if instantiating
- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port (
A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : inout STD_LOGIC_VECTOR (4 downto 0);
SEL : in STD_LOGIC_VECTOR (3 downto 0));
end ALU;
architecture Behavioral of ALU
is component ARITHMETIC_UNIT
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (4 downto 0);
end component;
component LOGIC_UNIT
end component;
component MUX2TO1
Port ( Z1 : in STD_LOGIC_VECTOR (4 downto 0);
Z2 : in STD_LOGIC_VECTOR (3 downto 0);
SEL: in STD_LOGIC);
end component;
signal Z1: STD_LOGIC_VECTOR (4 downto 0);
signal Z2: STD_LOGIC_VECTOR (3 downto 0);
begin
ALU0: ARITHMETIC_UNIT port map (A, B, Z1, SEL (2 downto
0)); ALU1: LOGIC_UNIT port map (A, B, Z2, SEL (2 downto

0)); ALU3: MUX2TO1 port map (Z1, Z2, Z, SEL (3));
end Behavioral;
13 | P a g e

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 18:35:39 10/7/2013
- Design Name:
- Module Name: ARITHMETIC_UNIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity ARITHMETIC_UNIT is
Port ( A : in
STD_LOGIC_VECTOR (3 downto
0);
SEL : in
0));
end ARITHMETIC_UNIT;
architecture Behavioral of ARITHMETIC_UNIT is
component FOURBITADDER
Z : out STD_LOGIC_VECTOR (4 downto 0));
end component;
component FOURBITSUBTRACTOR
end component;
component
MUX8TO1
is
Z2
:
in STD_LOGIC_VECTOR (4 downto 0);
Z3
:
Z4
:
Z5
:
Z6
:
Z7
:
Z8
:
end component;
signal Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8: STD_LOGIC_VECTOR (4 downto 0);
begin

Z7 <= '0'
&
A;
Z8 <= '0'
&
B;
ARI0: FOURBITADDER PORT MAP (A, B, Z1);
ARI1: FOURBITSUBTRACTOR PORT MAP (A, B,
Z2); ARI2: FOURBITADDER PORT MAP (A,
"0001", Z3); ARI3: FOURBITADDER PORT MAP
("0001", B, Z4);
ARI4: FOURBITSUBTRACTOR PORT MAP (A, "0001", Z5);
ARI5: FOURBITSUBTRACTOR PORT MAP (B, "0001", Z6);
ARI6: MUX8TO1 PORT MAP (Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z,
SEL); end Behavioral;
14 | P a g e

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 23:18:52 10/7/2013
- Design Name:
- Module Name: LOGIC_UNIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity LOGIC_UNIT is
end LOGIC_UNIT;
architecture Behavioral of LOGIC_UNIT is
component AND4BIT is
end component;
component OR4BIT is
end component;
component NOT4BIT is
end component;
component NAND4BIT is
end component;
component NOR4BIT is
end component;
component XOR4BIT is
end component;
component XNOR4BIT is
end component;
component MUX8TO1 is

15 | P a g e
Z4
:
in
0);
Z5
:
in
0);
Z6
:
in
0);
Z7
:
in
0);
Z8
:
in
0);
Z : out
0);
SEL : in
0));
end component;
component MUX8TO14BIT is
Port ( Z1 : in
0);
Z2
:
in
0);
Z3
:
in
0);
Z4
:
in
0);
Z5
:
in
0);
Z6
:
in
0);
Z7
:
in
0);
Z8
:
in
0);
Z : out
0);
SEL : in
0));
end component;
signal Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8: STD_LOGIC_VECTOR (3 downto 0); begin
LOI0: AND4BIT port map (A, B, Z1); LOI1:
OR4BIT port map (A, B, Z2); LOI3: NOT4BIT
port map (A, Z3); LOI4: NOT4BIT port map (B,
Z4); LOI5: NAND4BIT port map (A, B, Z5);
LOI6: NOR4BIT port map (A, B, Z6); LOI7:
XOR4BIT port map (A, B, Z7);
LOI8: XNOR4BIT port map (A, B, Z => Z8);
LOI9: MUX8TO14BIT port map (Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z, SEL); end
Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 23:47:01 10/7/2013
- Design Name:
- Module Name: MUX2TO1 - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity MUX2TO1
i
s
Port ( Z1
:
in
0);
Z2
:
in
STD_LOGIC_VECT
OR
(3
downto
0
)
;
Z :
ou
t
STD_LOGIC_VECT
OR
(4
downto
0
)
;
SEL: in STD_LOGIC);
end MUX2TO1;
architecture Behavioral of MUX2TO1 is
begin
with SEL select
Z <= Z1 when '0',
'0' & Z2 when others;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 11:12:14 10/7/2013
- Design Name:
- Module Name: MUX8TO14BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
--use
UNISIM.VComponents.all;
entity MUX8TO14BIT is
Port ( Z1 : in
0);
Z2
:
in
0);
Z3
:
in
0);
Z4
:
in
0);
Z5
:
in
0);
Z6
:
in
0);
Z7
:
in
0);
Z8
:
in
0);
end MUX8TO14BIT;
architecture Behavioral of MUX8TO14BIT is
begin
with SEL select
Z <= Z1 when
"000", Z2
when "001",
Z3 when "010",
Z4 when "011",
Z5 when "100",
Z6 when "101",
Z7 when "110",
Z8 when others;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 23:44:21 10/7/2013
- Design Name:
- Module Name: MUX8TO1 - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity MUX8TO1 is
Port ( Z1 : in
0);
Z2
:
in
0);
Z3
:
in
0);
Z4
:
in
0);
Z5
:
in
0);
Z6
:
in
0);
Z7
:
in
0);
Z8
:
in
0);
end MUX8TO1;
architecture Behavioral of MUX8TO1 is
begin
with SEL select
Z <= Z1 when
"000", Z2
when "001",
Z3 when "010",
Z4 when "011",
Z5 when "100",
Z6 when "101",
Z7 when "110",
Z8 when "111",
Z1 when others;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 14:59:13 10/7/2013
- Design Name:
- Module Name: AND2BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity AND2BIT
i
s
Port ( a
:
in STD_LOGIC;
b
:
in STD_LOGIC;
z
:
out STD_LOGIC);
end AND2BIT;
architecture
Behavioral of AND2BIT
is
begin
z <= a and b;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 11:36:12 08/7/2013
- Design Name:
- Module Name: AND4BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity AND4BIT
i
s
Port ( a
:
in
0);
b
:
in
0);
z : out
0));
end AND4BIT;
architecture and4bitarch of AND4BIT is
component
AND2BIT PORT
(
a : in STD_LOGIC;
b : in
STD_LOGIC; z :
out STD_LOGIC
);
end component;
begin
A1: AND2BIT port map (a (0), b (0), z (0));
end and4bitarch;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 15:12:29 10/7/2013
- Design Name:
- Module Name: FOURBITADDER - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
--use
entity FOURBITADDER is
Port ( a
:
in
0);
b
:
in
0);
z
:
out
0));
end FOURBITADDER;
architecture Behavioral of FOURBITADDER is
signal c: std_logic_vector (4 downto
0); component FULLADDER is
Port ( a : in STD_LOGIC;
b :
i
n
STD_LOGIC
;
cin
:
i
n
STD_LOGI
C;
s :
o
u
t
STD_LOGI
C;
cout : out STD_LOGIC);
end component;
begin
FA0: FULLADDER port map (a (0), b (0), '0', z (0), c (1));
FA1: FULLADDER port map (a (1), b (1), c (1), z (1), c (2));
FA2: FULLADDER port map (a (2), b (2), c (2), z (2), c (3));
FA3: FULLADDER port map (a (3), b (3), c (3), z (3), z (4));
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 23:56:59 10/7/2013
- Design Name:
- Module Name: FOURBITSUBTRACTOR - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
--use
entity FOURBITSUBTRACTOR is
Port ( a
:
in
STD_LOGIC_VECTOR (3
downto
0)
;
b
:
in
STD_LOGIC_VECTOR (3
downto
0)
;
z: out
0));
end FOURBITSUBTRACTOR;
architecture
Behavioral of FOURBITSUBTRACTOR
is
signal bo: std_logic_vector (4 downto 0);
component FULLSUBTRACTOR is
b :
i
n
STD_LOGIC
;
bin
:
i
n
STD_LOGI
C;
z :
o
u
t
STD_LOGI
C;
bout : out STD_LOGIC);
end component;
begin
FS0: FULLSUBTRACTOR port map (a (0), b (0), '0', z (0), bo (1));
FS1: FULLSUBTRACTOR port map (a (1), b (1), bo (1), z (1), bo
(2)); FS2: FULLSUBTRACTOR port map (a (2), b (2), bo (2), z (2),
bo (3)); FS3: FULLSUBTRACTOR port map (a (3), b (3), bo (3), z
(3), z (4));
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 15:01:15 10/7/2013
- Design Name:
- Module Name: FULLADDER - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity FULLADDER is
Port ( a : in
STD_LOGIC
;
b
:
in
STD_LOGIC
;
cin : in
STD_LOGI
C;
s
:
out
STD_LOGI
C;
cout : out STD_LOGIC);
end FULLADDER;
architecture Behavioral of FULLADDER
is signal t1: STD_LOGIC;
signal t2: STD_LOGIC;
component AND2BIT is
port (
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component XOR2BIT is
port (
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component OR2BIT is
port (
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC);
end component;
begin
I0: XOR2BIT port map (a, b, t1);
I1: XOR2BIT port map (cin, t1, s);

I3: AND2BIT port map (a, b, t2);
I5: AND2BIT port map (cin, t3, t4);
I6: OR2BIT port map (t2, t4, cout);
end Behavioral;
24 | P a g e

---------------------------------------------------------------------------------
-
- Company:
- Engineer:
-
- Create Date: 15:01:15 10/7/2013
- Design Name:
- Module Name: FULLSUBTRACTOR - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
---------------------------------------------------------------------------------
-
library IEEE;
use
--library UNISIM;
--use
entity FULLSUBTRACTOR is
Port ( a
:
i
n STD_LOGIC;
b
:
i
n STD_LOGIC;
b
i
n
:
i
n STD_LOGIC;
z :
out STD_LOGIC;
bout : out
STD_LOGIC);
end
FULLSUBTRACTOR;
architecture Behavioral of FULLSUBTRACTOR
is signal t1: STD_LOGIC;
component AND2BIT
is port (
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component XOR2BIT
is port (
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC);
end component;
component OR2BIT
is port (
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC);

end component;
component NOT2BIT
is port (
a : in STD_LOGIC;
z : out STD_LOGIC);
end component;
begin
I1: XOR2BIT port map (bin, t1, z);
I3: AND2BIT port map (b, bin, t2);
I4: NOT2BIT port map (a, t3);
25 | P a g e

I5: AND2BIT port map (t3, b, t4);
I6: AND2BIT port map (t3, bin, t5);
I7: OR2BIT port map (t2, t5, t6);
I8: OR2BIT port map (t6, t4, bout);
end Behavioral;
26 | P a g e

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 15:00:23 10/7/2013
- Design Name:
- Module Name: NAND2BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity NAND2BIT is
Port ( a : in
STD_LOGIC
;
b
:
in
STD_LOGIC
;
z
:
out
STD_LOGIC
);
end NAND2BIT;
architecture Behavioral of NAND2BIT is
begin
z <= a nand b;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 11:36:12 08/7/2013
- Design Name:
- Module Name: NAND4BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity NAND4BIT is
Port ( a : in
0);
b
:
in
0);
z
:
out
0));
end NAND4BIT;
architecture nand4bitarch of NAND4BIT is
component NAND2BIT
PORT (
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out
STD_LOGIC);
end component;
begin
O1: NAND2BIT port map (a (0), b (0), z (0));
end nand4bitarch;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 15:00:23 10/7/2013
- Design Name:
- Module Name: NOR2BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity NOR2BIT
i
s
Port ( a
:
in STD_LOGIC;
b
:
in STD_LOGIC;
z
:
out STD_LOGIC);
end NOR2BIT;
architecture
Behavioral of NOR2BIT
is
begin
z <= a nor b;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 11:36:12 08/7/2013
- Design Name:
- Module Name: NOR4BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity NOR4BIT
i
s
Port ( a
:
in
0);
b
:
in
0);
z
:
out
0));
end NOR4BIT;
architecture nor4bitarch of NOR4BIT is
component
NOR2BIT PORT
(
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out
STD_LOGIC);
end component;
begin
O1: NOR2BIT port map (a (0), b (0), z (0));
end nor4bitarch;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 15:00:23 10/7/2013
- Design Name:
- Module Name: NOT2BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity NOT2BIT is
Port ( a
:
in STD_LOGIC;
z
:
out STD_LOGIC);
end NOT2BIT;
architecture
Behavioral of NOT2BIT
is
begin
z <= not a;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 11:36:12 08/7/2013
- Design Name:
- Module Name: NOT4BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity NOT4BIT is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC_VECTOR (3 downto 0));
end NOT4BIT;
architecture not4bitarch of NOT4BIT is
component
NOT2BIT PORT
(
a : in STD_LOGIC;
z : out
STD_LOGIC);
end component;
begin
N1: NOT2BIT port map (a (0), z (0));
end not4bitarch;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 14:59:53 10/7/2013
- Design Name:
- Module Name: OR2BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity OR2BIT is
b : in STD_LOGIC;
z : out STD_LOGIC);
end OR2BIT;
architecture Behavioral of OR2BIT is
begin
z <= a or b;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 11:36:12 08/7/2013
- Design Name:
- Module Name: OR4BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity OR4BIT is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC_VECTOR (3 downto 0));
end OR4BIT;
architecture or4bitarch of OR4BIT is
component
OR2BIT PORT
(
a : in STD_LOGIC;
b : in
STD_LOGIC; z :
out STD_LOGIC
);
end component;
begin
O1: OR2BIT port map (a (0), b (0), z (0));
end or4bitarch;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 15:00:23 10/7/2013
- Design Name:
- Module Name: XNOR2BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity XNOR2BIT is
Port ( a : in
STD_LOGIC
;
b
:
in
STD_LOGIC
;
z
:
out
STD_LOGIC
);
end XNOR2BIT;
architecture Behavioral of XNOR2BIT is
begin
z <= a xnor b;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 11:36:12 08/7/2013
- Design Name:
- Module Name: XNOR4BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity XNOR4BIT is
Port ( a : in
0);
b
:
in
0);
z
:
out
0));
end XNOR4BIT;
architecture xnor4bitarch of XNOR4BIT is
component XNOR2BIT
PORT (
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out
STD_LOGIC);
end component;
begin
O1: XNOR2BIT port map (a (0), b (0), z (0));
end xnor4bitarch;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 15:00:23 10/7/2013
- Design Name:
- Module Name: XOR2BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity XOR2BIT
i
s
Port ( a
:
in STD_LOGIC;
b
:
in STD_LOGIC;
z : out STD_LOGIC);
end XOR2BIT;
architecture
Behavioral of XOR2BIT
is
begin
z <= a xor b;
end Behavioral;

--------------------------------------------------------------------------------
--
- Company:
- Engineer:
-
- Create Date: 11:36:12 08/7/2013
- Design Name:
- Module Name: XOR4BIT - Behavioral
- Project Name:
- Target Devices:
- Tool versions:
- Description:
--
- Dependencies:
-
- Revision:
--
--------------------------------------------------------------------------------
--
library IEEE;
use
--library UNISIM;
entity XOR4BIT
i
s
Port ( a
:
in
0);
b
:
in
0);
z
:
out
0));
end XOR4BIT;
architecture xor4bitarch of XOR4BIT is
component
XOR2BIT PORT
(
a : in STD_LOGIC;
b : in STD_LOGIC;
z : out
STD_LOGIC);
end component;
begin
O1: XOR2BIT port map (a (0), b (0), z (0));
end xor4bitarch;

4_BIT_ALU

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