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DiagramsOS.pdf

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CHP 01
Basic Elements of OS
Instruction Execution
Instruction Cycle with Interrupts
Interrupt Processing
Interrupts
User
Program
WRITE
WRITE
WRITE
I/O
Program
I/O
Command
END
1
2
3
2
3
4
5
(a) No interrupts
= interrupt occurs d...
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DiagramsOS.pdf

  1. 1. CHP 01 Basic Elements of OS Instruction Execution
  2. 2. Instruction Cycle with Interrupts Interrupt Processing
  3. 3. Interrupts User Program WRITE WRITE WRITE I/O Program I/O Command END 1 2 3 2 3 4 5 (a) No interrupts = interrupt occurs during course of execution of user program User Program WRITE WRITE WRITE I/O Program I/O Command Interrupt Handler END 1 2a 2b 3a 3b 4 5 (b) Interrupts; short I/O wait User Program WRITE WRITE WRITE 1 (c) Interrupts; lo Figure 1.5 Program Flow of Control Without and With In User Program WRITE WRITE WRITE I/O Program I/O Command END 1 2 3 2 3 4 5 (a) No interrupts = interrupt occurs during course of execution of user program User Program WRITE WRITE WRITE I/O Program I/O Command Interrupt Handler END 1 2a 2b 3a 3b 4 5 (b) Interrupts; short I/O wait User Program WRITE WRITE WRITE 1 (c) Interrupts Figure 1.5 Program Flow of Control Without and With
  4. 4. Memory Hierarchy Cache Memory
  5. 5. CHP 02 The Operating System as a User/Computer Interface A view of operating system services
  6. 6. The Operating System as Resource Manager Typical process implementation
  7. 7. Key Elements of an Operating System for multiprogramming Simple Batch Processing System CHP 3
  8. 8. Process Control Block Two-State Process Model Queuing Diagram c
  9. 9. Five State Process Model Using Two Queues One Suspend State
  10. 10. Multiple Blocked Queues Two Suspend State
  11. 11. OS Control Tables Structure of Process image in Virtual Memory
  12. 12. CHP 04 Single/Multithreaded Single/Multithreaded Processes
  13. 13. Threads vs Processes Types of Parallelism (Data and Task)
  14. 14. ULT, KLT & Combined Relationships between ULT States and Process States
  15. 15. CHP 7 Addressing Requirements for a Process Hardware Support for Relation Process Control Block Program Data Stack Current top of stack Entry point to program Process control information Increasing address values Branch instruction Reference to data Figure 7.1 Addressing Requirements for a Process Process Control Block Program Data Stack Figure 7.8 Hardware Support for Relocation Comparator Interrupt to operating system Absolute address Process image in main memory Relative address Base Register Bounds Register Adder
  16. 16. CHP 8 Address Translation in a Paging System Use of a Translation Lookaside Buffer
  17. 17. Operation of Paging and Translation Lookaside Buffer

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