1. SAURAV HALDER
Curriculum Vitae
814 11th Avenue SE, Apt 305
Minneapolis, MN 55414
(+1) 612-404-9739
halde018@umn.edu
in.linkedin.com/in/sauravhalder
Graduate student specializing in VLSI seeking Full time opportunities in
Physical Design, ASIC Design, Circuit Design
Education
2015 Aug –
Present
University of Minnesota, Twin Cities, MSEE, Expected Graduation Year – 2016 (Dec), GPA 3.55/4.
Graduate coursework : VLSI Design(Fall ’15), Advanced Computer Architecture(Fall ’15), ASIC Design and Verification
(Spring ’16), Advanced VLSI Design (Spring ’16),
2010–2014 Meghnad Saha Institute of Technology,Kolkata , B-Tech, GPA 8.6/10.
Undergraduate coursework : Analog ELectronics, Basics of VLSI and ASIC, Digital Communication, Digital Logic
Design,Embedded Systems and RTOS, Digital Signal Processing, Wireless Communication
Technical skills
Languages C, C++ ,Verilog, Perl, Java, Skill, JavaScript
Tools and
Simulators
Matlab, Hspice, Cadence Virtuoso, CosmosScope, Mentor Graphics Calibre, Pspice, Tanner Eda,
Synopsys Vcs, SimpleScalar, Cacti
Experience
May 2016 –
Aug 16
Intel Corporation, Physical Verification Intern.
Part of the Runset Automation team working on leading edge technologies and tools
Worked on automation of flows and helped in development of runsets
Dec 2014 –
May 2015
Tata Consultancy Services, Assistant Systems Engineer - Trainee, .
Advanced training in Java concepts covering HTML, CSS, JSP, Servlets, Struts, Hibernate
Academic Projects
Spring 2016 Full Custom Design of 128kb 6T SRAM in 45nm technology node.
Design and implementation of SRAM (2048x64b=128kB) Macro using row circuitry and column circuitry, with
critical path timing analysis, Full chip DRC, LVS and parasitic extraction.
Clock gating, write assist (VDD=0.8V for write) and Sleep Circuitry (Vgnd=0.3V during sleep) employed
Fall 2015 Design of a 16-bit Ladner-Fischer Adder in 45nm technology node.
Full-custom design and implementation performed in Cadence Virtuoso and Synopsys HSPICE
Grid based standard cell layout technique used for power and area optimization of the design
2014 Study of Sub-Threshold Surface Potential for Channel and Gate Engineered MOSFETS.
Developed an analytical model for Sub-threshold surface potential in a Short Channel MOS transistor
Modelling the Sub-threshold surface potential for DHDMG MOSFET and comparison with other MOSFETs
Fall 2015 Ring Oscillator Design in 45nm technology node.
Layout Design and simulations of a 7 stage ring oscillator circuit with a Fan-Out of 4 at each stage
Spring 2016 Secure Hash Algorithm - 3 (SHA-3) Encryption Processor.
Design, development and verification of Verilog code for functionality, Synthesis, Timing and Area optimizations for
a Secure Hash Algorithm -3 (SHA-3) Processor
Fall 2015 Leakage Energy Minimisation in Cache.
Analysis of the reduction in leakage power of Cache structures at reduced supply voltage for sleepy blocks
Interests and Activities
Participated in National Science, Cyber and Mathematics Olympiads
Participated in Robotics in Inter-College Technical Fests
Captained the College Soccer team and School Cricket team