Resume of Ria Ghosh

1. Ria Ghosh
Ria.Ghosh@utdallas.edu |469-601-3977 | McCallum Blvd.-7777, Dallas, TX-75252
Work Authorization- F-1 Visa
https://www.linkedin.com/in/ria-ghosh-5ba96378
OBJECTIVE
Seeking Internship as a Computer and Design Engineer to utilize my Hardware Designing, Network Security, Analysis and
Debugging Skills.
EDUCATION GRADUATION
Master of Science, Computer Engineering Expected August 2018
The University of Texas at Dallas, Richardson, TX GPA-3.67
Bachelor of Engineering, Electronicsand Telecommunication May 2016
Bhilai Institute of Technology, Durg, India GPA-8.99/10
HARDWARE AND SOFTWARE SKILLS
 Hardware Programming Languages: VHDL, VERILOG, SYSTEM VERILOG
 Hardware Tools: FPGA, CPLD, PCB Design
 Software Tools: XILINX ISE, MODELSIM, VIVADO, EDA, ECLIPSE, MS OFFICE
 Software Programming Languages: C, C++, JAVA, SQL, PYTHON, MATLAB
 Operating Systems: WINDOWS XP/VISTA/8/10, LINUX
EXPIRIENCE
SUMMER INTERN- Vardhaman Edutech Pvt. Ltd, Bhilai, India Summer 2015
Designed and implemented modifications (power optimization & effective architecture) in complex circuits of LFSR and PUFs
using EDA tools through VHDL programming which were tested on FPGA and CPLD kits.
VOCATIONAL INTERN- Bharat Sanchar Nigam Ltd, Durg, India Summer 2014
Assisted Broadband Installation and collaborated in the designs of various Network Security Mechanisms need to be
established in concerned regions according to the requirement and specifications analysis.
PUBLICATION
Design and Analysisof a maximum length 5-Bit Parallel LFSR’ in the International Journal Of Innovative Research in
Computer and Communication Engineering, Vol-4, Issue-4, April 2016, ISSN-2320-9801.
ACADEMIC PROJECTS
Design and Comparative Analysisof the Performance of Arbiter and Butterfly different PUFsthrough implementation
on FPGA. Nov- Dec 2016
This team project involved efficiently choosing the least resource utilizing PUF architecture and analyzing to what extent the
similarly designed PUFs are unclonable by giving a series of challenges and monitoring their out on the FPGA.
Inserting Trojansin 8051 micro-controller design Sep-Oct 2016
Modified thealready provided 8051 VHDLcode todo malicious activity likemaskingStoreddataoftheRAM or usinga sequence
detector to corrupt the data that is being inputted so as to understand the hacker’s mindset and prevent hacks.
Building an Effective Batch Language Processor using LINUX Aug-Sep 2016
Built a tool that parses and executes a Batch File containing number of commands using XML and JAVA Programming.
Generating a Novel Cryptographic Sequence using a Power Optimized LFSR Jan-May 2016
CPLD implementation of a unique, modified key design of a LFSR for security purposes using Xilinx and Spartan 3E where the
power dissipation of the LFSR circuit was reduced by 30% using clock gating method.
CERTIFICATIONS AND EXTRA-CURICULARS
 Successfully completed the coursework and practical training for Intel IoT camp, Web Development and Cloud Computing.
 Student Worker at UTD Dining Services presently holding the position of the cashier and managing the payroll of employees.
 Expert Technical Author Certification by Ezine Articles.
 Volunteered as the Team Lead at the Dallas Diwali Fair, managing the team, assigning responsibilities and controlling the
huge crowd gathered at the Cotton Bowl Stadium for the smooth running of the cultural event starring celebrities.
 Member of the club Toastmasters International.
 Volunteered for the National Social Services, India as a member of the Women Empowerment Awareness group.