1. REBECCA HEBDA
15320 SW 144th Terrace · Tigard, OR 97224 · 503-407-0480 · Rebecca.Hebda1@gmail.com
Highly Adaptable Engineering Manager and Technical Contributor
Results-driven Engineering Manager who excels at delivering state of the art microprocessors and SOCs,
successfully motivating teams, and achieving program goals under accelerated schedules. Excellent
technical, analytical, and communication skills demonstrated by more than 20 years of experience in
management and technical roles.
KEY SKILLS AND COMPETENCIES
 Computer Architecture/U-Arch
 Program/Project Management
 SOC
 Microprocessors
 IP Development
 Personnel Management
 IP Integration
 Strategic Planning
 Synthesis/Place & Route
 Circuit Design
 Problem Solving
 Low Power Design
 Logic Implementation
 Physical Design/Layout
 Memory Technology
 System Verilog
 Semiconductors
 VLSI
KEY SUCCESSES
Intel Corporation
 Led the cross-team/cross-site execution of innovative on-package memory chip which provided the
required memory bandwidth and capacity to support Iris/Iris Pro Graphics on multiple products.
Motivated stakeholders from multiple organizations and in multiple geographies to meet aggressive
timelines and requirements.
 Key technical and management contributions to Intel CPUs from the Pentium IV through present day
chips.
 Inventor/Co-Inventor on 6 patents for novel methods of CPU machine state recovery after
mispredicted branches and other related areas. These innovative features enabled CPU cores to
guarantee functionally correct behavior while increasing performance.
PROFESSIONAL EXPERIENCE
SOC/CPU Development Engineering Manager, Intel Corporation, 2001-2002, 2004 – Present
 Execution Manager for multiple projects from definition through post-silicon. Established project
expectations and methodologies, defined project milestones, and tracked team progress. Motivated
and engaged contributors across multiple teams and sites to ensure positive results.
 Managed a team of 10-15 engineers in the IP integration and design implementation for leading edge
SOC designs. Role modeled strong collaboration by utilizing technical skills to solve problems and
help where needed to make sure deliverables were met.
 Directed development and implementation of key functional blocks on multiple generations of state of
the art microprocessors from initial definition through tape-in on many process generations. Functional
areas included instruction micro-sequencer, instruction pre-decode logic, memory order buffer, fuse,
and storage/communications.
 Supervised individual contributors working on varied tasks including architectural and micro-
architectural definition, RTL development, schematic implementation, logic synthesis, physical
implementation, design convergence, and post-silicon verification.
 Managed performance and worked with each direct report to assign tasks and develop unique
development plans to allow them to grow their careers in meaningful ways.
 Drove low power design initiatives and power convergence execution for several generations of micro-
processor designs. Implemented detailed per block power budgets and tracking to enable the team to

2. focus on the most critical areas. Successfully enabled significant Cdyn and leakage reduction
generation over generation.
Implementation Architect, Intel Corporation, 2002-2004
 Defined micro-architecture and logical implementation for functional blocks related to instruction
length decoding and instruction pre-decode logic and queue for CPU product.
 Analyzed critical paths and provided micro-architectural and design based solutions that would
simplify design convergence and limit area growth or pipeline flux.
 Studied performance and power benefits/costs of multiple features being proposed for inclusion in
design and determined the best options for the project.
 Created highly-praised micro-architectural specification documentation to provide the design
implementers with detailed requirements.
Design Engineer, Intel Corporation, 1995-2001
 Inventor/Co-Inventor on 6 patents for novel methods of machine state recovery after mispredicted
branches and related areas.
 Created behavioral and structural RTL models for the branch misprediction recovery logic for CPU
product. Generated basic test suite and verified functionality. Used code assertions and graphical
debuggers to identify and resolve functional issues.
 Studied performance results for multiple configurations and combinations of branch predictor size and
method to determine the best tradeoffs of performance vs area for implementation. Helped define the
predictor block sizes and multi-level branch prediction scheme.
 Implemented logical and physical netlists for multiple functional blocks using industry tools to hand
draw schematics and place cells for datapath blocks or to synthesize and place/route for the control
blocks. Verified that the designs met timing, power, quality, and other spec set by the project.
 Developed a test suite to identify and screen structural “stuck-at” failures for several memory and
functional design blocks.
EDUCATION
Bachelor of Science (BS), Computer and Electrical Engineering, Purdue University, 1995