1. Ravi Mahajan, 333 West Malibu Drive, Chandler, AZ 85248. Phone : (480)-491-4782 (Home), (480)-760-
5854 (Cell). Email: rvmahaja@gmail.com
Highly Qualified and Experienced Technologist with a consistent track record of
high profile leadership and technical successes
Fellow of IEEE
Fellow of ASME
Winner SEMI-THERM 2016 THERMI Award
Winner ASME 2016 Allan Kraus Thermal Management Medal
Winner 2015 Mahboob Khan Outstanding Industry Liaison Award
IEEE CPMT Society Distinguished Lecturer
Education: PhD Mechanical Engineering, Lehigh University, 1992
MS, Mechanical Engineering, University of Houston, 1987
BS, Mechanical Engineering, Bombay University, 1985
Current Position: Senior Principal Engineer, Assembly Pathfinding, Intel
Corporation
Key Intel Accomplishments:
 Lead Architect : Packaging Technology Architecture, Assembly & Test
Technology Development (ATTD), (2000-Present)
- Inventor of the Silicon Bridge the core idea behind Intel’s revolutionary
EMIB (Embedded Multi-Die Interconnect Bridge) Technology a major
breakthrough in high density interconnects for heterogeneous Multi Chip
Packaging
- First Principal Engineer selected in Assembly Technology
- Key Architect responsible for defining package architectures, technologies
and assembly processes for packaging silicon at the 90nm, 65nm, 45nm,
32nm, 22nm, 10nm & 7nm Moore’s Law nodes. A number of these features
are implemented in millions of microelectronics packages
- Former Leader, Packaging Strategic Research Segment, a focus team that
manages ~$1-2M in annual university research funding
- 18+ successful years as Scientific Technical Advisory Board Member and
Science Area Chair (2007-2009) for the Semi-Conductor Research
Corporation
 Group Manager : Thermal Mechanical Tools and Analysis (TMTA), Assembly
Technology Development, INTEL Corporation (1995-2000)
- Developed and managed a highly successful group of 12 Engineers, 9
Technicians and a Thermal-Mechanical Lab chartered to deliver detailed
thermal and mechanical characterization of Intel’s tactical and strategic
packaging solutions for current and future CPU’s

2. - Group has made a high level of contributions leading to numerous
successful package technology certifications for leading Intel CPUs and is
counted among the foremost technology groups in CPU packaging
- Group has contributed significantly to INTEL’s Intellectual Property
portfolio through numerous breakthrough patents
- Key technologies like Moiré, Micro-Moiré, Shadow/Fizeau Moiré, Digital
Image Correlation and Micro-Tensile testing developed by group members
to extremely high levels of sophistication and deployability often
representing true state of the art.
 Individual Contributor : Design Process Development
- Technical Leaderfor Thermal solution developmentfor a series of high-end
thermal solution developments
- Design Integrator (Mobile Products) : Led cross-functional team that
ensured comprehensive design development and deployment into High
Volume Manufacturing (HVM) of enclosure for the Mobile Mini-Cartridge
for Pentium II solutions for Mobile Computing
- Led cross-functional team that ensured design development and HVM
deploymentof the first thin socket along with the thermal enablingsolution
for the component Pentium II and Pentium II solutions for Mobile
Computing. Team was awarded a prestigious Rapid Synchronization
award for developing the mobile cartridge
- Resolved key reliability issues that have had a direct impact on INTEL
product line. Received internal commendations for contributions
 Technology Competency Team Leader: Leader of an INTEL wide cross-
functional team that owned defining the INTEL Roadmap for a key thermal
technology metrics
 Founding Editor of IATTJ (INTEL Assembly and Test Technology Journal), an
Intel internal journal that documents current accomplishments and future
challengesin Assembly & Test Technologies. Thisisa highly successfuljournal
has been in existence for 16+ years and is recognized within Intel as a source of
high qualitypeer reviewedstate of the art information on Assembly,Packaging
and Test Technologies. It provides a forum for Intel technologists in field of
packaging to present achievements that cannot be published in external
literature for confidentiality reasons.
 20 years of experience in evaluating patent applications and in driving
innovation initiatives within Intel.
Key Intel External Accomplishments:
 Secretary of the Electronics thrust in the Society for Experimental Mechanics
- Organized three conferences tracks
- Editor, Experimental/Numerical Methods in Electronic Packaging Vols. I & II
 Reviewer, ASME Journal of Electronic Packaging, ASME’s INTERPACK, SRC
TECHCON, IEEE Transactions of Advanced Packaging

3.  Intel Mentor and Scientific Technical Advisory Board Representative to SRC
(1995-2016); STAB and Science Area Committee Chair in early and late 2000
 Invited Speaker at IEEE Phoenix Chapter, IBTC, Therminic International
Conference (France), Design Process Conference (Hong Kong)
 In 2007 awarded the “IEEE Engineer of the year” by the IEEE Phoenix Chapter
for sustained excellence in delivering cost effective, roadmap based packaging
technologies.
 In 2007 Elected Fellow of the American Society of Mechanical Engineers in
recognition of his numerous contributions to the field of packaging in thermal
management and mechanical stress analysis.
 In May 2002, Elected Senior Member of the IEEE.
 In Nov 2011, Elected Fellow of IEEE for Contributions to Electronic Packaging
Technology and Thermal Management of Microprocessors
 Associate Editor for the IEEE Transactions on Advanced Packaging for 5+
years
 Editor in Chief –Special Topics, IEEE Transactions on Components, Packaging
and Manufacturing Technology
 Chair, Industrial Advisory Board, InterPACK 05-15
 Winner SRC’s 2015 Mahboob Khan Outstanding Industry Liaison/Associate
Award
 Winner SEMI-THERM 2016 THERMI Award
 Industrial Advisory Board, Material Science and Engineering, University of
Arizona
 External Advisory Board Member for PRISM (NNSA Center for Prediction of
Reliability, Integrity and Survivability of Microsystems), Purdue University
Keynote and Invited Speaker
 IEEE, Phoenix Chapter (1998)
 Asia and South Pacific-Design Automation Conference (1999),
Thermal/Mechanical Design & Design Automation for Packaging,
 Keynote Address THERMINIC (1998, 2002) on on key technical challenges in
thermal and mechanical packaging
 Key note Address ITHERM 2002 “Challenges in the Thermal Management of
Microprocessors”
 Invited Speaker, MARCO Workshop in 2004 on key challenges in thermal
management
 Invited Speaker, International Electronics Packaging Symposium on National
Trends on Small Scale Systems and Micro-electronics Packaging, 2004, co-
sponsored by GE Global Research and Binghamton University “Thermal
Challenges and Solution Strategies for Microprocessor Cooling”
 Plenary Keynote, Heat and Mass Transfer Conference, Guwahati, India 2006

4.  Invited Speaker, International Workshop on Thermal Design and Management
in Electronics, Bangalore India 2006
 Invited speaker, IEEE Custom Integrated Circuits Conference, San Jose, CA,
September 2006
 Invited speaker, MRS 2006 on Packaging Roadmaps and the Pb-free transition
 Invited Speaker, IEEE Phoenix Chapter, Arizona State University,
SEMITHERM 2014-2015
 Invited Speaker, U. Michigan, November 2015
 Keynote Speaker, 7th International Electronics Cooling Technology Workshop,
California, November 2015.
 Keynote Speaker, SEMITHERM 2016, Santa Clara March 2016
 Keynote Speaker, IMAPS 2016, Phoenix March 2016
 Chair, 2016 ASME InterPACK Workshop on Packaging
Significant Publications (Partial List)
1. Mekonnen, Y., Xie, J., Manusharow, M., and Mahajan, R., “Die-Package Co-
Design Challenges with Embedded Multi-Die Interconnect Bridge,” Intel
Design and Test Technology Conference, 2015.
2. Mahajan, R., Erdogan. F., Kilic, B., and Madenci, E., “Cracking of an
Orthotropic Substrate Reinforced by an Orthotropic Plate.,” International
Journal of Solids and Structures, 2003, Vol 40, n 23, pp. 6389-6415.
3. Taylor, S. A., Chen, K., and Mahajan, R., “Moisture Migration and Cracking in
Plastic Quad Flat Packages (PQFPs),” ASME Journal of Electronic Packaging,
1997, Vol 119, pp. 85-88.
4. Mahajan, R., and Erdogan, F., “The Crack Problem for an Orthotropic Half-
plane Stiffened by Elastic Films,” International Journal of Engineering Science,
1993, Vol 31, n. 3, pp.403-424.
5. Mahajan, R., and Voloshin, A. S., “Transient Stress Intensity Factors for
Thermally Loaded Edge-Cracked Plates,” Journal of Thermal Stresses, 1993,
Vol 16, pp. 197-207.
6. Hinderliter, G. S., Mahajan, R. V., and Voloshin, A. S., „A Least-Squares
Approach for Evaluating Stress Intensity Factors from Mixed-Mode Caustics,”
Engineering Fracture Mechanics, 1991, Vol 40, n 2, pp. 323-333.
7. Mahajan, R. V., and Ravi-Chandar, K., “An Experimental Investigation of
Mixed-Mode Fracture,” International Journal of Fracture, 1989, Vol 41, pp. 235-
252.
8. Torresola, J., Chiu, C., Chrysler, G., Grannes, D., Mahajan, R., and Prasher., R.,
“A Density Factor Approach to Representing Impact of On-Die Power Maps
on Thermal Management,” Submitted to IEEE Transactions on Advanced
Packaging.
9. Ioan Sauciuc, Greg Chrysler, Ravi Mahajan, Ravi Prasher “Spreading in Heat
Sink Base: Phase Change Systems or Solid Metal??”, Conference Proceeding
THERMES 2002, 13-16 Januray, 2002, Santa Fe, New Mexico.

5. 10. Ioan Sauciuc, Greg Chrysler, Ravi Mahajan, Michele Szleper, “Air Cooling
Extension - Limits and Novel Ideas for Desktop and Server, IMAPS Advanced
Technology Workshop, San Jose, Oct 24-26, 2002.
11. Ioan Sauciuc, Greg Chrysler, Ravi Mahajan, Michele Szleper “Air Cooling
Extension - Limits and Novel Ideas”, Intel Technology Symposium, August
2002, Seattle.
12. Ioan Sauciuc, Greg Chrysler, Ravi Mahajan, Ravi Prasher “Spreading in Heat
Sink Base: Phase Change Systems or Solid Metal??”, IEEE Special
Transactions on Components and Packaging Technologies, December 2002,
Volume 25, Number 4, page 621-629.
13. Ioan Sauciuc, Greg Chrysler, Ravi Mahajan, Michele Szleper “Air-cooling
Extension – Performance Limits for Processor Cooling Applications”-
Proceedings of the 19th SEMI-THERM, San Jose, California, USA, 2003.
14. Mahajan, Ravi, Nair, Raj, Wakharkar Vijay, Swan, Johanna, Tang, John,
Vandentop, Gilroy, “Emerging Directions For Packaging Technologies,” Intel
Technology Journal, Volume 6, Issue 2 Semiconductor Technology and
Manufacturing, 2nd Quarter, 2002.
http://developer.intel.com/technology/itj/2002/volume06issue02/index.htm
15. Mahajan, Ravi, Brown, Ken, and Atluri, Vasu, “The Evolution of
Microprocessor Packaging,” Intel Journal of Technology, 3rd Quarter, 2000,
http://developer.intel.com/technology/itj/q32000.htm
16. Atluri Vasudeva, Mahajan Ravi, Patel Priyavardhan, Mallik Debendra, Tang
John, Wakharkar Vijay, Chrysler Gregory, Chiu Chia-pin, Choksi Gaurang,
Viswanath Ram, “Critical Aspects of High-Performance Microprocessor
Packaging,” MRS Bulletin, January 2003, Volume 28, No 1, pp. 21-34.
17. Lin, S., Mahajan, R., De, V., and Banerjee, K., ”Analysis and Implications of IC
Cooling for Deep Nanometer Scale CMOS Technologies,” IEDM 2005.
18. Torresola, J., Chiu, C., Chrysler, G., Grannes, D., Mahajan, R., Prasher, R., and
Watwe, Abhay, “Density Factor Approach to Representing Impact of Die
Power Maps on Thermal Management,” IEEE Transactions on Advanced
Packaging, Vol 28., No. 4, November 2005, pp. 659-664.
19. Mahajan, R.; Chiu, C.; Chrysler, G.; “Cooling a Microprocessor Chip,”
Proceedings of the IEEE, Volume 94, Issue 8, Aug. 2006 Page(s):1476 - 1486
20. Kilic, B., Madenci, E., and Mahajan, R., “Crack Opening And Sliding With A
Contact Zone And Energy Release Rate In A Cohesive And An Interface Crack
By Hadamard-Type Integral Equations,” International Journal of Solids and
Structures, Volume 43, Issue 5, March 2006, pp. 1159-1188.
21. Shankar Krishnan, Suresh Garimella, Greg Chrysler, Ravi Mahajan, ”Towards
a Thermal Moore’s Law,” IEEE Transactions on Advanced Packaging, v. 30, n (4),
August 2007m pp. 462-474.
22. Ihtesham Chowdhury, KellyLofgreen,Gregory Chrysler, Sridhar Narasimhan,
Ravi Mahajan, David Koester, Randall Alley, Ravi Prasher, Rama

6. Venkatasubramanian, “On-chip cooling by superlattice-based thin-film
thermoelectrics,” Nature Nanotechnology 4, 235-238 (25 January 2009)
23. J. Liu, P. Kumar, I. Dutta, C. M. Nagaraj, R. Raj, M. Renavikar, R. Mahajan,
“Effect of Interfacial Layers on the Performance of Cu-In LiquidPhaseSintered
Composites as Thermal Interface and Interconnect Materials,” accepted for
presentation @ InterPACK’11, Portland Oregon, July 6-8, 2011
24. Z. Huang, P. Kumar, I. Dutta, J. H. L.Pang, R. Sidhu, M. Renavikar, R. Mahajan,
“High Strain Rate Fracture Behavior of Sn-Ag-Cu Solder Joints on Cu
Substrates,” accepted for presentation @ InterPACK’11, Portland Oregon, July
6-8, 2011
25. Ephraim Suhir, R. Mahajan, “Are Current Qualification Practices Adequate? –
A Novel Approach to Predicting and Improving Device Failure Rates” Printed
Circuit Design & Fab/Circuits Assembly, April 2011, Vol. 28 n (4), pp. 26-36.
26. Devender, R. J. Mehta, K. Lofgreen, R. Mahajan, M. Yamaguchi, T. Borca-
Tasciuc, G. Ramanath, “Effects of Chemical Intermixing on Electrical and
Thermal Contact Conductances at MetallizedBismuthand Antimony Telluride
Interfaces,” Journal of Vacuum Science & Technology A 33, (2015), pp. 020605.
27. Devender, K. Lofgreen, S. Devasenathipathy, J. Swan, R. Mahajan, T. Borca-
Tasciuc, G. Ramanath, “Enhanced interfacial thermal transport in pnictogen
tellurides metallized with a lead-free solder alloy” Journal of Vacuum Science &
Technology A 33, 060611 (2015); http://dx.doi.org/10.1116/1.4935446.
28. N. Badwe, R. Mahajan and K. Sieradzki, “Interfacial Fracture Strength and
Toughness of Copper/Epoxy-Resin Interfaces” Acta Materialia 103 (2016), 512-
518.
29. B. Smith, C. Hernandez, A. Tasooji, R. Mahajan, E. Prack, M. Branch-Kelly, K.
McGuinness, M. Pavlov, “Characterization Methodologies for Investigating
Surface Integrity in Microelectronics Packaging” TMS 2016 145th ANNUAL
MEETING & EXHIBITION. WINNER 3rd Place for BestPoster out of 92 posters
presented.
30. S. Klein, A. Aleksov, V. Subramanian, R. Dias, P. Malatkar, R. Mahajan,
“Mechanical Testing for Stretchable Electronics,” ASME 2016 International
Mechanical Engineering Congress and Exposition, IMECE 2016, Nov 11-17,
2016, Phoenix Arizona.
Patent Portfolio
Granted
6,706,562 Electronic assembly with high capacity thermal spreader and
methods of manufacture
6,908,845 Integrated circuit die and an electronic assembly having a three-
dimensional interconnection scheme
7,576,432 Using external radiators with electroosmotic pumps for cooling
integrated circuits
6,981,849 Electro-osmotic pumps and micro-channels

7. 7,126,822 Electronic packages, assemblies, and systems with fluid cooling
7,882,624 Method of forming electronic package having fluid-conducting
channel
6,903,929 Two-phase cooling utilizing micro-channel heat exchangers and
channeled heat sink
6,934,154 Micro-channel heat exchangers and spreaders
7,508,671 A computer system having controlled cooling
7,279,796 Microelectronic die having a thermoelectric module
7,539,016 Electromagnetically-actuated micro-pump for liquid metal alloy
enclosed in cavity with flexible sidewalls
7,764,499 Electromagnetically-actuated micro-pump for liquid metal alloy
7,851,905 Microelectronic package and method of cooling an interconnect
feature in same
8,064,224 Microelectronic package containing silicon patches for high density
interconnects , and method of manufacturing same
9,136,236 Localized high density substrate routing
8,441,809 Microelectronic package containing silicon connecting region for
high density interconnects, and method of manufacturing same
8,609,532 Magnetically sintered conductive via
8,939,347 Magnetic intermetallic compound interconnect
8,313,958 Magnetic microelectronic device attachment
5,936,304 C4 package die backside coating
6,043,560 Thermal interface thickness control for a microprocessor
6,191,475 Substrate for reducing electromagnetic interference and enclosure
6,011,696 Cartridge and an enclosure for a semiconductor package
6,043,983 EMI containment for microprocessor core mounted on a card using
surface mounted clips
9,076,882 Methods for high precision microelectronic die integration
6,490,166 Integrated circuit package having a substrate vent hole
RE44,629 Process for assembling an integrated circuit package having a
substrate vent hole
Patents Pending
• Magnetic intermetallic compound interconnect
• Methods for high precision microelectronic die integration
• Electromagnetic interference shield for semiconductor chip packages
• Die-to-die bonding and associated package configurations
• Passive components in vias in a stacked integrated circuit package
• Flexible computing fabric
• Photovoltaic window
• Adaptive exoskeleton, devices and methods for controlling the same
• System and method for providing tactile feedback
• Integrated circuit package with embedded bridge
• Flexible microelectronic assembly and method

8. • Electro-magnetic interference (EMI) shielding techniques and
configurations