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semidynamics
RISC-V Summit 2020
SemiDynamics
High Bandwidth
Vector-capable
RISC-V Cores
Roger Espasa, PhD
CEO
1
semidynamics
RISC-V Summit 2020
semidynamics
SemiDynamics
• European Based RISC-V IP Provider
• HQ in Barcelona
• Founded 2016
• Proud participant in the European Processor Initiative (EPI)
• RISC-V Acceleration core supplied by SemiDynamics
2
semidynamics
RISC-V Summit 2020
semidynamics
Introducing 2 new RISC-V IP Cores
November 11, 2020 3
Available for licensing
2-wide In-Order 2-wide Out-of-Order
Gazzillion Misses™
AVISPADO 220 ATREVIDO 220
Gazzillion Misses™
RISC-V Vector Support RISC-V Vector Support
semidynamics
RISC-V Summit 2020
semidynamics
What’s a high bandwidth core?
4
semidynamics
RISC-V Summit 2020
semidynamics
A core with lots of outstanding
memory requests
5
semidynamics
RISC-V Summit 2020
semidynamics
6
A core with Gazzillion Misses™
semidynamics
RISC-V Summit 2020
semidynamics
Example: Gathering Sparse Data with 8 outstanding requests
7
while ( condition )
load a[index[i]]
load b[i]
compute
store c[i]
Original Program
top:
load index[i] -> x5
load (x5) -> x6
load b[i] -> x7
compute x6, x7 -> x8
store x8 -> c[i]
loop to top
Stylized Assembly Code
Wait “L” cycles, where L=memory latency, L > 100
Time →
After the 8th miss, stop until first miss comes back
(loop will be unrolled ~4 times)
Now send the 9th miss to
the memory system
semidynamics
RISC-V Summit 2020
semidynamics
Example: Gathering Sparse Data with Gazzillion Misses™
8
while ( condition )
load a[index[i]]
load b[i]
compute
store c[i]
Original Program
top:
load index[i] -> x5
load (x5) -> x6
load b[i] -> x7
compute x6, x7 -> x8
store x8 -> c[i]
loop to top
Stylized Assembly Code
Wait time greatly reduced
Time →
After the 8th miss, continue sending requests!
semidynamics
RISC-V Summit 2020
semidynamics
Another Example: Vector Gather with Gazzillion Misses™
• Consider the RISC-V “vlxei32.v” gather instruction
• Assume VLEN=512b
• Instruction will request 16 addresses (assume to different cache lines)
9
Time →
After the 8th miss, continue sending requests!
At larger VLEN or smaller indices, even larger gains
semidynamics
RISC-V Summit 2020
semidynamics
Comparison to other cores
10
1 2 3 4 5 6
Retirement/Issue Width
20
40
60
80
100
120
140
POWER9
SMT4
16
12
IceLake
64+
Avispado
128+
Atrevido
A76
20
RISC-V Boom
10
Outstanding
Misses
U8
SCR7
AX25
semidynamics
RISC-V Summit 2020
semidynamics
Gazzillion Misses™ good for…
11
Recommendation
Systems
MLP
AE
CNN
RNN LSTM GRU
DRL
Key-Value
Stores
Sparse
Data / HPC
Machine
Learning
semidynamics
RISC-V Summit 2020
semidynamics
Gazzillion Misses™ good for SoCs…
12
With Limited
SRAM/Cache
Core
Bus Ctrl
D
D
R
Accel
High Bandwidth/
Streaming
With Vector Units
Vector
Unit
Vector
Unit
D
D
R
semidynamics
RISC-V Summit 2020
semidynamics
Avispado Core Details
13
semidynamics
RISC-V Summit 2020
semidynamics
AVISPADO 220
RISCV64GCV
14
INT
FP
MIQ
GIQ
VFIQ
64B 8B
PC I$
ITLB
BP
Queue Dec
2i
D$
DTLB Align
vAGU
Gazzillion
Coherent
Interface
• SV48
• 16KB I$
• Decodes upcoming V1.0 vector spec
• 32KB D$
• Full hardware support for unaligned accesses
• Coherent (TL, ACE, CHI)
Available for licensing
semidynamics
RISC-V Summit 2020
semidynamics
Customizable upon request
• Cache Size / Associativity
• Coherent Interface
• In-flight instructions
15
semidynamics
RISC-V Summit 2020
Introducing
SemiDynamics’
RISC-V Vector Processing Unit
16
November 11, 2020 SemiDynamics Confidential
semidynamics
RISC-V Summit 2020
semidynamics
SemiDynamics’ VPU
• Implements the RISC-V Vector 1.0 Specification
• Including lmul, segmented loads
• No vector atomics currently
• Ready for OOO support
• Renaming
• Customizable settings
• VLEN = vreg size = from 128b to 4096b
• Data path width = from 128b to 512b
• Fast cross-lane network for slide/rgather/compress/expand
November 11, 2020 17
Available for licensing 3 months after V-spec freeze
SemiDynamics Confidential
semidynamics
RISC-V Summit 2020
semidynamics
VPU Block Diagram
• Lane based organization
• Full cache-line bus from D-cache
• Units per lane
• FMA
• INT
• DIV
• XL: Cross-lane (rgather, …)
• Full masking support
November 11, 2020 18
From D-cache
SemiDynamics Confidential
Lane0
XL Network
VREG0
A B C
Bypass
Lane1 LaneN-1
FMA INT XL
DIV
Available for licensing 3 months after V-spec freeze
semidynamics
RISC-V Summit 2020
semidynamics
AVISPADO 220 with VPU
RISCV64GCV
19
INT
FP
MIQ
GIQ
VFIQ
64B 8B
PC I$
ITLB
BP
Queue Dec
2i
D$
DTLB Align
vAGU
Gazzillion
Coherent
Interface
• SV48
• 16KB I$
• Decodes upcoming V1.0 vector spec
• 32KB D$
• Full hardware support for unaligned accesses
• Coherent (TL, ACE, CHI)
• Vector Memory (vle, vlse, vlxe, vse, …) processed by MIQ/LSU
VPU
November 11, 2020 SemiDynamics Confidential
Available for licensing 3 months after V-spec freeze
semidynamics
RISC-V Summit 2020
semidynamics
Atrevido Core Details
20
semidynamics
RISC-V Summit 2020
semidynamics
ATREVIDO 220
RISCV64GCV
21
INT
FP
MIQ
GIQ
VFIQ
64B 8B
PC I$
ITLB
BP
Queue Ren
2i
D$
DTLB Align
vAGU
Gazzillion
Coherent
Interface
• SV48
• 16KB I$
• Decodes upcoming V1.0 vector spec
• 32KB D$
• Full hardware support for unaligned accesses
• Coherent (TL, ACE, CHI)
Dec
Available for licensing
• Larger BP
• Renaming
• Retirement Logic
semidynamics
RISC-V Summit 2020
semidynamics
ATREVIDO 220 with VPU
RISCV64GCV
22
INT
FP
MIQ
GIQ
VFIQ
64B 8B
PC I$
ITLB
BP
Queue Ren
2i
D$
DTLB Align
vAGU
Gazzillion
Coherent
Interface
• SV48
• 16KB I$
• Decodes upcoming V1.0 vector spec
• 32KB D$
• Full hardware support for unaligned accesses
• Coherent (TL, ACE, CHI)
Dec
• Larger BP
• Renaming
• Retirement Logic
Available for licensing 3 months after V-spec freeze
VPU
semidynamics
RISC-V Summit 2020
semidynamics
Summary
23
IP cores available for licensing
2-wide In-Order 2-wide Out-of-Order
Gazzillion Misses™
AVISPADO 220 ATREVIDO 220
Gazzillion Misses™
VPU 1.0 VPU 1.0
semidynamics
RISC-V Summit 2020
semidynamics
Thank you!
www.semidynamics.com
info@semidynamics.com
24

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Semi dynamics high bandwidth vector capable RISC-V cores