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Do SI Simulation, Also for Carbon Reduction

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Keynote Speech in 2015 ANSYS Taiwan Technical Conference

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Do SI Simulation, Also for Carbon Reduction

  1. 1. Do SI Simulation, Also for Carbon Reduction (做模擬,也可以做環保) Nansen Chen, Ph.D. MediaTek Inc., Taiwan
  2. 2. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Use Smartphones to Do...  WW 1st tri-cluster w/ 10-core CPU (helio X20) 1 Dual-cluster Tri-cluster
  3. 3. 6/11/2015Copyright © MediaTek Inc. All rights reserved. And with CrossMount TM to Share…  Converge all platforms for sharing hardware and software resources together. 2 It’s more GREEN! HFSS Q3D SIwave Designer
  4. 4. 6/11/2015Copyright © MediaTek Inc. All rights reserved. If some is good, more is better… 3  Global LCD TV shipment > 200 Mu. @ year [1].
  5. 5. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Why 2-Gb/s/pin DRAM access 4 Super Hi-Vision (7,680x4,320 = 33 Mpixels) 4K2K Full HD Sources: officialandroid.blogspot.tw; benevo.pixnet.net
  6. 6. 6/11/2015Copyright © MediaTek Inc. All rights reserved. 4-layer or 2-layer PCB 5 4-layer PCB 2-layer PCB Ref. plane 4.3 mils   58 mils  The 8-layer PCB (509 x 473 mm2) was certificated as 186.44 Kg CO2 equivalent (Source: Unimicron).
  7. 7. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Why Carbon Reduction 6  Except cost, we hope less global climate change! Sources: pansci.tw; eric0703.pentaxfans.net 2015年3月25日:日月潭「九蛙疊像」16年首度洗澎澎。 2009年8月7-8日莫拉克颱風:最高降雨量3060 mm,台東縣知本溫泉區「金帥飯店」倒塌。
  8. 8. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Why Carbon Reduction (cont’d) 7  Fabless chip suppliers should take more responsibility?
  9. 9. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Carbon Footprint 8  AUO's 32’’ LCD TV: WW 1st carbon footprint label.
  10. 10. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Carbon Footprint (cont’d) 9  AUO: a TV is turned on 5 hours/day [2]. 28% 60%
  11. 11. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Channel Design 10 DDR3 FBGA96 package in HFSS Controller package + PCB in SIwave  Chip to chip co-simulation methodology  I/O netlists + Full channel S-parameters.
  12. 12. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Channel Design (cont’d) 11  Thickness (mm)  2.5-layer PCB: 2-layer PCB + a graphite layer  Conductivity: graphite (7x104 S/m) < copper (5.8x107 S/m)
  13. 13. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Channel Design (cont’d) 12 Top layer Bottom layer  Channel-1 design using the 2.5-layer PCB.  Channel-2 design using the traditional 2-layer PCB.
  14. 14. 6/11/2015Copyright © MediaTek Inc. All rights reserved. System Performance 13  Electrical performance in frequency domain (DQ1)
  15. 15. 6/11/2015Copyright © MediaTek Inc. All rights reserved. System Performance (cont’d) 14 -3.0 -2.0 -1.0 0.0 Ch-1 Ch-2 dB/GHz Max. I.L. Rate in 2 GHz -9.0 -6.0 -3.0 0.0 Ch-1 Ch-2 dB Max. R.L. in 2 GHz 0.92 dB 4.35 dB  Electrical performance in frequency domain (DQ1)
  16. 16. 6/11/2015Copyright © MediaTek Inc. All rights reserved. 15 System Performance (cont’d)  Read-2000 (Byte-0): Channel-1, DRAM ODI = 48 Ω.  iVddr from LDO: ODT=40/60/120/160 Ω = 173/131/118/110 mA. ODT = 40 Ω ODT = 60 Ω ODT = 160 Ω ODT = 120 Ω Differential DQSOverlapped 1-byte signals
  17. 17. 6/11/2015Copyright © MediaTek Inc. All rights reserved. 16 System Performance (cont’d)  Read-2000 (Byte-0): Channel-2, DRAM ODI = 48 Ω.  iVddr from LDO: ODT= 40/60/120/160 Ω = 170/127/114/106 mA. ODT = 40 Ω ODT = 60 Ω ODT = 160 Ω ODT = 120 Ω Differential DQSOverlapped 1-byte signals
  18. 18. 6/11/2015Copyright © MediaTek Inc. All rights reserved. 17 System Performance (cont’d)  Write-2000 (Byte-0): Channel-1, DRAM ODT = 120 Ω.  iVddr from LDO: ODI = 65/51/45/40 Ω = 119/133/140/147 mA. ODI = 65 Ω ODI = 51 Ω ODI = 45 Ω ODI = 40 Ω Differential DQSOverlapped 1-byte signals
  19. 19. 6/11/2015Copyright © MediaTek Inc. All rights reserved. 18 System Performance (cont’d)  Write-2000 (Byte-0): Channel-2, DRAM ODT = 120 Ω.  iVddr from LDO: ODI = 65/51/45/40 Ω = 118/131/137/145 mA. ODI = 65 Ω ODI = 51 Ω ODI = 45 Ω ODI = 40 Ω Differential DQSOverlapped 1-byte signals
  20. 20. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Power Consumption  Calculation based on same performance 19 Channel-1 Channel-2 RE-2000 160 Ω/48 Ω 60 Ω/40 Ω ODT/ODI = Channel-1 Channel-2 WR-2000 OFF/65 Ω 60 Ω/40 Ω ODT/ODI =
  21. 21. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Power Consumption (cont’d)  Average Current Consumption (CCAVG) per byte 20 0 50 100 150 Ch-1 Ch-2 mA/byte RE-2000 (CCAVG) 0 50 100 150 200 Ch-1 Ch-2 mA/byte WR-2000 (CCAVG)
  22. 22. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Power Consumption (cont’d) 21 Wh635.1day)(perhr-55.1byte-4 2 8920   VmA  A 32-bit data access at 2 Gb/s (w/ 1.5 V I/O power) 台灣歷年電力排放係數:公斤 CO2/度(cfp.epa.gov.tw) 2005 2006 2007 2008 2009 2010 2011 2012 0.559 0.564 0.559 0.557 0.543 0.535 0.536 0.532 1.635 Wh x 0.532 Kg CO2/Kwh x 200 M(units)/3 ≈ 58 t. CO2
  23. 23. 6/11/2015Copyright © MediaTek Inc. All rights reserved. Conclusions 22  Recommend JEDEC STD to add two more weak drive strengths for further power savings [3].  The proposed 2.5-layer PCB can achieve DDR3- 2000 speed with low-carbon settings.
  24. 24. 6/11/2015Copyright © MediaTek Inc. All rights reserved. 23
  25. 25. 6/11/2015Copyright © MediaTek Inc. All rights reserved. References [1] T. Lo, “LCD TV market trends and outsourcing strategies for 2013,” DIGITIMES Research. (2012, Dec.). [Online]. Available: http://www.digitimes.com/ [2] C. Lee, “The Low-Carbon Future: Taiwanese Industry Goes Green,” Taiwan Panorama, Vol. 35, No. 4 (2010), pp. 6-35. [3] DDR3 SDRAM Specification, JEDEC Std. JESD79-3F, 2012. 24
  26. 26. www.mediatek.com

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