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Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes


     Design And Implemation Of An Enhanced Dds Based Digital
            Modulator For Multiple Modulation Schemes
                                           Manoj Kollam1, S.A.S.Krishna Chaithanya2, Nagaraju kommu3
                                               Lecturer, Dept. of E & C,GSSSIETW, Mysore, India1,
                                               Dept. of E & C2,3 ,VNR VJIET2,3, Hyderabad, india2,3
                                                                mkollam@gmail.com

Abstract— This paper deals with the design & implementation of a               frequency resolution, and operation over a broad spectrum
Digital Modulator based on the FPGA. The design is implemented using
                                                                               of frequencies.
the Enhanced Direct Digital Synthesis (DDS) Technology. The basic
DDS architecture is enhanced with the minimum hardware to facilitate
the complete system level support for different kinds of Modulations with           In this paper, a new Digital Modulator with multiple
minimal FPGA resources. The size of the ROM look up is reduced by              modulation capabilities has been proposed. The paper
using the mapping logic. The Design meets the present Software Define
                                                                               mainly focuses on enhancing the existing DDS architecture
Radio (SDR) requirements and provides the user selection for desired
modulation technique to be used. The VHDL programming language is              with minimal hardware elements to provide a single unit
used for modeling the hardware blocks for powerful and flexible                solution and for supporting different modulations. It avoids
programming and to avoid VHDL code generation tools. The design is             the users to have a modulator for each modulation. The
simulated in the ModelSim Simulation Tool and Synthesized using the
                                                                               design is made completely using the VHDL programming
Xilinx ISE Synthesis Tool. The architecture is implemented on the
SPARTAN-3A FPGA from Xilinx Family in the SPARTAN-3A                           for avoiding VHDL code generation tools for powerful and
evaluation board. The experimental results obtained demonstrate the            flexible programming and synthesized on the SPARTAN-
usefulness of the proposed system in terms of the system resources, its        3A FPGA. The Design meets the present Software Define
capabilities for design, validation and practical implementation purposes.
                                                                               Radio (SDR) requirements and provides the user selection
Keywords- Field Programmable Gate Array (FPGA), Direct Digital                 for desired modulation technique to be used.
Synthesis (DDS), Software Define Radio (SDR), ModelSim, Xilinx ISE.                 This paper is organized into 5 sections. In section 1, a
                                                                               brief description of digital modulation technology’s present
     I.         INTRODUCTION                                                   situation and problems are introduced and a new method of
                                                                               designing a Digital Modulator for supporting multiple
     Modulation is the process of conveying the information                    modulation schemes is proposed. In section 2, DDS
over the medium. Digital modulation represents the transfer                    Technology, A new method of using the enhanced DDS
of the digital bit stream from the transmitter to the                          technology to design digital modulator is proposed. In
receiver(s) via the analogue informational channel (the                        section 3, the Architecture of the designed Digital
medium).                                                                       Modulator, its construction, operations of various modules
     During the modulation process the informational signal                    used in the architecture are described in detail. In section 4,
modifies one or more carrier parameters. Usually, the carrier                  the analysis of the simulation and synthesis results for the
is a sine wave, defined by amplitude, frequency and phase.                     statistical data about the design correctness and the amount
Depending on the carrier parameter being changed, there are                    of device resource consumption of the design and
three basic types of modulation techniques Binary                              programming the FPGA device. In the final section, the
Amplitude Shift Keying (BASK), Binary Frequency Shift                          advantages of using enhanced DDS technology to design
Keying (FSK) and Binary Phase Shift Keying (BPSK). All                         digital modulator for multiple modulation techniques have
the other known modulation techniques are derived from                         been discussed.
these three basic types.
                                                                                   II.      DDS TECHNOLOGY
     The Digital Modulators often require a means to
generate sinusoidal waveforms according to strong                                   Digital modulator is based on DDS technology and
requirements regarding amplitude, phase or frequency from                      realized on FPGA. Direct digital synthesis (DDS) is a
electronic systems. Both the accuracy and the stability of the                 method of producing an analog waveform usually a sine
generated signals must usually be addressed, particularly                      wave, by generating a time-varying signal in digital form
when the parameters of interest have to be modified in real                    and then performing a digital-to-analog conversion. The
time.                                                                          ability to accurately produce and control waveforms of
     The Direct Digital Synthesis (DDS) of signals is a                        various frequencies and a profile has become a key
current alternative to classical analog methods based on the                   requirement common to a number of industries. DDS
use of Phase-Locked Loops providing various advantages                         technique is rapidly gaining acceptance for solving
[2]. As operations within a DDS device are primarily digital,                  frequency (or waveform) generation requirements in both
it can offer fast switching between output frequencies, fine                   communications and industrial applications because single-



                           International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011
                                                                             102
Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes

chip IC devices can generate programmable analog output
waveforms simply and with high resolution and accuracy.
    Furthermore, the continual improvements in both
process technology and design have resulted in cost and
power consumption levels that were previously unthinkably
low [].

                 A.DDS Modulation Capabilities
    It is simple to add modulation capabilities to the DDS,
because the DDS is a digital signal processing device. In the
DDS it is possible to modulate numerically all three                         As the vector rotates around the wheel, a corresponding
waveform parameters.                                                    output sinewave is being generated. One revolution of the
                  S(n) = A(n) sin(2π (ΔP (n) + P(n)))                   vector around the phase wheel, at a constant speed, results
    Where A(n) is the amplitude modulation, ΔP (n) is the               in one complete cycle of the output sinewave[3].
frequency modulation, and P (n) is the phase modulation.
All known modulation techniques use one, two or all three                    The phase accumulator is utilized to provide the
basic modulation types simultaneously. Consequently any                 equivalent of the vector’s linear rotation around the phase
known waveform can be synthesized from these three basic                wheel. The contents of the phase accumulator correspond to
types within the Nyquist band limitations in the DDS [1].               the points on the cycle of the output sinewave. The number
                                                                        of discrete phase points contained in the “wheel” is
                   B.DDS Operating Principle                            determined by the resolution, N, of the phase accumulator.
         The Principle of operation of the DDS can be                   The output of the phase accumulator is linear and cannot
understood with the Fig.1. The Frequency tuning input is                directly be used to generate a sinewave or any other
converted into the angular phase by Phase Accumulator and               waveform except a ramp.
is converted into the sinewave amplitudes by                                 Therefore, a phase-to-amplitude lookup table is used to
Amplitude/Sine Conv. Algorithm. This is applied to the D/A              convert a truncated version of the phase accumulator’s
for analog sinewave output [3].                                         instantaneous output value into the sinewave amplitude
                                                                        information that is presented to the D/A converter

                                                                            The relationship between the length of the phase
               Fig.1: Signal flow through DDS architecture              accumulator and output frequency form the basic tuning
                                                                        equation for DDS architecture:
    To understand this basic function, visualize the sine                                 FOUT = (M (REFCLK)) /2N
                                                                        Where:
                                                                              FOUT: Output frequency of the DDS
                                                                              M: Binary tuning word
                                                                              REFCLK: Internal reference clock frequency
                                                                              N: The length in bits of the phase accumulator.
                                                                                 Changes to the value of M in the DDS architecture
                                                                        result in immediate and phase-continuous changes in the
                                                                        output frequency.


                                                                             C. Algorithm of Rom Compression

wave oscillation as a vector rotating around a phase circle as               In the technology of DDS, the conversion of phase to
shown in the Fig.2. The number of discrete phase points                 amplitude is realized by look-up table ROM. Its content is
contained in the wheel is determined by the resolution of the           stored in ROM, phase value is the address of ROM and its
phase accumulator, which determines the tuning resolution               output is the amplitude of conversion. When the number of
of the DDS. Each designated point on the phase wheel                    phase is big, it is not only increasing quantization error of
corresponds to the equivalent point on a cycle of a sine                amplitude, but also the rapid increase of the required
waveform.                                                               hardware [1]. So the algorithm of ROM compression based
                                                                        on the symmetry of sine wave is adopted in the system.
                                                                              Sine wave of one period is divided into 4 Quarters:
                                                                        [0~π/2], [π/2~π], [π~3π/2], [3π/2~2π] as shown in the Fig.3.
                       Fig.2: Digital Phase Wheel.
                                                                        Using the symmetrical nature of a sinewave and utilizing the
                                                                        mapping logic to synthesize a complete sinewave cycle

                        International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011
                                                                   103
Design And Implemation Of An Enhanced Dds B
                              I                              Based Digital Mo
                                                                            odulator For Mult
                                                                                            tiple Modulation S
                                                                                                             Schemes

from ¼ cycle of data from the phase accumulator. T
f                          m                            The           supplie all other com
                                                                             es               mponents with the clock inp and the
                                                                                                              h              put
phase-to-amplit
p             tude lookup taable generates all the necessa
                                                         ary          other f the Data buffer, the each bit of the user data is
                                                                             for                               h
d by reading forward then back through the lookup tab
data         g                                          ble.          transmi itted at high of clock2.
                                                                                             f
Fig shows the symmetric nature of the sine wave. Th
F                           n                            his               Th Resetter sup
                                                                             he                pplies all othe components with the
                                                                                                               er             s
method saves n
m            nearly three-fou
                            urths resources
                                          s.                          reset innput taking fr  rom the exter   rnal push butt ton on the
                                                                      board.
                                                                           Th Modulation Control Unit is the major p of the
                                                                             he                                               part
                                                                      architeccture which co ontains the reg gisters to store the Center
                                                                      frequen ncy, Frequency Deviation, P
                                                                                               y               Phase Deviatio Center
                                                                                                                              on,
                                                                      Phase and Amplitud parameters It supplies the other
                                                                                              de              s.
                                                                      hardwa with these values and se the control register to
                                                                             are                             ets
                                                                      facilitat different mo
                                                                               te            odulation Techniques.
                                                                           Thhe Frequency Shifter ad
                                                                                             y                dds/subtracts the two
                                                                      frequen ncies i.e. center frequency an frequency d
                                                                                                              nd             deviation to
                                                                      get the mark and spac frequencies during FSK. I all other
                                                                                               ce                             In
                                                                      cases it acts as a simp buffer and transmits the data to the
                                                                              t                ple
                                                                      success block.
                                                                              sive
                                                                           Th Phase Accum
                                                                             he               mulator will ke  eeps on incremmenting the
                   Fig.3: Symm
                             metric Nature of Sin Wave.
                                                ne                    instantaaneous frequen  ncies with the phase offset to get the
                                                                                                              e
                                                                      instantaaneous phase v values
                                                                           Th Phase Shift adds/subtra
                                                                             he               ter             acts the two f frequencies
        III.      THE ARCH
                         HITECTURE O DIGITAL
                                   OF                                 i.e. cennter frequency and frequen deviation to get the
                                                                                             y               ncy
                          MODULATOR
                          M        R                                  mark an space phase during PSK In all other cases it acts
                                                                               nd             es             K.
                                                                      as a simmple buffer an transmits th data to the successive
                                                                                             nd               he
                                                                      block.
                                                                           Th Phase to Amplitude conv
                                                                             he                               verts these insstantaneous
                                                                      values into the sine w  wave amplitud for transmi
                                                                                                             des             ission. It is
                                                                      just a lo up table co
                                                                              ook            ontaining ampl   litude values.
                                                                           Th Amplitude Multiplier m
                                                                             he                             multiplies the a  amplitudes
                                                                      stored i internal regi
                                                                               in              isters with the sine wave ins stantaneous
                                                                      amplitu udes to get the logic high an low amplitu
                                                                                             e               nd              udes during
                                                                      ASK m  modulation and acts as a buffe in all other c
                                                                                                              er             cases.
                                                                           All the blocks o the design c be Enabled/Disabled
                                                                                             of               can
                                                                      depend ding on the control register v    value for facillitating the
                                                                      selected type of modu
                                                                              d              ulation.
                                                                            To reduce the number of complex additions and
                                                                              o
                                                                      multipl lications booth algorithm is used for imp
                                                                                             h’s                              plementing
                                                                      this moodule.

                                                                                      A. Boot Multiplica
                                                                                            th’s       ation Procedure

                                                                           Th First step is making the Bo
                                                                             he                         ooth table and the second
               Fig.4: Digital Mod
                                dulator Architectu
                                                 ure
                                                                      step is implementing the Booth’s Al
                                                                                                        lgorithm.

                                                                      Step 1: Making the Boooth table
    The Digita Modulator architecture i shown in t
                al                          is              the                1. Take two number        rs multiplierr(X) and
Fig.4. It cons
F              sists of Phase Accumulator and Phase-to-
                             e              r
                                                                                   multipli
                                                                                          icand (Y).
Amplitude Con
A               nverter which are the basic constructs of a
                                           c               f
                                                                               2. From th two number pick the nu
                                                                                          he             rs,          umber with
DDS and other digital hardw
D               r           ware added to support differe   ent
                                                                                   the smaallest difference between a series of
modulations in the architectur
m                            re.
                                                                                   consecu
                                                                                         utive numbers, and make it a mmultiplier.
    The overa functionality of the mo
               all                          odulator can be                    3. Take the 2’s complem of Y and call it –Y
                                                                                           e            ment
understood wit respect to fu
u              th            unctionality of each element of
                                           f
                                                                               4. Load the X value in th table.
                                                                                                        he
th design.
 he
                                                                               5. Load th previous first least signifi
                                                                                         he                           icant bit of
    The Clock Generator tak the input f
               k             kes           from the extern  nal                    X for X-1 value
crystal oscillato from the bo
c               or            oard and mult tiplies or divid
                                                           des
                                                                               6. Load 0 in U and V ro which wil have the
                                                                                                         ows           ll
th clock. Here the It genera two clocks one is (Clock
 he            e            ates           s               k1)
                                                                                   product of X and Y at the end of ope
                                                                                                                      eration.
System Clock, for the entire operation of the system a
S                            e             f               and

                        Internat
                               tional Journal of S
                                                 Smart Sensors and Ad Hoc Networ (IJSSAN) Volu
                                                                               rks           ume-1, Issue-1, 20
                                                                                                              011
                                                                  104
Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes

         7.    Make the number of rows for each cycle as the
               number of bits.

Step 2: Booth Algorithm

     Booth algorithm requires examination of the multiplier
bits, and shifting of the partial product. Prior to the shifting,
the multiplicand may be added to partial product, subtracted
from the partial product, or left unchanged according to the
following rules:
     1. Look at the first least significant bits of the
          multiplier “X”, and the previous least significant
          bits of the multiplier “X - 1”.
               a. 0 0 Shift only
                                                                             Fig.5: Simulation Result during Reset Condition
               b. 1 1 Shift only.
               c. 0 1 Add Y to U, and shift
               d. 1 0 Subtract Y from U, and shift or add                    The Fig.5 shows the status of all the units in the Digital
                    (-Y) to U and shift                                 Modulator design during the reset condition. At this
     2. Take U & V together and shift arithmetic right shift            situation all the components are initialized to zero.
          which preserves the sign bit of 2’s complement
          number. Thus a positive number remains positive,
          and a negative number remains negative.
     3. Shift X circular right shifts because this will
          prevent us from using two registers for the X value.
     4. Repeat the same steps until the total cycles are
          completed.

    The advantage of using the booth’s algorithm is it
reduces the number of complex multiplications and
additions from a regular multiplication, which in turn
reduces the utilization of number of FPGA resources.

         IV.       ANALYSIS OF SIMULATION AND
                       SYNTHEIS RESULTS

     To verify the design, the overall system is simulated in                       Fig.6: Simulation Result during BASK Condition
the ModelSim environment and synthesized in the Xilinx
Environment. The modules simulated and synthesized are                       During the BASK condition the signal contains two
Modulation Control Unit, Frequency Adder, Clock                         amplitudes depending upon the data input. This is shown in
Generator, Phase Shifter, Phase Accumulator, Phase-to-                  the Fig.6. The simulation result contains the status of
Amplitude Converter, Amplitude Multiplier, Resetter and                 different components and signals during ASK condition.
the overall system.
      The simulation and synthesis results of the digital
modulator architectural are shown below with respect to
different modulation techniques.




                                                                                    Fig.7: Simulation Result during BPSK Condition




                        International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011
                                                                    105
Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes

    During the BPSK condition the signal contains two
phases depending upon the data input. This is shown in the
Fig.7. The simulation result contains the status of different
components and signals during BPSK condition.




                                                                                Fig.10: Receive Console showing the SPI Programming Successful.
                                                                             The Spartan-3A Evaluation board from Avnet is used
                                                                        for implementing the Design because of its low cost. It
                                                                        contains a 128 Mbits of SPI Flash memory that can be used
                                                                        to store a FPGA bit file. With the SPI memory programmed,
                                                                        that FPGA will configure itself on power-up, when the
          Fig.8: Simulation Result during BFSK Condition                MODE jumpers are set for Master SPI mode[7].
                                                                             The Fig.10 shows the Receive console showing the SPI
     During the BFSK condition the signal contains two                  Programming Successful.
frequencies depending upon the data input. This is shown in
the Fig.8. The simulation result contains the status of                        V.        CONCLUSIONS
different components and signals during BFSK condition.
                                                                             In this paper, the Enhanced DDS based Digital
                                                                        Modulator is designed using VHDL. The design shows the
                                                                        Digital Modulator architecture is developed with the
                                                                        enhanced DDS architecture and provides more modulation
                                                                        capabilities with the utilization of less hardware resources.
                                                                        The design provides single unit solution for different
                                                                        Modulation Techniques, with the user choice of Modulation
                                                                        type to be used. Presently, the modulations implemented are
                                                                        BASK, BPSK, BFSK.
                                                                             The simulation results show that the design principles
                                                                        are correct and effective. After synthesizing the system we
                                                                        got the statistical data about the number of input-output
                Fig.9: Device Utilization Summary                       buffers, the number of registers, number of flip-flops and
                                                                        latches used in the usage of FPGA tool. These results show
    In the Device Utilization Summary, we can see the
                                                                        that the utilization of the device resources is quite minimal.
number of flip flops, I/Os and BUFGMUX utilized in the
                                                                        The final bit file is programmed into the Xilinx XC3S400A
design. This is shown in the Fig.9.
                                                                        FPGA device.
     A. Programming the Design into SPI Flash Memory of                       ACKNOWLEDGEMENTS
            SPARTAN-3A FPGA Evaluation kit
                                                                            It is a pleasure to recognize the many individual who
                                                                        have helped me in completing this technical paper. I
                                                                        sincerely express heartiest thanks to my guide
                                                                        Mrs V.Padmaja for all the technical guidance,
                                                                        encouragement and support throughout this process.

                                                                        REFERENCES

                                                                        [1]    Natural Science Foundation of Jiangxi Province of China with
                                                                               Grand 2008GZS0028,”Design and Implement of Digital Modulator
                                                                               Based on Improved DDS Technology and DSP Builder”.
                                                                        [2]    “FPGA-Based Design, Implementation, and Evaluation of Digital
                                                                               Sinusoidal Generators”, 2008 IEEE.


                        International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011
                                                                   106
Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes

[3]   Analog Devices, A technical tutorial on digital signal synthesis,
      1999.
[4]   Wang Meng,Wang Ning(2006). “The Implementation of DDS with
      FPGA by Less Resources Used” .Microelectronics And
      Computer,Vol.23, No.8, pp.181-183.
[5]   Digital frequency synthesis demystified / Bar-Giora Goldberg, 1999.
[6]   Digital modulation techniques / Fuqin Xiong,2000.
[7]   Xilinx Spartan-3A Evaluation Kit User Guide,Rev 2.1.




                           International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011
                                                                            107

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Design and implemation of an enhanced dds based digital

  • 1. Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes Manoj Kollam1, S.A.S.Krishna Chaithanya2, Nagaraju kommu3 Lecturer, Dept. of E & C,GSSSIETW, Mysore, India1, Dept. of E & C2,3 ,VNR VJIET2,3, Hyderabad, india2,3 mkollam@gmail.com Abstract— This paper deals with the design & implementation of a frequency resolution, and operation over a broad spectrum Digital Modulator based on the FPGA. The design is implemented using of frequencies. the Enhanced Direct Digital Synthesis (DDS) Technology. The basic DDS architecture is enhanced with the minimum hardware to facilitate the complete system level support for different kinds of Modulations with In this paper, a new Digital Modulator with multiple minimal FPGA resources. The size of the ROM look up is reduced by modulation capabilities has been proposed. The paper using the mapping logic. The Design meets the present Software Define mainly focuses on enhancing the existing DDS architecture Radio (SDR) requirements and provides the user selection for desired modulation technique to be used. The VHDL programming language is with minimal hardware elements to provide a single unit used for modeling the hardware blocks for powerful and flexible solution and for supporting different modulations. It avoids programming and to avoid VHDL code generation tools. The design is the users to have a modulator for each modulation. The simulated in the ModelSim Simulation Tool and Synthesized using the design is made completely using the VHDL programming Xilinx ISE Synthesis Tool. The architecture is implemented on the SPARTAN-3A FPGA from Xilinx Family in the SPARTAN-3A for avoiding VHDL code generation tools for powerful and evaluation board. The experimental results obtained demonstrate the flexible programming and synthesized on the SPARTAN- usefulness of the proposed system in terms of the system resources, its 3A FPGA. The Design meets the present Software Define capabilities for design, validation and practical implementation purposes. Radio (SDR) requirements and provides the user selection Keywords- Field Programmable Gate Array (FPGA), Direct Digital for desired modulation technique to be used. Synthesis (DDS), Software Define Radio (SDR), ModelSim, Xilinx ISE. This paper is organized into 5 sections. In section 1, a brief description of digital modulation technology’s present I. INTRODUCTION situation and problems are introduced and a new method of designing a Digital Modulator for supporting multiple Modulation is the process of conveying the information modulation schemes is proposed. In section 2, DDS over the medium. Digital modulation represents the transfer Technology, A new method of using the enhanced DDS of the digital bit stream from the transmitter to the technology to design digital modulator is proposed. In receiver(s) via the analogue informational channel (the section 3, the Architecture of the designed Digital medium). Modulator, its construction, operations of various modules During the modulation process the informational signal used in the architecture are described in detail. In section 4, modifies one or more carrier parameters. Usually, the carrier the analysis of the simulation and synthesis results for the is a sine wave, defined by amplitude, frequency and phase. statistical data about the design correctness and the amount Depending on the carrier parameter being changed, there are of device resource consumption of the design and three basic types of modulation techniques Binary programming the FPGA device. In the final section, the Amplitude Shift Keying (BASK), Binary Frequency Shift advantages of using enhanced DDS technology to design Keying (FSK) and Binary Phase Shift Keying (BPSK). All digital modulator for multiple modulation techniques have the other known modulation techniques are derived from been discussed. these three basic types. II. DDS TECHNOLOGY The Digital Modulators often require a means to generate sinusoidal waveforms according to strong Digital modulator is based on DDS technology and requirements regarding amplitude, phase or frequency from realized on FPGA. Direct digital synthesis (DDS) is a electronic systems. Both the accuracy and the stability of the method of producing an analog waveform usually a sine generated signals must usually be addressed, particularly wave, by generating a time-varying signal in digital form when the parameters of interest have to be modified in real and then performing a digital-to-analog conversion. The time. ability to accurately produce and control waveforms of The Direct Digital Synthesis (DDS) of signals is a various frequencies and a profile has become a key current alternative to classical analog methods based on the requirement common to a number of industries. DDS use of Phase-Locked Loops providing various advantages technique is rapidly gaining acceptance for solving [2]. As operations within a DDS device are primarily digital, frequency (or waveform) generation requirements in both it can offer fast switching between output frequencies, fine communications and industrial applications because single- International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011 102
  • 2. Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes chip IC devices can generate programmable analog output waveforms simply and with high resolution and accuracy. Furthermore, the continual improvements in both process technology and design have resulted in cost and power consumption levels that were previously unthinkably low []. A.DDS Modulation Capabilities It is simple to add modulation capabilities to the DDS, because the DDS is a digital signal processing device. In the DDS it is possible to modulate numerically all three As the vector rotates around the wheel, a corresponding waveform parameters. output sinewave is being generated. One revolution of the S(n) = A(n) sin(2π (ΔP (n) + P(n))) vector around the phase wheel, at a constant speed, results Where A(n) is the amplitude modulation, ΔP (n) is the in one complete cycle of the output sinewave[3]. frequency modulation, and P (n) is the phase modulation. All known modulation techniques use one, two or all three The phase accumulator is utilized to provide the basic modulation types simultaneously. Consequently any equivalent of the vector’s linear rotation around the phase known waveform can be synthesized from these three basic wheel. The contents of the phase accumulator correspond to types within the Nyquist band limitations in the DDS [1]. the points on the cycle of the output sinewave. The number of discrete phase points contained in the “wheel” is B.DDS Operating Principle determined by the resolution, N, of the phase accumulator. The Principle of operation of the DDS can be The output of the phase accumulator is linear and cannot understood with the Fig.1. The Frequency tuning input is directly be used to generate a sinewave or any other converted into the angular phase by Phase Accumulator and waveform except a ramp. is converted into the sinewave amplitudes by Therefore, a phase-to-amplitude lookup table is used to Amplitude/Sine Conv. Algorithm. This is applied to the D/A convert a truncated version of the phase accumulator’s for analog sinewave output [3]. instantaneous output value into the sinewave amplitude information that is presented to the D/A converter The relationship between the length of the phase Fig.1: Signal flow through DDS architecture accumulator and output frequency form the basic tuning equation for DDS architecture: To understand this basic function, visualize the sine FOUT = (M (REFCLK)) /2N Where: FOUT: Output frequency of the DDS M: Binary tuning word REFCLK: Internal reference clock frequency N: The length in bits of the phase accumulator. Changes to the value of M in the DDS architecture result in immediate and phase-continuous changes in the output frequency. C. Algorithm of Rom Compression wave oscillation as a vector rotating around a phase circle as In the technology of DDS, the conversion of phase to shown in the Fig.2. The number of discrete phase points amplitude is realized by look-up table ROM. Its content is contained in the wheel is determined by the resolution of the stored in ROM, phase value is the address of ROM and its phase accumulator, which determines the tuning resolution output is the amplitude of conversion. When the number of of the DDS. Each designated point on the phase wheel phase is big, it is not only increasing quantization error of corresponds to the equivalent point on a cycle of a sine amplitude, but also the rapid increase of the required waveform. hardware [1]. So the algorithm of ROM compression based on the symmetry of sine wave is adopted in the system. Sine wave of one period is divided into 4 Quarters: [0~π/2], [π/2~π], [π~3π/2], [3π/2~2π] as shown in the Fig.3. Fig.2: Digital Phase Wheel. Using the symmetrical nature of a sinewave and utilizing the mapping logic to synthesize a complete sinewave cycle International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011 103
  • 3. Design And Implemation Of An Enhanced Dds B I Based Digital Mo odulator For Mult tiple Modulation S Schemes from ¼ cycle of data from the phase accumulator. T f m The supplie all other com es mponents with the clock inp and the h put phase-to-amplit p tude lookup taable generates all the necessa ary other f the Data buffer, the each bit of the user data is for h d by reading forward then back through the lookup tab data g ble. transmi itted at high of clock2. f Fig shows the symmetric nature of the sine wave. Th F n his Th Resetter sup he pplies all othe components with the er s method saves n m nearly three-fou urths resources s. reset innput taking fr rom the exter rnal push butt ton on the board. Th Modulation Control Unit is the major p of the he part architeccture which co ontains the reg gisters to store the Center frequen ncy, Frequency Deviation, P y Phase Deviatio Center on, Phase and Amplitud parameters It supplies the other de s. hardwa with these values and se the control register to are ets facilitat different mo te odulation Techniques. Thhe Frequency Shifter ad y dds/subtracts the two frequen ncies i.e. center frequency an frequency d nd deviation to get the mark and spac frequencies during FSK. I all other ce In cases it acts as a simp buffer and transmits the data to the t ple success block. sive Th Phase Accum he mulator will ke eeps on incremmenting the Fig.3: Symm metric Nature of Sin Wave. ne instantaaneous frequen ncies with the phase offset to get the e instantaaneous phase v values Th Phase Shift adds/subtra he ter acts the two f frequencies III. THE ARCH HITECTURE O DIGITAL OF i.e. cennter frequency and frequen deviation to get the y ncy MODULATOR M R mark an space phase during PSK In all other cases it acts nd es K. as a simmple buffer an transmits th data to the successive nd he block. Th Phase to Amplitude conv he verts these insstantaneous values into the sine w wave amplitud for transmi des ission. It is just a lo up table co ook ontaining ampl litude values. Th Amplitude Multiplier m he multiplies the a amplitudes stored i internal regi in isters with the sine wave ins stantaneous amplitu udes to get the logic high an low amplitu e nd udes during ASK m modulation and acts as a buffe in all other c er cases. All the blocks o the design c be Enabled/Disabled of can depend ding on the control register v value for facillitating the selected type of modu d ulation. To reduce the number of complex additions and o multipl lications booth algorithm is used for imp h’s plementing this moodule. A. Boot Multiplica th’s ation Procedure Th First step is making the Bo he ooth table and the second Fig.4: Digital Mod dulator Architectu ure step is implementing the Booth’s Al lgorithm. Step 1: Making the Boooth table The Digita Modulator architecture i shown in t al is the 1. Take two number rs multiplierr(X) and Fig.4. It cons F sists of Phase Accumulator and Phase-to- e r multipli icand (Y). Amplitude Con A nverter which are the basic constructs of a c f 2. From th two number pick the nu he rs, umber with DDS and other digital hardw D r ware added to support differe ent the smaallest difference between a series of modulations in the architectur m re. consecu utive numbers, and make it a mmultiplier. The overa functionality of the mo all odulator can be 3. Take the 2’s complem of Y and call it –Y e ment understood wit respect to fu u th unctionality of each element of f 4. Load the X value in th table. he th design. he 5. Load th previous first least signifi he icant bit of The Clock Generator tak the input f k kes from the extern nal X for X-1 value crystal oscillato from the bo c or oard and mult tiplies or divid des 6. Load 0 in U and V ro which wil have the ows ll th clock. Here the It genera two clocks one is (Clock he e ates s k1) product of X and Y at the end of ope eration. System Clock, for the entire operation of the system a S e f and Internat tional Journal of S Smart Sensors and Ad Hoc Networ (IJSSAN) Volu rks ume-1, Issue-1, 20 011 104
  • 4. Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes 7. Make the number of rows for each cycle as the number of bits. Step 2: Booth Algorithm Booth algorithm requires examination of the multiplier bits, and shifting of the partial product. Prior to the shifting, the multiplicand may be added to partial product, subtracted from the partial product, or left unchanged according to the following rules: 1. Look at the first least significant bits of the multiplier “X”, and the previous least significant bits of the multiplier “X - 1”. a. 0 0 Shift only Fig.5: Simulation Result during Reset Condition b. 1 1 Shift only. c. 0 1 Add Y to U, and shift d. 1 0 Subtract Y from U, and shift or add The Fig.5 shows the status of all the units in the Digital (-Y) to U and shift Modulator design during the reset condition. At this 2. Take U & V together and shift arithmetic right shift situation all the components are initialized to zero. which preserves the sign bit of 2’s complement number. Thus a positive number remains positive, and a negative number remains negative. 3. Shift X circular right shifts because this will prevent us from using two registers for the X value. 4. Repeat the same steps until the total cycles are completed. The advantage of using the booth’s algorithm is it reduces the number of complex multiplications and additions from a regular multiplication, which in turn reduces the utilization of number of FPGA resources. IV. ANALYSIS OF SIMULATION AND SYNTHEIS RESULTS To verify the design, the overall system is simulated in Fig.6: Simulation Result during BASK Condition the ModelSim environment and synthesized in the Xilinx Environment. The modules simulated and synthesized are During the BASK condition the signal contains two Modulation Control Unit, Frequency Adder, Clock amplitudes depending upon the data input. This is shown in Generator, Phase Shifter, Phase Accumulator, Phase-to- the Fig.6. The simulation result contains the status of Amplitude Converter, Amplitude Multiplier, Resetter and different components and signals during ASK condition. the overall system. The simulation and synthesis results of the digital modulator architectural are shown below with respect to different modulation techniques. Fig.7: Simulation Result during BPSK Condition International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011 105
  • 5. Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes During the BPSK condition the signal contains two phases depending upon the data input. This is shown in the Fig.7. The simulation result contains the status of different components and signals during BPSK condition. Fig.10: Receive Console showing the SPI Programming Successful. The Spartan-3A Evaluation board from Avnet is used for implementing the Design because of its low cost. It contains a 128 Mbits of SPI Flash memory that can be used to store a FPGA bit file. With the SPI memory programmed, that FPGA will configure itself on power-up, when the Fig.8: Simulation Result during BFSK Condition MODE jumpers are set for Master SPI mode[7]. The Fig.10 shows the Receive console showing the SPI During the BFSK condition the signal contains two Programming Successful. frequencies depending upon the data input. This is shown in the Fig.8. The simulation result contains the status of V. CONCLUSIONS different components and signals during BFSK condition. In this paper, the Enhanced DDS based Digital Modulator is designed using VHDL. The design shows the Digital Modulator architecture is developed with the enhanced DDS architecture and provides more modulation capabilities with the utilization of less hardware resources. The design provides single unit solution for different Modulation Techniques, with the user choice of Modulation type to be used. Presently, the modulations implemented are BASK, BPSK, BFSK. The simulation results show that the design principles are correct and effective. After synthesizing the system we got the statistical data about the number of input-output Fig.9: Device Utilization Summary buffers, the number of registers, number of flip-flops and latches used in the usage of FPGA tool. These results show In the Device Utilization Summary, we can see the that the utilization of the device resources is quite minimal. number of flip flops, I/Os and BUFGMUX utilized in the The final bit file is programmed into the Xilinx XC3S400A design. This is shown in the Fig.9. FPGA device. A. Programming the Design into SPI Flash Memory of ACKNOWLEDGEMENTS SPARTAN-3A FPGA Evaluation kit It is a pleasure to recognize the many individual who have helped me in completing this technical paper. I sincerely express heartiest thanks to my guide Mrs V.Padmaja for all the technical guidance, encouragement and support throughout this process. REFERENCES [1] Natural Science Foundation of Jiangxi Province of China with Grand 2008GZS0028,”Design and Implement of Digital Modulator Based on Improved DDS Technology and DSP Builder”. [2] “FPGA-Based Design, Implementation, and Evaluation of Digital Sinusoidal Generators”, 2008 IEEE. International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011 106
  • 6. Design And Implemation Of An Enhanced Dds Based Digital Modulator For Multiple Modulation Schemes [3] Analog Devices, A technical tutorial on digital signal synthesis, 1999. [4] Wang Meng,Wang Ning(2006). “The Implementation of DDS with FPGA by Less Resources Used” .Microelectronics And Computer,Vol.23, No.8, pp.181-183. [5] Digital frequency synthesis demystified / Bar-Giora Goldberg, 1999. [6] Digital modulation techniques / Fuqin Xiong,2000. [7] Xilinx Spartan-3A Evaluation Kit User Guide,Rev 2.1. International Journal of Smart Sensors and Ad Hoc Networks (IJSSAN) Volume-1, Issue-1, 2011 107