1. KONDALA RAO KOTTU
Phone no: (503)853-4008 Email id: er.kondalarao@gmail.com
SUMMARY
• Product Development Engineer with 3 years' experience in high volume SoC test engineering and
characterization.
• Experience in handling ATE test equipment for wafer and package level for device characterization.
• In depth knowledge of semiconductor manufacturing process and test methodology.
• Experience in yield management and binning strategies.
• Knowledge in performing statistical analysis on high volume data using JMP and Excel.
• Ability to setup DOE's to define root cause of failure mechanisms.
• Ability to work with oscilloscope and logic analyzer for device debug.
• Solid understanding in Bench correlations, guard band methodologies, Adaptive kill strategies and
statistics associated with test limit definitions.
• Flexible and versatile to adapt to a new environment and ability to multitasking and work independently.
WORK EXPERIENCE
SoC Product Development Engineer in Intel Corporation August 2015 – Present
• Development of test program flows, working with the module owners and senior test program
architecture PDE to build test program from definition, through integration and validation, to release in
HVM environment.
• Performing evaluation, development, and debug of new test methods and methodologies
• Statistical analysis of tested parameters and working with internal teams to define optimal sort/class test
pass/fail criteria on wafer/package level.
• Provide content debug support, working with module/content owners on the ATE tester platform
• Data analysis and deployment of solutions to improve test coverage, yield, TTR, hardware capacity, and
other product health indicators
• Keen attention to details, with a conscious focus towards efficiency and convergence via sort/class test
methodologies, standardization, and proliferation of best practices within and across product segments
• Strong participation and active contribution to global working groups dedicated to identifying and
meeting current and future test challenges.
• Supported test engineering teams with test program release activities.
SoC Debug Intern in Intel Corporation June 2014 – July 2015
• Supported USB type C enabling and debug for customers for Power delivery.
• Responsible for regression testing on Atom powered Android tablets for performance related issues
on HW/SW level.
• Key contribution in whitelisting Intel Based tablet on Chromecast. Designed test content for
Chromecast whitelisting.
• Automated pre-work test suite using UI Automation technique in Python for customer workshops.
• Key contributions in 3P audio enabling on Atom SoC ecosystem.
• Integrated and tested Modem firmware switching tool on Baytrail AndroidPlatform.
• Monitored Performance metrics by running CPU, GPU benchmarks across the different platforms for
Tablets based on Intel Processor.
• Good Knowledge on CPU C states and P states.
Kindle Debug Associate in Amazon Development Centre India. Aug 2012-July 2013
• Responsible to replicate and root the issues encountered by the end customer in application or digital
content on Fire Tablet with Android OS and report the logs to the respective Hardware/Software
team for a resolution and triage the resolution or patch build to see the issue is resolved.

2. EDUCATION
Portland State University, Portland, OR
Masters in Electronics and Computer Engineering
Jawaharlal Nehru Technological University
Bachelors in Electronics and Communication Engineering
COURSE WORK
Microprocessor System Design. Digital Integrated Circuits.
Computer Architecture. Low Power IC design.
Formal Verification of HW/SW Systems. ASIC: Modelling and Synthesis.
TECHNICAL SKILLS
Programming Languages : C,C++.
Scripting Languages : Perl, Python
Analytical Tools : Excel, JMP
Hardware Languages : Verilog, VHDL.
Operating Systems : Android, MAC OS, Linux, Windows.