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What is a timer ?
At a high level, a timer is just a “Counter” register that counts up or down automatically.
A Counter can be used to keep track of time. It can increment/decrement a count register based on a
clock and to check if the count has reached some value and trigger an action.
17 Peripherals
Timers generally have a resolution of 8 or 16 or 32 Bits.
So a 8 bit timer is 8Bits wide so capable of holding value within 0-255. But this register has a magical
property ! Its value increases/decreases automatically at a predefined rate (supplied by user).
This is the timer clock. And this operation does not need CPU’s attention.
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HOW TO COUNT…
Up: the timer starts at zero, then counts up until it hits some maximum value.
The maximum value is stored in a special register called a compare register.
The maximum value can be the largest value the timer register can hold (like 0xFF for 1Byte Counter) or some
arbitrary value.
Down: the timer starts at some value you set and counts down until it reaches zero.
Up/Down: the timer counts up until it reaches the value in the compare register, and then counts
down until it reaches zero.
12
Counter register
External
source
Oscillator
Counter/Timer
COUT
0
1
Flag
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Timer used to …
timer will produce a regular output with the same accuracy as the input clock.
This output could be used to generate a periodic interrupt like a real-time
operating system (RTOS) timer tick.
provide a baud rate clock to a UART.
drive any device that requires a regular pulse.
Delay generating
Counting
Wave-form generating
Capturing
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Timer Infra Structure
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If we want to calculate 1ms
CLK Oscillator = 24 MHz
Timer clock= (24 / 12) MHz = 2 MHz
Timer cycle = 500ns
Delay count = delay time / cycle time
1 ms / 500 ns = 2000
Counter numbers= (216 -1)-2000 = 63535
Set Count value 63535 to max or set count 0 >
2000-1
16-bit counterClk 16
External
Clock
2x1 mux
Mode
Controller
irq
Reset
Cnt
÷
Clock Divider
External Input Pin
Output
pin
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Watchdog (WDOG)
WDOG is intended to be used to apply a reset to a system in the event of a
failure.
WDOG consists of counter with a programmable timeout interval that has the
capability to generate an interrupt and a reset signal on timing out.
For normal operation – the software has to ensure that the counter never
reaches zero (“kicking the dog”)
Usually WDOG interrupt is set with highest priority.
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Normal Mode
The simplest mode of operation is the Normal mode (WGM01:0 = 0).
In this mode the counting direction is always up (incrementing), and no counter clear is performed.
The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from
the bottom (0x00).
In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the
TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not
cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag,
the timer resolution can be increased by software. There are no special cases to consider in the Normal
mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much
ofthe CPU time.
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Clear Timer on Compare Match
(CTC) Mode
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches
the OCR0. The OCR0 defines the top value for the counter, hence also its resolution. This mode allows
greater control of the Compare Match output frequency. It also simplifies the operation of counting
external events.
The timing diagram for the CTC mode is shown in the figure below. The counter value (TCNT0) increases
until a Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared.
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Example 2: toggle led each 5 µs if you have a
frequency = XTAL = 10 MHZ
by Using compare match mode
Because XTAL = 10 MHz, the counter counts up
every 0.1 µs. This means that we need 5 µs / 0.1
µs = 50 clocks. Therefore, we have OCR0= 49.
DDRB |= 1<<3;
PORTB &= ~(1<<3);
while (1)
{
OCR0 = 49;
TCCR0 = 0x09;
while((TIFR&(1<<OCF0))==0);
TCCR0 = 0; //stop timer0
PORTB.3 = ~PORTB.3;
}
COM01WGM00FOC0 COM00 CS02 CS01 CS00 TCCR0WGM01
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using Timer0 and CTC mode generate a square wave on pin
PORTB.5, while at the same time data is being transferred
from PORTC to PORTD.
with 100 microS
Timer Lab 2 compare match interrupt
Time (µS)
44
F =1 MHZ
100*10^-6 / 10^-6 = Counter Numbers = 100
Compare Match = 100 – 1 =99 (start from 0 to 99)
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What is PWM ?
A PWM Signal is a periodic rectangular pulse.
Frequency = 1/T
Duty Cycle = (T_ON/T)
Pulse width modulation (PWM) is a powerful technique for controlling analog
circuits with a microprocessor's digital outputs. PWM is employed in a wide
variety of applications, ranging from measurement and communications to
power control and conversion.
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What is need of PWM?
PWM is mainly used for controlling the speed of DC motors . By pulse width
modulation we can get a variable voltage digitally, that is we get voltages
between 0 and VCC by switching the VCC on and off periodically . Other
applications are fading Led , getting different tones in Buzzer,Contolling the
degree of rotation of Servo motor .
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How Does A Servo Motor Work?
Usually a servomotor turns 90° in either direction, i.e. maximum movement
can be 180°
Three wires are taken out of a servo: positive, ground and control wire.
A servo motor is controlled by sending a Pulse Width Modulated (PWM) signal
through the control wire. A pulse is sent every 20 milliseconds.
Width of the pulses determine the position of the shaft. For example, a pulse
of
1ms will move the shaft anticlockwise at -90°, a pulse of 1.5ms will move the
shaft at the neutral position that 0° and a pulse of 2ms will move the shaft
clockwise at +90
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How Does A Servo Motor Work?
Width of the pulses determine the position of the shaft. For example, a pulse of
1ms will move the shaft anticlockwise at -90°, a pulse of 1.5ms will move the shaft at the neutral position
that 0° and a pulse of 2ms will move the shaft clockwise at +90
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Servo motor
Servo motor works on PWM (Pulse width
modulation) principle, means its angle of rotation is
controlled by the duration of applied pulse to its
Control PIN. Basically servo motor is made up of
DC motor which is controlled by a variable resistor
(potentiometer) and some gears
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Servo motor (another degree
range)(Motor-PWMSERVO in ISIS)
Servo motor can be rotated from 0 to 180 degree,
but it can go up to 210 degree, depending on the
manufacturing. This degree of rotation can be
controlled by applying the Electrical Pulse of proper
width, to its Control pin. Servo checks the pulse in
every 20 milliseconds. Pulse of 1 ms (1 millisecond)
width can rotate servo to 0 degree, 1.5ms can rotate
to 90 degree (neutral position) and 2 ms pulse can
rotate it to 180 degree.
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We can’t connect a DC Motor
directly to a microcontroller ?
A microcontroller can’t supply the current required for the working of DC
Motor. ATmega32 Microcontroller can source or sink currents up to 40mA but
a DC Motor needs current very much more than that.
The negative voltages created due to the back emf of the motor may affect
the proper functioning of the microcontroller.
You may need to control the direction of rotation of the motor by changing
the polarity of the motor supply.
The operating voltage of the DC Motor may be much higher than the
operating voltage of the microcontroller.
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L293D
To solve these problems you may use transistorized H Bridge in which
freewheeling diodes are used to avoid problems due to back emf. Thus it requires
minimum four transistors, diodes and resistors for each motor. It is better to use
readymade ICs such as L293D or L293instead of making your own H Bridge, which
simplifies your project.
L293D is a Quadruple Half H-Bridge driver commonly used for motor driving. We
needn’t connect any transistors, resistors or freewheeling diodes. All the four
outputs of this IC are TTL compatible and output clamp diodes are provided to
drive inductive loads. L293D can provide up to 600mA current, in the voltage
raging from 4.5 to 36v. L293 is a similar IC which can provide up to 1A in the same
voltage range.
L293 or L293D contains four Half H Bridge drivers and are enabled in pairs. Input
EN1 is used to enable pair 1 (IN1-OUT1, IN2-OUT2) and input EN2 is used to enable
pair 2 (IN3-OUT3, IN4-OUT4). We can drive two DC Motors with one L293D, but
here for demonstration we are using only one. You can connect second DC Motor
to driver pair 2 according to your needs.
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Normal Mode
The simplest mode of operation is the Normal mode (WGM01:0 = 0).
In this mode the counting direction is always up (incrementing), and no counter clear is performed.
The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from
the bottom (0x00).
In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the
TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not
cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag,
the timer resolution can be increased by software. There are no special cases to consider in the Normal
mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much
ofthe CPU time.
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Clear Timer on Compare Match
(CTC) Mode
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manipulate the
counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches
the OCR0. The OCR0 defines the top value for the counter, hence also its resolution. This mode allows
greater control of the Compare Match output frequency. It also simplifies the operation of counting
external events.
The timing diagram for the CTC mode is shown in the figure below. The counter value (TCNT0) increases
until a Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared.
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