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Prepared By,
Ms. K. D. Patil, Assistant Professor
Department of Information Technology
(NBA accredited)
Sanjivani College of Engineering, Kopargaon-423603.
Maharashtra, India.
(An Autonomous Institute, Affiliated with SPPU, Pune.)
NAAC ‘A’ Grade Accredited, ISO 9001:2015 certified
 There are two special function Registers
 Interrupt Enable (IE) Register
▪ Bit addressable
▪ Used to enable/ Disable interrupts of 8051
 Interrupt Priority (IP) Register
▪ Bit addressable
▪ Used to set the priority of interrupts
Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE,
Kopargaon 2
Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE,
Kopargaon 3
EA --- --- ES ET1 EX1 ET0 EX0
IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
IE Bits Operation
EA IE.7 Enables/ Disables all interrupts
If EA = 0 , no interrupt will be acknowledged
If EA = 1, interrupt source is individually enabled/ disabled by setting or
clearing its enable bit
___ IE.6 Not Implemented, Reversed for future use
___ IE.5 Not Implemented, Reversed for future use
ES IE.4 enable/ disable the serial port interrupt
ET1 IE.3 enable/ disable theTimer 1 overflow interrupt
EX1 IE.2 enable/ disable External Interrupt 1
ET0 IE.1 enable/ disable theTimer 0 overflow interrupt
EX0 IE.0 enable/ disable External Interrupt 0
MSB LSB
 When 8051 is powered up or upon reset, , IP register contains all
‘0’ s, making priority sequence based according to the below
 Priority schema in table is nothing but an internal polling
sequence in which 8051 polls the interrupt in the sequence
 To give higher priority in any of the interrupts, we make the
corresponding bit in IP register high
Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE,
Kopargaon 4
Type of Interrupt Priority
External Interrupt 0 INT 0 Highest Priority
Timer Interrupt 0 TF0
External Interrupt 1 INT 1
Timer Interrupt 1 TF1
Serial Communication RI +TI
Timer 2 Interrupt (8052 only) TF2 Lowest Priority
Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE,
Kopargaon 5
--- --- PT2 PS PT1 PX1 PT0 PX0
IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0
IP Bits Operation
___ IP.7 Not Implemented, Reversed for future use
___ IP.6 Not Implemented, Reversed for future use
PT2 IP.5 If PT2 = 1, High Priority
If PT2 = 0, Low Priority forTimer 2 Interrupt (In case of 8052)
PS IP.4 If PS = 1, High Priority
If PS = 0, Low Priority for Serial COM Interrupt
PT1 IP.3 If PT1 = 1, High Priority
If PT1 = 0, Low Priority forTimer 1 Interrupt
PX1 IP.2 If PX0 = 1, High Priority
If PX0 = 0, Low Priority for External Interrupt 1
PT0 IP.1 If PT2 = 1, High Priority
If PT2 = 0, Low Priority forTimer 0 Interrupt
PX0 IP.0 If PX0 = 1, High Priority
If PX0 = 0, Low Priority for External Interrupt 0
 In microcontroller,Timer 1 andTimer 0 interrupts
are generated by time register bitsTF1 andTF0.
 Steps to write a program as follows
 Select the configuration ofTMOD register and their
mode of operation.
 Enables the IE registers and corresponding timer bits
in it.
 Choose and load the initial values ofTLx andTHx by
using appropriate mode of operation.
 Set the timer run bit for starting the timer.
 Write the subroutine for a timer and clears the value
ofTRx at the end of the subroutine.
Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE,
Kopargaon 6
ORG 0oH ;wake-up ROM reset location
LJMP MAIN ;by-pass interrupt vector table
ORG 30H ;main program for initialization
MAIN:
....
END
 While writing a program using interrupt we must
avoid using memory space allocated to the Interrupt
VectorTable.Therefore, we place all the initialization
codes in the memory starting at 30H
 LJMP is the first instruction that the 8051 executes
when it is powered up
 LJMP redirects the controller away from the IVT
Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE,
Kopargaon 7
 Write ALP for 2KHz square wave generation of
XTAL=11.0592MHz using timer interrupt
ORG 0000H
LJMP MAIN
ORG 001BH
CPL P1.0
RETI
ORG 0030H
MAIN: MOVTMOD, # 10H
MOVTL1, #1AH
MOVTH1, #0FFH
MOV IE, #88H
SETBTR1
HERE: SJMP HERE
END
Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE,
Kopargaon 8
 “The 8051 Microcontroller and Embedded
Systems usingAssembly and C” , Muhammad
Ali Mazidi, Janice Gillispie Mazidi, Rolin D.
McKinlay, Second Edition, Pearson
publication
 http://what-when-how.com/8051-
microcontroller/programming-external-
hardware-interrupts/
Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE,
Kopargaon 9
Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE,
Kopargaon 10

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Unit 5_Interrupt programming in 8051 micro controller - part 2

  • 1. 1 Prepared By, Ms. K. D. Patil, Assistant Professor Department of Information Technology (NBA accredited) Sanjivani College of Engineering, Kopargaon-423603. Maharashtra, India. (An Autonomous Institute, Affiliated with SPPU, Pune.) NAAC ‘A’ Grade Accredited, ISO 9001:2015 certified
  • 2.  There are two special function Registers  Interrupt Enable (IE) Register ▪ Bit addressable ▪ Used to enable/ Disable interrupts of 8051  Interrupt Priority (IP) Register ▪ Bit addressable ▪ Used to set the priority of interrupts Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE, Kopargaon 2
  • 3. Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE, Kopargaon 3 EA --- --- ES ET1 EX1 ET0 EX0 IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 IE Bits Operation EA IE.7 Enables/ Disables all interrupts If EA = 0 , no interrupt will be acknowledged If EA = 1, interrupt source is individually enabled/ disabled by setting or clearing its enable bit ___ IE.6 Not Implemented, Reversed for future use ___ IE.5 Not Implemented, Reversed for future use ES IE.4 enable/ disable the serial port interrupt ET1 IE.3 enable/ disable theTimer 1 overflow interrupt EX1 IE.2 enable/ disable External Interrupt 1 ET0 IE.1 enable/ disable theTimer 0 overflow interrupt EX0 IE.0 enable/ disable External Interrupt 0 MSB LSB
  • 4.  When 8051 is powered up or upon reset, , IP register contains all ‘0’ s, making priority sequence based according to the below  Priority schema in table is nothing but an internal polling sequence in which 8051 polls the interrupt in the sequence  To give higher priority in any of the interrupts, we make the corresponding bit in IP register high Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE, Kopargaon 4 Type of Interrupt Priority External Interrupt 0 INT 0 Highest Priority Timer Interrupt 0 TF0 External Interrupt 1 INT 1 Timer Interrupt 1 TF1 Serial Communication RI +TI Timer 2 Interrupt (8052 only) TF2 Lowest Priority
  • 5. Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE, Kopargaon 5 --- --- PT2 PS PT1 PX1 PT0 PX0 IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 IP Bits Operation ___ IP.7 Not Implemented, Reversed for future use ___ IP.6 Not Implemented, Reversed for future use PT2 IP.5 If PT2 = 1, High Priority If PT2 = 0, Low Priority forTimer 2 Interrupt (In case of 8052) PS IP.4 If PS = 1, High Priority If PS = 0, Low Priority for Serial COM Interrupt PT1 IP.3 If PT1 = 1, High Priority If PT1 = 0, Low Priority forTimer 1 Interrupt PX1 IP.2 If PX0 = 1, High Priority If PX0 = 0, Low Priority for External Interrupt 1 PT0 IP.1 If PT2 = 1, High Priority If PT2 = 0, Low Priority forTimer 0 Interrupt PX0 IP.0 If PX0 = 1, High Priority If PX0 = 0, Low Priority for External Interrupt 0
  • 6.  In microcontroller,Timer 1 andTimer 0 interrupts are generated by time register bitsTF1 andTF0.  Steps to write a program as follows  Select the configuration ofTMOD register and their mode of operation.  Enables the IE registers and corresponding timer bits in it.  Choose and load the initial values ofTLx andTHx by using appropriate mode of operation.  Set the timer run bit for starting the timer.  Write the subroutine for a timer and clears the value ofTRx at the end of the subroutine. Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE, Kopargaon 6
  • 7. ORG 0oH ;wake-up ROM reset location LJMP MAIN ;by-pass interrupt vector table ORG 30H ;main program for initialization MAIN: .... END  While writing a program using interrupt we must avoid using memory space allocated to the Interrupt VectorTable.Therefore, we place all the initialization codes in the memory starting at 30H  LJMP is the first instruction that the 8051 executes when it is powered up  LJMP redirects the controller away from the IVT Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE, Kopargaon 7
  • 8.  Write ALP for 2KHz square wave generation of XTAL=11.0592MHz using timer interrupt ORG 0000H LJMP MAIN ORG 001BH CPL P1.0 RETI ORG 0030H MAIN: MOVTMOD, # 10H MOVTL1, #1AH MOVTH1, #0FFH MOV IE, #88H SETBTR1 HERE: SJMP HERE END Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE, Kopargaon 8
  • 9.  “The 8051 Microcontroller and Embedded Systems usingAssembly and C” , Muhammad Ali Mazidi, Janice Gillispie Mazidi, Rolin D. McKinlay, Second Edition, Pearson publication  http://what-when-how.com/8051- microcontroller/programming-external- hardware-interrupts/ Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE, Kopargaon 9
  • 10. Prepared By: Ms. K. D. Patil, Dept. of InformationTechnology, Sanjivani COE, Kopargaon 10