JAYAPRAKASH JPINFOTECH

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An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock

Vor 6 Jahren • 35 Aufrufe

JAYAPRAKASH JPINFOTECH

Dokumente

NS2 ieee 2017 project titles | Final Year IEEE 2018 Network Simulator Projects

A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS

A 2.4–3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique

A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging

A 30-W 90% Efficiency Dual-Mode Controlled DC–DC Controller With Power Over Ethernet Interface for Power Device

A 65-nm CMOS Constant Current Source With Reduced PVT Variation

A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing

A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding

A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy

A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission

A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications

A Way-Filtering-Based Dynamic Logical–Associative Cache Architecture for Low-Energy Consumption

An All-MOSFET Sub-1-V Voltage Reference With a −51-dB PSR up to 60 MHz

An FPGA-Based Hardware Accelerator for Traffic Sign Detection

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock

Antiwear Leveling Design for SSDs With Hybrid ECC Capability

Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits

Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application

Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture

Delay Analysis for Current Mode Threshold Logic Gate Designs

Design of Power and Area Efficient Approximate Multipliers

Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

Efficient Designs of Multiported Memory on FPGA

Efficient Soft Cancelation Decoder Architectures for Polar Codes

Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations

Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology

Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems

ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware