Lecture 5 Synchronous Sequential Logic

PHE 2251
PHE 225
Synchronous Sequential Logic
Lecture 5
Instructor: Professor Jim Evangelos
Electrical Engineering
Cecil College
North East, MD 21901

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Outline
1. Introduction
2. Sequential Circuits
3. Storage Elements: Latches
4. Storage Elements: Flip-Flops
5. Analysis of Clocked Sequential Circuits
6. Synthesizable HDL Models of Sequential Circuits
7. State Reduction and Assignment
8. Design Procedure

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5.1 Introduction
Digital circuits considered thus far have been combinational.
In combinational circuits, the output depends only and
immediately on their inputs. They have no memory, i.e.
dependence on past values.
Sequential circuits, however, act as storage elements and have
memory. They can store, retain, and then retrieve information
when needed at a later time.
This course distinguishes sequential logic from combinational
logic.

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5.2 Sequential Circuits
The diagram shows that the outputs in a sequential circuit are a function
not only of the inputs, but also of the present state of the storage elements.
A sequential circuit is specified by a time sequence of inputs, outputs and internal states.
Combinational logic depends only on present values of the inputs.
There are two flavors of sequential circuits, and the difference has to do
with the timing of their input signals. These are:
1. Synchronous Sequential Circuits
- Where discrete instants of time determine the behavior.
2. Asynchronous Sequential Circuits
- Where the behavior depends upon inputs signals occurring at any
instant of time.
- Behavior is also determined from which input signals change

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Storage elements for asynchronous sequential circuits consist of time-delay
devices. These are combinational circuits with feedback loops. Because of
this feedback, however among the gates, the asynchronous sequential circuit
may be unstable at times. Unstable circuits such as these are not considered
in our study.
Synchronous circuits employ signals that affect storage elements at discrete
instants of time. Synchronization is performed with the aid of a clock
generator.
Clocked sequential circuits used to control storage elements are the most
common types used. These circuits almost never have instability problems.
Storage elements (memory) used in clocked sequential circuits are called
flip-flops.

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A flip-flop is a binary storage device capable of storing one bit of
information.
Prior to the occurrence of a clock pulse, the combinational logic forming
the next value at the flip flop must reach a stable value. Consequently, the
speed with which the combinational logic operates is critical.
A transition from one state only occurs based on the clock pulse. Not even the
output of the flip-flops occurs until the appropriate clock pulse. This is true
even if the input to the combinational logic changes. Nothing happens until the
clock says so! Brings new meaning to the phrase:
“Timing is Everything”

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5.3 Storage Elements: Latches
A storage element can maintain a binary state indefinitely (as long as power is
delivered to the circuit), or until directed by an input signal to switch states.
Storage elements that operate with signal levels (rather than signal
transitions) are referred to as latches.
Storage elements controlled by a clock transition are flip-flops.
For this reason latches are said to be level sensitive devices, and flip-flops
are said to be edge sensitive devices.
Although latches can store information they are not practical for use as
storage elements in synchronous sequential circuits. They must be
studied however, because they are the basic building blocks of flip-flops.

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The SR latch is a circuit with two cross coupled NOR gates or two cross
coupled NAND gates, and two inputs labeled “S” for Set, and “R” for Reset.
There are two outputs, Q and Q’. A diagram of the cross coupled NOR is
shown below with its truth table.
The quiescent state is when both S and R are at zero. A latch has “state” and
the state changes when either S = 1 or R = 1, but only momentarily, and always
one at a time. Attempting to set S =1 and R = 1 simultaneously will result in an
unstable or unpredictable situation due to propagation delay. This is forbidden.
To make things clearer, the QQ’ state machine is shown to the right. Notice the forbidden
state in red. And there are two quiescent states. Note how it relates to the truth table.
Note that QQ’ state 11 is not possible, why is this?
SR Latch
01
00
10
S=1, R=0
S=0, R=1
S=1, R=1
forbidden
S=1, R=1
forbidden
S=0, R=0 S=0, R=0
QQ’ QQ’
QQ’

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The SR latch with cross coupled NAND is shown below (note sometimes called the S̅ R̅
latch, because it is the inverse of the previous one). Quiescent sate is with both inputs
equal to 1. When a state change is desired a zero(0) is set on S or R inputs momentarily,
to put it into either the Set or Reset quiescent states. Attempting S=0 and R=0
simultaneously is forbidden for similar reasons given for the NOR coupled latch on the
previous slide. Compare this latch to the NOR based latch.
Again, to make things clearer, the QQ’ state machine is shown to the right.
Notice the forbidden state in red. And there are two quiescent states. Note
how it relates to the truth table, and compare this to the NOR based SR
latch. Note that QQ’ state 00 is not possible.
SR Latch (S̅ R̅ )
01
11
10
S=0, R=1
S=1, R=0
S=0, R=0
forbidden
S=0, R=0
forbidden
S=1, R=1 S=1, R=1

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The operation of an SR latch can be modified by providing an additional
input signal that controls when the state of the latch can be changed by
determining when the S and R lines are “enabled”. For NAND the output
of the NAND gates stay at 1 as long as the Enable remains at 0.
Notice, this may seem contradictory to the SR latch on the previous slide, but
upon careful examination, you have to remember that the S is NANDED with
Enable, and the R is NANDED with Enable. In other words, the wiring of the SR
Latch with a NAND control circuit changes the behavior slightly, yielding a
slightly different truth (function) table.
SR Latch (with En control)
To make things clearer, a QQ’ state machine is shown to the right. Notice the
indeterminate state of this circuit is the same as the forbidden state of the previous slide.
01
11
10
En = 1,
S=1, R=0
En=1
S=0, R=1
En = 1,
S=1, R=1
forbidden
En = 1,
S=1, R=1
forbidden
En=0
S=X, R=X
En=0
S=X, R=X
set state
reset state

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We can eliminate the undesirable condition of the indeterminate or
forbidden state in the SR latch by ensuring that the S and R are never
equal to 1 at the same time! This is done with the D latch. Only two inputs
are needed D (data), and En (enable).
The reason why this is called a transparent latch, is because when the
Enable signal is given, the data passes from D to Q. This is called
asserting the En line. When En is de-asserted, the data on D line does not
make it to Q and Q’.
D Latch (Transparent Latch)
The QQ’ state machine is much nicer now
(no forbidden or indeterminate red states!).
0110
En = 1,
D = 1
En=0,
D = x
En=0
D=X
set state
En = 1,
D = 0
reset state

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The graphic symbols of all the latches we examined on the previous slides
is shown below. The bubbles always indicate complement. Bubbles on
input mean negative logic. In the compllemented cases for examplle, S =
0 means asserting Set, and R= 0 means asserting Reset.
D Latch (Transparent Latch)

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5.4 Storage Elements: Flip-Flops
The state of a latch or flip-flop is switched by a change in the control input.
The momentary change (or switch) is called a trigger and it is used to
“trigger” a flip-flop.
When latches are used for storage elements a serious problem arises.
The state transition of the latches start as soon as the clock pulse
changes to logic 1.
If the inputs applied to a latch change while the clock pulse is still at
logic-1, the latch will respond to the new values and a new output state
occurs. The result is an unpredictable situation.
For this reason, the output of a latch cannot be applied directly using
combinational logic to the input of some other latch when all the latches
use the same clock signal.
Clock pulses:
Input signals:

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This is also why a latch is said to be a “level-sensitive” device as opposed
to a flip-flop which is a “transition-sensitive” device. As long as the clock
“level” is maintained, the latch lets the input change the output.
So, this problem doesn’t exist with flip-flops. The reason is that flip-flops
use transition triggering. The feedback path is eliminated that is inherent
in sequential circuits using latches.
Clock pulses:
Input signals:

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As shown in the figure below, this transition can be from the positive edge
or the negative edge.
There are two ways to change a latch into a flip flop:
1. Employ two latches in a special configuration that isolates the output and
prevents it from being affected by the input changing.
2. Produce a flip-flop that triggers only during the transitions, 0 to 1 or 1 to 0
of the clock signal, and it is disabled during the rest of the clock pulse.
We now examine both approaches:

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We show the construction of a D flip-flop using two D latches:
Edge-Triggered D Flip-flop
The circuit samples the D input and changes the output Q only
on the negative edge of the clock. When Clk = 0, the slave is
enabled & Q is equal to the master output, y.
A change in the output of the flip-flop can be triggered only by
and during the transition of the clock from 1 to 0.
The behavior of the master-slave flip-flop dictates that:
1. The output changes only once
2. A change in the output is triggered by the negative edge of the clock
3. Changes only occur during a clock’s negative level.

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Another construction of edge triggered D flip-flops uses three SR latches as
shown:
S and R inputs of the output latch are maintained at logic 1 when
Clk = 0. This causes the output to remain in its present state.
Any change in D while Clk = 1does not affect the output!
(more detail of how this works is in your book)

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When the input clock in a positive edge
triggered flip-flop (like this one) makes
a positive transition, D is transferred to
Q.
A negative transition of the clock (from
1 to 0) does not affect the output nor is
it affected by changes in D when Clk is
at logic 1 or logic 0 level.
Therefore, this flip-flop responds to the transition from 0 to 1 (a positive
edge transition) and nothing else!

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As you may have guessed, timing and response is critical for these flip-
flops.
These are important parameters specified in manufacturer’s data books
for specific logic families:
Setup time: D must maintain a constant value prior to clock transition
Hold time: D input must not change after application of a positive
transition of the clock.
Propagation delay time: The interval between the trigger edge and the
stabilization of the output to a new state.

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A graphic representation of edge triggered D flip-flops is shown:
The Clk and “>” symbol denotes dynamic input (constantly changing).
Also on the graphic we can tell if the D flip flop responds to positive or
negative edge triggering.

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Other Flip-Flops
Flip-flops are constructed from an interconnection of gates. The
simplest and most economical flip-flop is the edge triggered D flip-flop
because it requires the fewest number of gates.
For this reason, other flip-flops can be constructed by using the D flip-
flop and external logic.
Two flip-flops less widely used in digital design are the JK & T flip-flops.
There are three operations that can be performed with a flip-flop:
1. Set the flip-flop to 1
2. Reset the flip-flop to 0
3. Complement the output

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Other Flip-Flops
The D flip-flop can Set or Reset the output depending upon the value
of the D input immediately before clock transition.
JK flip-flops, synchronized by a clock, have two inputs and perform all
three of the before mentioned steps.
The JK flip-flop is a D flip-flop with gates as shown:

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Other Flip-Flops
The J input Sets the flip-flop to 1. The K input Resets it to 0.
When both J and K are enabled, the output is complemented.
The operation of the JK flip-flop is characterized by this formula:
D = JQ’ + K’Q

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Other Flip-Flops
D = JQ’ + K’Q
J=1, K = 0 D = Q’ + Q = 1 Next clock edge sets the output to 1
J=0, K=1 D = 0 Next clock edge resets the output to 0
J = K = 1 D = Q’ Next clock edge complements the input.
J = K = 0 D = Q Next clock edge leaves input alone.

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Other Flip-Flops
The graphic symbol for the JK flip flop is now shown.
Note how it is similar to the graphic symbol for the D flip flop.

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Other Flip-Flops
The T, or Toggle flip-flop is another flip-flop, and it is obtained from the
JK flip-flop when inputs J & K are tied together:
Toggle flip-flop
T=0 (J=0, K = 0) With the Next clock edge, leave the input alone.
T=1 (J=0, K = 1) With the Next clock edge, compliment the input.
The T can be constructed with a D flip-flop & XOR
The expression becomes: D = TQ = TQ’ + T’Q
And the
graphic
symbol for
this flip-flop
is shown
(note the T):

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Characteristic Tables
A characteristic table defines the logical properties of a flip-flop by
describing its operation in tabular form.
You’ll notice Q(t) in the
tables, this indicates present
state.
Also, Q(t+1) indicates the
next state (one clock period
later)
Characteristic tables for three flip-flops are shown:

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Characteristic Equations
The characteristic equations can be derived from the characteristic
tables shown previously. We show each of these below:
D flip-flop: Q(t + 1) = D
Which states that the next state of the output is simply
equal to the input D in the present state
JK flip-flop: Q(t + 1) = JQ’ + K’Q
Where Q is the value of the flip-flop prior to
the application of the clock edge.
T flip-flop: Q(t + 1) = T  Q = TQ’+ T’Q Note to professor:
Make a note of this on
whiteboard, it is referred a
few slides up.

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Direct Inputs
Some flip-flops have asynchronous inputs that are used to force the flip-flop to a
particular state, independent of the clock.
The input that sets the flip-flop to 1 is called preset or direct set. To clear the flip-flop
to 0, use clear or direct reset.
These features are useful because when power is first turned on in a digital system,
the sate of the flip-plot is unknown. Below is what is known as a positive edge
triggered D flip-flop with active-low asynchronous reset.
These asynchronous inputs, allow the user
to force it to a known state (note the
mistake in the book, pg. 204).

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5.5 Analysis of Clocked Sequential Circuits
Analysis describes what a given circuit will do under certain operating
conditions.
The analysis of a sequential circuit consists of obtaining a table or
diagram for the time sequence of inputs, outputs, and internal states.
It is also possible to write a Boolean expression that describes the
behavior of the sequential circuit.
A logic diagram is recognized as a clocked sequential circuit if it
contains flip-flops (of any type) with clock inputs. In this section we
are going to show how to represent algebraically the next-state
conditions in terms of the present state and the inputs.
We are going to use state tables and state diagrams to formally
represent the behavior of the digital circuit.

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State Equations
The behavior of clocked sequential circuits can be described
algebraically by means of state equations. A state equation specifies
the next state as a function of the present state and the inputs.
Consider the circuit:
It is possible to write a set of state equations for the circuit:
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A’(t)x(t)
The left side of the equation with (t+1), denotes the next state
of the flip-flop one clock edge later. Since (on the right) all
equations are a function of the present state, we can omit t,
and write the equations more simply:
A(t+1) = Ax + Bx
B(t+1) = A’x
The Boolean expressions for the state equations can be
derived directly from the gates that form the combinational
circuit part of the sequential circuit, since D values of the
combinational circuit determine the next state. The present
state value of the output can be expressed as:
y(t) = [ A(t) + B(t) ]x’(t)
by removing t, for the present state we get the common form:
y = ( A + B )x’
Later we show that this circuit is a 0 detector.

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State Table
The state table for the circuit we just analyzed is shown to the
right. The derivation of the state table requires listing all
possible combinations for the present states and inputs.
The next state of the flip-flop must satisfy:
A( t+1) = Ax + Bx
Similarly, the next state of flip-flop B is derived from the state
equation:
B(t+1) = A’x
The output column is derived from the output equation:
y = Ax’ + Bx’
In general, a sequential circuit with m flip flops and n inputs
needs 2m+n rows in the state table. The Next State section
has m columns, one for each flip-flop.
It is sometimes convenient to express table 5.2
slightly differently, having only three sections:
present state, next state, output.
We show this with enumerated vales for the inputs.

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State Diagram
The graphical representation of a state table is the state
diagram. The state diagram of the circuit discussed is
shown. The numbers in the bubbles indicate the next
states. The numbers along the lines indicate
input/outputs of the present state.
Steps presented thus far have been this:
Circuit diagram → Equations → State Table → State Diagram
Notice, there is no difference in the information
conveyed with State Table, or State Diagram, it is just in
presentation.
Also, notice this circuit is a zero detector. After a string
of inputs of 1’s the first 0 detected gives an output of 1,
and returns the state of the circuit immediately back to
state 00. This happens in all of the states, given an input
of zero!
You would never discover this is a zero detector circuit
without the State Diagram!

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Flip-Flop Input Equations
There is a convention using flip-flop input symbol to denote the
input equation variable and a subscript to designate the name
of the flip-flop output. For example, the following input
equation specifies an OR gate with inputs x and y connected
to the D input of a flip-flop whose output is labeled with the
symbol Q:
DQ = x + y
The sequential circuit we used before consist of two flip-flops A
and B, an input x, and output y. Using our convention, we can
re-write the equations like this:
DA = Ax + By
DB = A’x
y = (A + B)x’
DA and DB correspond to the next states Q(t+1), but A and B as
you may recall reflect the current states.

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Analysis with D Flip-Flops
We summarize a procedure for analyzing a clocked sequential circuit with D flip-flops by
means of a simple example. The circuit we want to analyze is described by:
DA = A  x  y
The DA implies a D flip-flop with output A. The x and y variables are inputs. No outputs are
given, which implies the output comes from the output of the flip-flop.
A(t+1) = A  x  y
So the next state is
equal to 1 when
there is an odd
number of 1’s
among A, x, and y.
The circuit has two
states, either 1 or 0.

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Analysis with JK Flip-Flops
In general, a state table consists of four sections:
• present state
• inputs
• next state
• outputs
The first two are obtained by listing all binary combinations. The
next-state values are obtained from the state equations. The
outputs are determined from the output equations.
When a flip-flop other than D type is used, such as JK or T, it is
necessary to refer to the corresponding characteristic table or
characteristic equations to obtain the next values. (see slide 28
for the characteristic equations).

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An example is shown with the following setup:
The circuit has no outputs,
therefore there will be no output
column in the state table.
The circuit is characterized by
these flip-flop input equations:
JA = B KA = Bx’
JB = x’ KB = A  x = A’x + Ax’
Notice, that in the state table the present
state and the input columns represent all
the eight binary combinations. The JK
flip-flop inputs are from table 5.1

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The input equations for the two JK flip flops were listed (on slide 28).
For our case, with the two flip-fops, the characteristic equations of
the flip-flops are obtained by substituting values A and B for the
name of the flip-flop instead of Q:
A(t+1) = JA’ + K’A
B(t+1) = JB’ + K’B
Substituting values
for JA,KA, JB, KB:
A(t+1) = BA’ + (Bx’)’A = A’B + AB’ + Ax’
B(t+1) = x’B’ + (Ax)’B = B’x’+Abx+A’Bx’

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So this is how the Next State columns are populated, from these equations:
A(t+1) = BA’ + (Bx’)’A = A’B + AB’ + Ax’
B(t+1) = x’B’ + (Ax)’B = B’x’+Abx+A’Bx’
And from the State table we
can draw the state diagram: Note that since the circuit has no
outputs, the directed lines out of
the circles are marked with one bit
only, designating the input, x.

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Analysis with T Flip-Flops
The characteristic equation for T flip-flops is:
Q(t +1) = T  Q = T’Q + TQ’.
Now we consider an example with 2 flip-flops:
Here we show the two input
equations and one output
equation:
TA = Bx
TB = x
y = AB
To get the next state, we
substitute the TA and TB values for
in the characteristic equations:
A(t+1) = (Bx)’A + (Bx)A’ =
AB’ + Ax’ + A’Bx
B(t+1) = x  B
And from the State Table we can build the State Diagram ! Notice the output is in the state circle itself.
This is because the output depends upon the present state only, not the input!

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Mealy and Moore Models of Finite State Machines
The most general model of sequential circuits have
inputs, outputs, and internal states.
The two models of sequential circuits are shown
below:
Edward Forrest Moore (November 23, 1925 in Baltimore,
Maryland – June 14, 2003 in Madison, Wisconsin) was an
American professor of mathematics and computer science,
the inventor of the Moore finite state machine, and an early
pioneer of artificial life.
On the previous
slides we dealt with
several examples:
Mealy: Outputs depend on inputs. Thus the
output is the value that is present immediately
before the active edge of the clock.
Moore Outputs do NOT depend on inputs. The outputs are
synchronized with the clock, because they only depend on
flip-flop outputs that are synchronized with the clock!
There is a Fundamental difference
between the two!

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5.6 Synthesizable HDL Models of Sequential Circuits
•We came across Verilog HDL in section 3.9, and behavioral modeling
with Verilog was introduced in 4.12.
•Behavioral models are the abstract representation of the functionality of
digital hardware. It describes how a circuit behaves, not the internal
details.
•Truth tables, state tables, state diagrams all describe this behavior, but
so does HDL!
•HDL has added value, because it can be simulated to produce
waveforms demonstrating the behavior of a machine.
•Synthesis: When something is synthesizable we mean the process of
translating source code into a set of hardware structures that implement
the functionalities described in code. In contrast to circuit simulation,
which is a testing procedure used to ensure the synthesized circuit does
implement the intended behavior. Usually simulation is done just in
software.

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Two types of abstract behaviors in Verilog HDL.
1. declared by initial is called single-pass behavior and
specifies a single block statement (begin..end or fork..join pair).
Synthesis tools do not accept descriptions using initial.
2. declared by always means the behavior is cyclic. This
behavior executes indefinitely, until the simulation is stopped. Using
initial only executes once.
The book contains three ways to make a free running clock, review
these examples.
These use a #, delay control operator, which is commonly used in
single pass behaviors.
Another is the @, event control operator and is used to suspend
activity until an event occurs.
Behavioral Modeling

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The general form of the use of the event control operator is as
follows:
always @ (event control expression) begin
// Procedure assign statements that execute
// these must be of reg type
end
The sensitivity list can specify level-sensitive events, edge-sensitive
events, or a combination of the two. (the third option is not
synthesizable).
always @ (A or B or C)
If A, B, or C change, the statements between begin and end execute.
Since edge sensitive transitions can be either posedge or negedge,
but not both, HDL takes care of this, for example:
always @ (posedge clock, negedge reset)
Behavioral Modeling

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A procedural assignment is the assignment of a logic value to a
variable within an initial or always statement. This is in contrast to
a continuous assignment discussed in 4.12 with dataflow modeling.
A continuous assignment has an implicit level-sensitive sensitivity list
consisting of all the variables on the right-hand side of its assignment
statement.
Remember that a variable having type reg remains unchanged until
a procedure assignment is made to give it a new value.
Two kinds of procedure statements: blocking and nonblocking. (=)
is used by blocking statements, (<=) is used by nonblocking.
Behavioral Modeling

46
Blocking assignment statements are executed sequentially in the order
they are listed in a block of statements. Nonblocking assignments are
executed concurrently on the right hand side, the left hand side is not
assigned until all the expressions are evaluated.
Consider these two examples:
Behavioral Modeling
B = A
C = B + 1
B <= A
C <= B + 1
At the completion of the assignments on the left (blocking), B
contains A and C contains the result B+1.
At the completion of the assignments on the right (nonblocking), C also
contains the result B+1. The difference is that during the individual
assignments, the values A and B+1 are not immediately assigned,
instead they are put into a temporary storage, and at the end of the
statements, they are all assigned in one shot.

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There are two general rules for blocking (=), versus nonblocking
(<=) assignment:
Behavioral Modeling
Rule 1. Use blocking (=) assignments where sequential
ordering is imperative and in cyclic behavior that is level
sensitive (i.e. combinational logic).
Rule 2. Use nonblocking assignments (<=) when modeling
concurrent execution (i.e. in edge-sensitive behavior such as
synchronous, concurrent register transfers) and when modeling
latched behavior. Concurrent register transfers are
synchronized by a common clock. We cover this in chapter 8.

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Note that in 5.1, Q must be declared a reg type because it is assigned a value in a
behavior. Latches respond to input signal levels, so the two inputs (D, enable) are listed
without edge qualifiers in the sensitivity list following the @ symbol in the always
statement. Notice this is nonblocking (<=) assignment per Rule 2.
HDL Models of Flip-Flops and Latches
Note that in 5.2, we have two positive-edge D flip-flops in two modules. The
first only responds to a clock; the second includes an asynchronous reset in
addition to the clock. Output Q is declared as reg because it is the target
output of a procedural assignment statement. The keyword posedge ensures
that the transfer of input D into Q is synchronized by the positive edge
transition of Clk. A change in D at any other time does not change Q.

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There is a certain rule to keep in mind when dealing with
the second module.
(1) Each if or else if statement in the procedural
assignment statement is to correspond to an
asynchronous event.
(2) The last else statement corresponds to the clock
statement
(3) The asynchronous events are tested first.
Hardware always has a reset signal, and it is strongly
recommended that all models of edge sensitive
behavior include a reset (or preset) input signal to
establish the initial state of the flip-flops.

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In this example, we’ve got construction of
a T and JK flip-flops from a D flip flop.
And the characteristic equations are:
T flip-flop: Q(t + 1) = Q  T
In the TFF, the declared wire DT is assigned
exclusive OR of Q and T, and the instantiation
of DFF with DT being passed in for D produces
the required T flip-flop.
The JK flip-flop is specified in a similar manner by using the characteristic
equation to define the replacement for D in the instantiated DFF.

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In this example, we show another way to
construct a JK flip flop. Here we use the
characteristic table instead of the
characteristic equation. The case
multiway branch condition check the two-
bit number obtained by concatenating J
and K.
So, we compare two bit numbers 00, 01,
10, or 11. The four possible conditions
specify the value of the next state Q after
the application of the positive edge of the
clock.
As soon as any one of the conditions is
met, the appropriate assignment for Q is
made on the positive clock edge signal.
Note that case should be indented inside
the always (it is not in your book.)

52
State diagram-Based HDL Models
An HDL model of the operation of a sequential circuit can
be based off the state diagram. The state’s binary
assignment is done with the parameter statement. This
is a Verilog constant. S0 = 2’b00 and is preferable to S2
= 2 because it ensures only 2 bits are used.
The circuit for the Mealy zero detector detects a 0
following a sequence in a series of 1s in a serial bit
stream.
The three always statements operate concurrently.
The first always statement checks for state change.
The second always picks up the state change in its
sensitivity list and updates the next_state.
The third always also detects a change in state and
updates the value of output.
Also note that the second and third will pick up changes
in the input (x_in) and update next_state and y_out
accordingly .
The test bench code (still part of Example 5.5) is shown
on the next slide

53
The test bench is code used to test the Mealy Zero Detector.
Notice for example how t_y_out is due to the dynamic
behavor of t_x_in.
the fork…join construct is used to have statements execute
in parallel so the time delays are relative to a common
reference at t=0. The Mealy glitch is a transient logic value,
notice how it doesn’t line up with the clock.
The $finish is a system task and causes the simulation to
terminate unconditionally after 200 time units.
Each time unit division on the scale below is 3 time units.
0
31
2

54
Next we show the Moore Zero Detector, with its state
diagram. In this example, the output of the circuits is
independent of the input and is taken directly from the
outputs of the flip-flops. The state transitions are
described by a single clocked (edge-sensitive) cyclic
behavior by ONE always block of code!
Important observations:
(1) The output only depends on the state
(2) reset “on-the-fly” forces the state machine back to
S0 (00)
(3) The state transitions are consistent with the state
diagram.

55
Structural Description of Clocked Sequential Circuits
We are showing alternative ways to model a circuit.
Compare the two modules, which are highlighted.
The second way, includes the behavior of the T flip flop
itself, instead of the state machine. The circuit with T flip
flops is now shown above with it’s state machine.
An alternative to the Toggle_fip_flop is also shown. This
alternative describes the flip-flop in terms of its characteristic
function. The two models are interchangeable, and equivalent.

56
Structural Description of Clocked Sequential Circuits
Finally, we build the test bench to test the two approaches: The stimulus module provides common inputs to
circuits to simultaneously display their output
responses.
The first initial block specifies a toggling of input
x_in that occurs at the negative edges transition
fo the clock. Notice 16 clock “ticks”.
The second initial block provides eight clock
cycles with a period of 10ns.
As a result, the pair (A,B) goes through
sequence 00, 01, 10, 11 and back to 00. The
change in the count is triggered by positive edge
of the clock, provided x_in = 1.
If x_in = 0, the count does not change. y_out is
equal to 1 when both A and B are equal to 1.
Each time division is
10 ns in the timing
diagram →

57
5.7 State Reduction and Assignment
Analysis of sequential circuits starts from a circuit diagram and ends
with a state table or diagram.
The design (synthesis) of a sequential circuit starts from a set of
specifications, and ends in a logic (circuit) diagram.
Two sequential circuits may exhibit the same input-output behavior, but
have a different number of internal states in their state diagram.
There are certain properties of sequential circuits that may simplify a
design by reducing the number of gates and flip-flops it uses. And as
expected, this reduces the cost of a circuit.

58
The reduction of the flip-flops in a sequential circuit is referred to as the
state-reduction problem.
State Reduction
Since m flip-flops produce 2m states, a reduction in the number of states
may (or may not) result in a reduction in the number of flip-flops.
Also, the reduction in the number of flip-flops could even result in an
increase of the combinational logic (an unintended and unexpected
consequence).
We begin our discussion with an example state machine. In our
example the states will be denoted with letters, and not binary digits…..

59
There is an infinite number of input sequences that could
be entered into this circuit, resulting in a unique output set.
State Reduction
This state diagram has 7 states. Suppose we are
interested in a certain bit sequence, 01010110100. We
test our current state diagram, and obtain the following
outputs with state transitions:
Suppose we could find a sequential circuit that does the same thing in less than 7
states. If identical inputs are applied to the two circuits and we get identical
outputs, then the two circuits are equivalent!
state
a a b c d e f f g f g a
Input
0 1 0 1 0 1 1 0 1 0 0
Output
0 0 0 0 0 1 1 0 1 0 0

60
The problem of state reduction is to find ways of reducing
the number of states in a sequential circuit without altering
the input-output relationships.
State Reduction
To begin to reduce the number of states, we need to build
a state table from the state diagram:
Two states are said to be equivalent if, for each member
of the set of inputs, they give exactly the same output and
send the circuit either to the same state or an equivalent
state. In which case, one of the states can be removed.
Putting this into practice, we inspect the table to
the right, and we look for two present states that
go to the same next state and have the same
output for both input equations. States e, and g
are two such states!

61
So, one of the states must be removed.
State Reduction
This gives us a new table! But upon inspecting
this new table, we realize present state f has the
same next states for the same inputs as present
state d. Present states d and f also have
matching outputs!
Our original state diagram had 7 states, this one has 5 !
And using our original table with test inputs, we see that our
new state diagram works just as good, and is equivalent!
We decide to remove g. So we remove the last
row, and everywhere else the occurrence of g
in the original table is then replaced by e.
Therefore present state f is removed and replaced
by d. We get a another new reduced state table,
we inspect this state table and decide we cannot
reduce it any further.
state
a a b c d e f f g f g a
Input
0 1 0 1 0 1 1 0 1 0 0
Output
0 0 0 0 0 1 1 0 1 0 0



62
State Assignment
Finally, in order to make our state machine useful in the
world of digital electronics, we must use binary
numbers to represent our states. Note that our original
state machine (7 states) would require 23 = 8
combinations, with one combination unused. In our 5
state state machine we wind up with 3 unused states.
Unused states usually (but not always) results in a
reduction of logic gates.
This table shows three possible Assignment
schemes we can use for our states in our new
5 state state machine.
The table above, is the table we
chose, with Assignment 1, binary.
Sometimes, when a state table
uses binary assignments we refer
to this as a transition table, to
distinguish it from a state table
that uses symbolic names for the
states.

63
5.8 Design Procedure
The sequential building block used by synthesis tools is the D flip-flop.
Together with additional logic, it can implement the behavior of the JK and T
flip flops. Designers don’t concern themselves with which flip flops they
use, instead their focus is on correctly describing the sequential
functionality that is implemented by the synthesis tool. In the slides that
follow we illustrate manual methods using D, JK, and T flip-flops.
A combinational circuit merely requires a truth table for its implementation. A
sequential circuit, requires a state table for its specification. So, the first
step is to obtain this state table, leading to the state diagram.
A sequential circuit is made up of flip-flops and combinational gates. The
design procedure consists of choosing flip-flops along with combinational
circuits that produce a circuit which fulfills the stated specifications. The
number of flip-flops is dictated by the number of states.

64
The procedure for designing a synchronous sequential circuit can be
summarized by these steps:
1. From the word description and specifications of the desired operation,
derive a state diagram of the circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derived the simplified flip-flop input equations and output equations
7. Draw the logic diagram (the circuit).
Steps 4 through 7 in the design is accomplished by exact algorithms and
is automated. This part of the design procedure is known as synthesis.

65
As an example of the design procedure, we use a design that detects a
sequence of three or more consecutive 1’s in a string of bits coming
through the input line.
We can come up with a state diagram of a Moore model sequential circuit.
Note that it stays in S3 state as long as there are three or more consecutive
1’s detected.

66
Once we have the state diagram, the rest of the design follows the
synthesis procedure.
Synthesis Using D Flip-Flops
In fact, the circuit can be designed by using an HDL description of the state
diagram. Here, however, we go with a state table designed by hand.
This table shows the states of two D flip flops (four states total).
S0 =
S1 =
S2 =
S3 =

67
The characteristic equation of the D flip-flop; is Q(t+1) = DQ, which means
that the next state values in the state table specify the D input condition
for the flip-flop. The flip-flop input equations can be obtained directly
from the next-state columns of A and B and expressed as sum-of
minterms form:
A(t+1) = DA(A,B,x) = S(3,5,7)
B(t+1) = DB(A,B,x) = S(1,5,7)
y(A,B, x) = S(6,7)
Where A and B are the present state
values of the flip-flops, x is input and
DA ,DB are input equations.

68
We take the equations on the previous slide,
A(t+1) = DA(A,B,x) = S(3,5,7)
B(t+1) = DB(A,B,x) = S(1,5,7)
y(A,B, x) = S(6,7)
And use Karnaugh maps!
Now we have the simplified Boolean expressions!
The advantage of designing with D flip-flops is that the Boolean equations describing
the inputs to the flip-flops can be obtained directly from the state table. Software tools
automatically infer and select the D-type flip-flop from a properly written HDL model.

69
Finally, we create the schematic of the sequential circuit:
DA = Ax + Bx
DB = Ax + B’x
y = AB
This is the circuit for
a three or more
consecutive 1’s in a
string of bits
detector!

70
Excitation Tables
The design of a sequential circuit with flip-flops other than D type is
complicated by the fact that the input equations for the circuit must be
derived indirectly from the state table. For D-type, the input equations are
obtained directly from the next state. This is not the case with JK and T
type flip-flops. In order to determine the input equations for these, it is
necessary to derive a functional relationship between the state table and
the input equations.:
The flip-flop characteristic tables for the JK and T types provide the value of
the next state when the inputs and the present state are known. During the
design process we know the transition from the present state to the next state
and wish to find the input conditions that will cause the transition. So, we
need a table that lists the required inputs for a given state transition. This
done with an excitation table.

71
Excitation Tables
Below we show excitation tables for JK and T flip-flops. Note that these
tables show the present sate Q(t) and next states Q(t+1) and columns for
each input to show how the transition occurred. (note a small error in your
book, = should be +).

72
Synthesis Using JK Flip-Flops
The manual synthesis procedure for sequential circuits with JK flip-flops is the
same as with D flip-flops, except that the input equations must be evaluated
from the present state to the next-state transition derived from the excitation
table. To illustrate the procedure, we synthesize the sequential circuit
specified in the following table:
S0 =
S1 =
S2 =
S3 =

73
The flip flop inputs from the table specify the true table for the input
equations as a function of the present states A, B, and input x. They can
be simplified with Karnaugh tables!

74
Note the increase in the number of don’t cares. This is good, as we fill up
these maps, it makes the combinational circuit even simpler. This is the
advantage of using JK Flip-Flops! Nonetheless, D flip-flops are easier to
implement in automated design flow.
The resulting circuit is
much simpler! (compare
to slide 69)

75
Synthesis Using T Flip-Flops
The procedure for synthesizing circuits using T flip-flops is demonstrated
with a binary counter. An n-bit binary counter consist of n flip-flops that
can count in binary from 0 to 2n – 1. A three bit binary counter’s state
diagram is shown below:
Notice there are no
inputs (or outputs
shown). This is
because the state
transitions in this
case only depend
upon the clock.

76
The state table can be easily derived from the state diagram. Note that
the Present State column is always one state prior to the Next State, in
the State transition diagram. Note the flip-flop inputs needed to “toggle”
the bits between states.
From the state table,
we can build the k-
maps, populating 1’s
where the flip-flop
inputs are 1:

77
The input equations under each map specifies the combinational circuit
for the counter. Using these with three flip-flops, we obtain the logic
(circuit) diagram:

Lecture 5 Synchronous Sequential Logic

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