4. Corporate Overview
Incorporated: 1990
Headquarters: San Jose, California
Nasdaq listed: TSRA
Shares Outstanding: ~52 Million
Employees: ~270 (~210 Engineers)
2015 Revenue: $273 Million
2015 Net Income: $117 Million
Mission: Invent, develop, and commercialize electronic interconnect, imaging, and learning
technologies to enable efficient, intelligent devices everywhere.
5. Over 25 Years of Leadership in
Innovation & Technology Licensing
Develops novel semiconductor
packaging & interconnect solutions for
memory, mobile, computing, and smart
object applications.
Develops software and hardware-
accelerated computational imaging,
computer vision and biometrics
solutions for multiple applications.
Parent Company: Founded in 1990, manages licensing for Tessera’s subsidiaries.
Acquired in August 2015
6. ZiBond® and DBI® Process : Leverages Existing
Infrastructure
Courtesy Chipworks
ZiBond® DBI®
Courtesy Chipworks
Homogenous Bonding
Dielectric - Dielectric
(eg. SiO2- SiO2)
Oxide Si
Si
Hybrid Bonding
Oxide to Oxide with Interconnect
(eg. Cu/SiO2 - Cu/SiO2)
Interconnect
Si
Si
7. ZiBond Bond Energy
0
1000
2000
3000
4000
5000
0 1 2 3 4
Time(Hours)
BondEnergy(mJ/m^2)
250C
200C
150C
100C
50C
21C
Minimum bond
energy for post bond
fabrication
Fracture Strength
of Silicon
nd® Bond Energy
Low Distortion Dielectric Bonding
Very High Bond Energy at Very Low Temperature
8. DBI® Hybrid Bonding Uniqueness
Cross-Section after Pick/Place
(example)
Heating Closes Recess (~ 1 nm / 50ºC) Further Heating Compresses Metal
w/out External Pressure
Spontaneous Chemical Reaction with
By products Diffusing Away from
Bond Interface
Electrical Interconnections at Low Temperature without
External Pressure Minimizes Stress and Cost of Ownership
9. ZiBond® and DBI® Have Widespread
Applicability
Die to Wafer (D2W) Bonding
Die to Die (D2D) Bonding
MEMS
(MEMS+Cap Wafer,
MEMS+Logic)
DRAM
(Multi-Die 3D Stacking)
Image Sensor
(Image Sensor + Logic)
RF
(RF IC + ASIC)
2.5D Logic + Memory
(CPU/GPU + Stacked Memory)
Fingerprint Sensor
(Image Sensor + Logic)
Wafer to Wafer (W2W)
Bonding
Current ZiBond and/or DBI Licensees*:
Sony, Silanna Semiconductor (acq. by Qualcomm), Raytheon, Novati, Fraunhofer, Tezzaron, Sandia and
MIT LL
* Licensed to ZiBond and/or DBI
11. Example MEMS Process Flow*
• „Typical“ flow requires two
bond steps
• Variety of bond options
– Si Fusion
– Anodic
– Transient Liquid Phase
– Eutectic
– Metal
thermocompression
– Others ...
Handle Wafer
with cavity
MEMS Device
Wafer
Wafer Bond 1:
Handle to
MEMS
MEMS Device
Definition
CMOS Wafer
Wafer Bond 2:
MEMS to
CMOS
Bond pad
expose,
Packaging
* Adapted from “Applying the CMOS Test Flow to MEMS
Manufacturing” Mike Daneman, InvenSense, Inc.
(http://www.meptec.org/Resources/2%20-%20InvenSense.pdf)
12. Comparing Bond Technologies*
Anodic Glass Frit TLP Eutectic Metal
TCB
Bonding
Temp. (oC)
350 - 450 350 - 450 180 - 300 300 - 450 100 - 400
Post Anneal
(oC)
NA Same as
bonding
Higher than
bonding
Same as
bonding
NA
Bond Cycle
Time (min)
5 – 20 20 – 30 30 – 50 30 – 50 15 - 90
Line Width
(mm)
>20 200 – 500 >30 >30 >30
Topography
Toler. (mm)
0 1 – 1.5 1 1 0
Leak Rate Low Low Very Low Very low Low
Other High
Voltage
Pressure
*Adapted from EVG’s presentation at MEMS Tech XPOT Semicon West 2015
15. High Throughput: DBI Die to Wafer
Die to Wafer Bonding
would be used in MEMS
applications where top
and bottom die sizes may
not match
Die to wafer video here
16. Comparing Permeability of Water Vapor in
Materials
Ref: D. Stroehle “On the Penetration of Water Vapor into Packages with Cavities and on Maximum Allowable Leak
Rates” 15th Annual Proceedings, Reliability Physics Symposium, pp 101-106, 1977.
• Glass seals vary considerably
in permeability
– 10 um seal width does not
provide adequate sealing
– 100 um may suffice,
depending on glass
properties
• Metal seals demonstrate
orders of magnitude better
performance than glass
• Depending on applications,
either ZiBond or DBI could be
used
100 mm
10 mm
17. Hermetic Sealing With ZiBond
• Die Size: 8x8 mm2
• Cavity: 7x7 mm2x 0.1mm
• Bond ring: 0.5 mm
• MIL STD 883E
Ref: P. Enquist, “Room Temperature
Direct Wafer Bonding for Three
Dimensional Integrated Sensors”,
Sensors and Materials, Vol. 17, No.
6, 2005, p. 307
Helium partial pressure vs post-helium pressure time for ZiBond bonded silicon cavity to silicon wafer
Expect even better hermetic sealing from DBI (comparable to other metal bond technologies)
18. ZiBond in MEMS
Photograph of a MEMS cavity wafer encapsulated with ZiBond to a glass wafer for a micromirror
application. Inset of a singulated die shows the ZiBond surface
19. Comparing Bond Technologies
Anodic Glass Frit TLP Eutectic Metal
TCB
ZiBond DBI
Bonding
Temp. (oC)
350 - 450 350 - 450 180 - 300 300 - 450 100 - 400 Room Room
Post Anneal
(oC)
NA Same as
bonding
Higher than
bonding
Same as
bonding
NA 75 – 300
Post anneal
150 – 300
Post anneal
Bond Cycle
Time (min)
5 – 20 20 – 30 30 – 50 30 – 50 15 - 90 < 5* < 5*
Line Width
(mm)
>20 200 – 500 >30 >30 >30 > 20** > 20**
Topography
Toler. (mm)
0 1 – 1.5 1 1 0 0 0
Leak Rate Low Low Very Low Very low Low Low Very
Low***
Other High
Voltage
Pressure
• Ref: Ziptronix internal data; BEOL development facility (Morrisville, NC)
** Preliminary analysis shows equal to/better than Anodic bonding
** Ref: Slide 15, equivalent or better than similar metal bonding
21. Applying ZiBond and DBI to MEMS
• Wafer / Die Bonding is a Key Technology Enabler - 2.5D/ 3D IC, Image Sensors, MEMS / Other
Sensors, DRAM, RF …
• ZiBond® and DBI® : Cost effective, low temperature wafer to wafer and die to wafer
bonding platforms for wide range of applications
– In high volume production - Multiple generations of leading smartphones and other consumer electronics
– RF: Enables reliable bonding and lowers cost for filters and switches
– Image Sensor: Industry leading backlight illuminated (BSI) image sensor with up to pixel-level interconnect capability
– DRAM: Thinnest and lowest cost 3D DRAM
– 2.5D/3D IC: Eliminates microbumps, underfills and improves performance
• ZiBond® and DBI® for MEMS:
– Alleviates temperature, cycle time, pressure or high voltage concerns with current bonding solutions
– Enables lower cost and reliable MEMS devices
Editor's Notes
Machine learning technology that is specifically designed for deployment at the edge: into tiny devices, rather than giant data centers. (We have a dedicated team of experts led by our CTO working specifically on “small” machine learning that can run in battery-powered devices.)
Wafer to wafer, chip to wafer and chip to chip bonding are key technology enablers in semiconductor industry and currently used in wide variety of market and applications
Wafer to wafer bonding are used in Sensor, MEMS, RF etc applications where sensor or MEMS or RF front end IC die needs to bond with logic procssing ICs. Most cases senor or analog front end Si and digital processing Si are not single chip solution to utilize the best technology node for each Si cost, function and performance optimization. Generally die per wafer count are very high and wafer level processing for stacking results into best optimized solution.
In MEMS, in some of the process cap wafer needs to bonded hermitically seals with MEMS IC which also require wafer level low cost bonding solution.
Chip to wafer bonding are used is solutions where die per wafer count are lower, ASP is typicall higher. Wafer level processing may result into bad chip to be bonded and throwing away higher ASP due part due to yiled loss. So chip to wafer bonding process is used where known good die is bonded on known good chip of the wafer. Chip to wafer bonding good example would be DRAM 3D staking.
Chip to chip bonding are common method for very high ASP Silicon, with various sizes of large chips need to bonded.
GPU, high-end FPGA, high bandwidth memorey etc 2.5/3D assemblies are examples of prffered method for chip to chip bonding.
