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1. AN SURVEY OF EFFICIENT FPGA IMPLEMENTATION OF ADVANCED ENCRYPTION
STANDARD ALGORITHM FOR ENCRYPTION USING VERILOG
A.UDAY KUMAR,
M.TECH-VLSI,SRM UNIVERSITY-NCR CAMPUS,
MODINAGAR,GHAZIBAD-201204
EMAIL-ID:-udaykumar1303@gmail.com
ABSTRACT:-
This paper implements the FPGA implementation of
AES algorithm using verilog .All cryptographic
algorithms use FPGA for hardware implementation
.Because,FPGA are programmable devices we need
those cryptographic algorithms to secure the
information .Here in this we use AES algorithm for
encryption and decryption. This proposed design
uses an iterative looping with block and key size of
128 bits look up table implementation of S-box. This
gives less complexity in the architecture. we use
Verilog HDL for the simulation. Here we compose
these results with previous results to slow the
efficiency.
Keywords:-FPGA,AES,VERILOG HDL,ENCRYPTION,DECRYPTION
INTRODUCTION:-
Before AES there was one standard algorithm for the
symmetric key encryption namely DATA
ENCRYPTION STANDARD with the key length of 56
bits so,it can be easily broken ,so people thought
DES is not sufficient to secure data for this reason .
In sep,1997 The National institute of standard and
technology(NIST) has given a call for cryptographic
algorithm. Finally Rijnadel AES has been selected by
the (NIST).Here AES has the size of 128,192 and 256
bits. So, automatically it becomes difficult to break
the key. Here rijnadel specified the block key size in
any multiple of 32 bits.
The AES is a cryptographic algorithm used to secure
the data. AES is symmetric block chipper to encrypt
and decrypt the data in blocks of 128 bits. Encryptor
is used to convert the plaintext into cipher text.
Decryptor is used to convert the block cipher text to
plaintext. Here encryptor and decryptor need the
10,12and14 iteration rounds to complete the
encryption and decryption process. Here number of
rounds required based on the size of block size and
key size. Here, in the data encryption process we
utilize look up table implementation of s-box to get
the complexity less in architecture.
FPGA implementation is the better choice for the
cryptographic algorithms especially for AES than
GPP’S and ASIC’S because FPGA’S are
reprogrammable devices. It can give better response
in wider applications than ASIC’s. It provides faster
hardware solution than GPP’s.
AES ALGORITHM:
It is a cryptographic algorithm used to encrypt or
decrypt the data to keep the data secured.AES is a
symmetric block cipher that process the data in the
size of 128 bit blocks. The 128 bit data block split
into 4*4 matrix of 8 bits called the state and it put
through the rounds of operation designed to encrypt
the data. The no.of.rounds depends on the size of
the key and block data [3] .
Here these rounds consists of 4 transformations
namely Sub-S-Byte, Shift, Add Round key and Mix
column transformation. The last round omits mix
column transformation. This is the process to
encrypt the data as well as decryption is also same
but inverse to encryption process rounds.
AES ENCRYPTION:-
The below figure depicts the AES encryption. Input
to these AES encryption is plain text and output is
block cipher text. We can get this block cipher text
by performing the rounds namely First round
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ISBN:378-26-138420-027

2. ,Normal round and Last round. As we have stated
these rounds consists of sub byte, shift, mix column
and add round key transformation to encrypt the
data.
Normal round consists of 4 transformations but the
first and last round differ from normal round. In first
round there is presence of additional add round key
at the same time. Last round omits the mix column
transformation. Here encryption works with the 128
bit-[2].
SUB BYTE TRANSFORMATION:-
It is a non-linear byte substitution operating on each
row of the state bytes independently. Here non-
linear substitution means each byte is replaced with
the other according to look up table. This is also
known as s-box. That s-box consists of 256 number
and their corresponding resulting values the
following figure shows the look up table. This is
more efficient method than directly implementing
multiplicative inverse operation followed by affine
transformation. By using this method we can reduce
the complexity of the hardware. As the hardware
complexity decreases latency go decrease
automatically. By this we can complete the S-Box in
single clock cycle.
SHIFT ROW TRANSFORMATION:-
It performs the shifting operation. It is just a routing
process. In this encryption process ,we can explain
this transformation in the way that, the bytes in the
first row of state do not change. The second, third
and fourth rows shift critically to the left one byte,
two byte, three bytes respectively depicted in
thebelowfigure.
MIX COLUMN TRANSFORMATION:-
Mix column transformation performs the mixing
operation on the columns of the state .The main Aim
of the mix column transformation is combining the
four bytes in a column using the linear trans
formation. Here columns of the state are considered
as the polynomial over the gf(2^8) and multiplied by
the modulo(X^4+1) with the fixed polynomial c(x)
given by
C(x)=(03)x^3+(01)x^2+(01)x+(02)
By using this approach we can easily realize the 4-
byte output of mix column transformation
ADD ROUND KEY TRANSFORMATION:-
Here in this Add Round key transformation ,a round
key is added to the state ,which is resulted from the
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ISBN:378-26-138420-028

3. mix column transformation by using the X-OR with
state round key.
AES ENCRYPTION CORE:-
In AES Encryption each round completes their
respective process in the single clock cycle .As we
have stated earlier input to and output of the
encryption process is plain text, round key and block
cipher text. It runs the process with the size of 128-
bit wide.
When the input signal is asserted then input data
loaded into the round and new encryption starts to
produce the new encrypted data (block cipher
text).This will produce the cipher text after 11,12,13
iterations . No. Of iteration rounds based on the size
of the data block size and key size. This allow’s the
external synchronous ROM to store the round key
schedule. A new encryption can be started since the
round key index is zero . once it go high the process
will go run to encrypt the data .By the time it reach
next zero it produce the output.
AES DECRYPTION:-
AES Decryption is the process used to convert the
block chipper text into the original data .we can get
the decrypted data after several rounds .This rounds
consists of same transformations what we had in the
encryption but inverse. Here also we do not have
mix column transformation in the last round
.decryption also take 11to14 iteration rounds to
complete the process.
INVERSE ADD-ROUND KEY TRANSFOMATION :-
This Add Round Key transformation is same as we
discussed in the encryption like using the X-OR
function between the state and the round key index.
Here round keys have to be selected in the reverse
order because it is the inverse add round key
transformation .Basically add round key
transformation is the inverse function because the x-
or function using here is having own-inverse
property
INVERSE SHIFT TRANSFORMATION:-
Inverse shift transformation is same but inverse to
the shift transformation in encryption process.
Basically, it performs the shifting operation between
the rows of the state .first row will not shift. Second,
third, fourth row are shifted to right by one, two,
three bytes respectively
INVERSE SUB BYTE TRANSFORMATION:-
This transformation is a non-linear byte substitution.
Non-linear substitution means replacing each byte
with another byte according to the inverse look up
table (inverse s-box).This below figure depicts the
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ISBN:378-26-138420-029

4. inverses-box.
INVERSRE MIX COLUMN TRANSFORMATION:-
Inverse Mix column transformation performs the
mixing operation on the columns of the state. The
main aim of this transformation is combining the
four bytes in the state .In inverse mix column trans
formation, the polynomial of degree less than 4over
gf (2^8), which coefficients are the elements of the
state are multiplied by modulo (x^4+1) by fixed
polynomial then it given as
D(x)=(0b)x^3+(0d)x^2+(09)x+(0e)
AES DECRYPTION CORE :-
AES Decryption core is the process used to convert
the block cipher text to original text .when the signal
is asserted, block cipher text enter into the round a
new decryption process starts to produce the
decrypted data. once block cipher text enter into the
decryption after 11 to14 iterations it gives the
decrypted data. This also allows the external
synchronous rom to store the round key index. a
new decryption can be started whenever the round
key index is zero .one clock cycle later the output of
the previous become available .since it go high it run
the process by the time it go low it give the result .
FPGA IMPLEMENTATION OF AES ALGORITHM:-
FPGA is the best choice for the cryptographic
algorithms, for AES also. because it is a re-
programmable one .it gives the better response in
speed than general purpose processors and it
provide greater applicability than ASIC .the below
figure shows the FPGA implementation of AES
algorithm .the table after the diagram shows the
control signals.
Here we should maintain 128-bit length for text-in,
text-out and key. Here control signals
clk,reset,enable are used to make the process
working correctly means proper operation of the
core .proper round keys can be generated by
combining the block key ,load key with key round
block to perform the key expansion. This process
works under the control of control signals coming
from the controller block. This controller block takes
the clock, enable, reset, direction, write signals from
the outside and generate the control signals. When
the write signal make a low-high-low transition plain
text (text_in) will go loaded .we can find the process
is completed when the done signal is pulsed after
the some clock cycles from the write signal goes low
.Done signal occur in one cycle .While doing the
process with 128-bit wide block the process can be
completed within 25 cycles for both encryption and
decryption process
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ISBN:378-26-138420-0210

5. SIMULATION RESULTS:-
Here use VERILOG HDL to write the code for this
design. All the result are synthesized and simulated
on the quatos 9.0, the model sim-altera 6.49 and
ep20k400cb652c7 device. The below figure shows
the results of the encrypted and decrypted algorithm
from the model-sim simulator.
In the above design simulation results that latency is
very low. Based on the above simulation results we
can say that both theoretical results and simulated
results are equal. How means the output of the
encryption was found after 13 cycles from the
starting of the encryption process. so, latency of the
encryption process is 13 cycles. Automatically
decryption need 12 cycles.
COMPARISION:-
To show that our design is best we should compare
our design results with the other results. If the result
of our design is better than other design, then only
we can say that our design is best. The below table
shows the comparision between our design and
other design.
When we compare our design with other FPGA
vendors like Xilinx and other altera mixed versions
.Our design has given better results in the respective
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ISBN:378-26-138420-0211

6. fields of area, throughput, latency, memory. At the
same time our design can keep the data in high
secure. The below figure shows the comparison
table which consists of compared results between
our design and other designs
CONCLUSION:-
Now-a-days information security is the major
concern for the user. For that, In this paper we have
proposed the FPGA implementation of AES
algorithm with data block of 128-bits and key length
of 128-bits using verilog. We used altera apex20kc
FPGA which is a high performance device to
implement our design based on the iterative
approach. We will simulate the results by using the
model sim and we compared the results with other
designs .Finally, we found that our design got the
better results than the other results in the respective
fields of area, throughput and latency.
REFERENCES:-
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Implementation of Advanced Encryption standard algorithm”.
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2. Hoang trang and nguyen van loi ,”an efficient FPGA
Implementation of Advance Encryption Standard Algorithm”.
computing and communication technologies-IEEE,2012 (feb27-
mar1).
3. Chetna sangwan, chetna bharadwaj , nisha and taruna
sikka,”vlsi implementation of Advanced Encryption standard
algorithm”. Computing and communication technologies-IEEE,
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4. Anderson cattenlan zigiotto and Roberto d’amore , “Low-cost
FPGA Implementation of Advanced Encryption Standard
algorithm”.Integrated circuits andsystem design-
IEEE,2012,page(191-196).
5. cristian chip, david chein, Charles chein, Ingrid
verbauwhede,frank chang.”Hard ware implementation in FPGA of
Rijnadael algorithm”.cicuit and systems-IEEE-2012aug(4-
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ISBN:378-26-138420-0212