(1&2)
Chapter (7) of the text book

8086 Minimum-Mode Signals
Mode
Select MN/MX’
Interrupt
interface
8086 MPU
Power supply
Vcc GND
INTR
_____
INTA
_____
TEST
NMI
RESET
HOLD
HLDA
Address / data bus
AD0-AD15,
A16/S3-A19/S6
ALE
____
BHE/S7
M/IO’
DT/R’
___
RD
___
WR
____
DEN
READY
CLK
DMA
interface
Memory/IO
controls

32 32

8086

3 2
XTAL
or EFI
CLK
to mP
PCLK
to Per
OSC:
EFI To other mPs

f/3
frequency, f
RC circuit for
automatic Reset on power up
PCLK
2.5 MHz
f/6
Grounded when
Xtal Osc is used
Manual
Reset
push button
Switch
Typical Application of the 8284A for clock and Reset signal generation
RC time constant large enough
for 50 ms min Reset pulse
at worst trigger conditions (1.05 V Threshold)
RESET
50 ms
Minimum
Effective
Digital
#RES Input
R
C
OSC
f 15 MHz
Synced
To CLK

RLH - Fall 1997RLH - Spring
1998
ECE 611 Timing - 49
8086 Bus Timing - Read
T1 T2 T3 T4 T1 T2 T3 Tw Tw T4
Bus Cycle Bus Cycle
Two Wait States
States
CLK
Status Status
A,BHE
A,BHE
A(19-16)
BHE
(WR is kept high)
Mem Read I/O Input
A Data In A Data In
AD(15-0)
Latch
Address
Latch
Address
ALE
Mem I/O
M / IO
Read Read
RD
Receive Receive
DT/R
Disable Enable Disable Enable
DEN
Ready Ready
Wait Wait
READY
Valid Valid
AB(19-0)
Data In Data In
DB(15-0)

RLH - Fall 1997RLH - Spring
1998
ECE 611 Timing - 50
8086 Bus Timing - Write
T1 T2 T3 T4 T1 T2 T3 Tw T4
Bus Cycle Bus Cycle
One Wait State
CLK
(RD is kept high)
Mem Write I/O Output
Status Status
A,BHE
A,BHE
A(19-16)
BHE
AD(15-0) Data Out
A
A Data Out
Latch
Address
Latch
Address
ALE
Mem I/O
M / IO
Write Write
WR
Latch
Data Latch
Data
Transmit Transmit
DT/R
Disable Enable Disable Enable
DEN
Ready Ready
Wait
READY
Valid Valid
AB(19-0)
Data Out Data Out
DB(15-0)