Test results obtained during fault current interruption tests with an air-core reactor are compared to test results obtained using a saturating-core inductive HTS Fault Current Limiter in the same circuit under the same circumstances. These test results are further compared with analytical simulations developed using the PSCAD® software suite. The simulations exhibit good agreement with the test results and confirm that compared to an equivalent air-core reactor, the HTS FCL results in lower amplitude and significantly lower rate of rise of the Transient Recovery Voltage.

1. 1
Abstract — Test results obtained during fault current
interruption tests with an air-core reactor are compared to test
results obtained using a saturating-core inductive HTS Fault
Current Limiter in the same circuit under the same
circumstances.
These test results are further compared with analytical
simulations developed using the PSCAD® software suite. The
simulations exhibit good agreement with the test results and
confirm that compared to an equivalent air-core reactor, the
HTS FCL results in lower amplitude and significantly lower rate
of rise of the Transient Recovery Voltage.
Index Terms — transient recovery voltage, rate of rise of
transient recovery voltage, fault current limiter, HTS FCL,
saturating-core FCL, inductive FCL, air-core reactor.
I. INTRODUCTION
ince 2006, Zenergy Power has been developing a type of
inductive magnetic fault current limiter (MFCL) for
electric power grid applications. For efficiency, the
Zenergy MFCL currently relies on a high-temperature
superconductor (HTS) DC magnet to bias a magnetic core,
though any source of DC magnetic flux could be employed.
The DC-flux-saturated magnetic core, when coupled with a
surrounding AC coil, acts as a variable inductor in an electric
circuit. The inductance of the HTS MFCL changes instantly in
real-time in response to the current in the electrical circuit
being protected. The inductance varies from a low steady-
state value, which oscillates slightly as the DC magnetic bias
level oscillates with changing AC current in the deeply
saturated portion of the magnetic core material B-H curve
during normal operating conditions, to a high value during a
fault condition, which is sufficient to limit the fault current to
the desired maximum value. A number of superconducting
fault current limiter concepts have been extensively reported
upon to date [1-5]. Likewise, the development and evolution
of Zenergy’s MFCL has been extensively documented in this
and other papers [6-10, 15]. A remarkable agreement between
measurements and analytical simulation of fault current
limitation was described in [6] where a comprehensive
description of the work conducted on the development, testing
and application of a compact saturable core HTS fault current
limiter was presented.
During the extended field demonstration of the first
Zenergy MFCL to operate in the commercial electrical grid,
Zenergy and system host, Southern California Edison (SCE)
became aware of a number of important considerations,
including the potential for the MFCL to experience resonance
________________________________________________
Franco Moriconi(franco.moriconi@zenergypower.com) and Francisco De La
Rosa (francisco.delarosa@zenergypower.com) are with Zenergy Power, Inc.,
Burlingame, CA, USA
in the protected circuit under some conditions [8], along with
issues raised by projection engineers concerned with the
impact of the MFCL on relay settings and circuit-breaker
performance parameters. In particular, questions were raised
regarding the time rate of change of the limited fault current at
interruption and the effects of the MFCL on transient recovery
voltage (TRV) and the rate of rise of recovery voltage
(RRRV). The burden on a circuit-breaker is a function of the
magnitude of the interrupted current and the TRV [11].
The use of conventional series reactors can reduce the
current interruption rating of a circuit breaker. However, they
can increase the RRRV and the peak TRV value to above that
when the series reactor is absent [11-13]. A larger RRRV
reduces the interrupting capability of the circuit breaker and
the beneficial effects of fault current limiting. Even though
fault current limiting devices impose the same interrupting
burden on the circuit breaker regardless of the side of the
breaker on which they are installed, analysis suggests that they
are best placed on the downstream side of the circuit breaker
to reduce the source side voltage [14]. Dependence of RRRV
with distance to the fault for a series reactor with very small
parallel capacitance has been reported to be minimal [11].
In 2010, Zenergy received its first commercial contract for a
saturable-core MFCL – an 11kV device to be installed in a
33/11kV primary substation operated by CE Electric in North
Lincolnshire, UK. The 1,250 amp continuous-rated MFCL
will be installed on the low-side of one of the 33/11kV
transformers and the incoming circuit-breaker on the existing
11kV switchboard [9]. CE Electric and their integration
contractor, Applied Superconductor Ltd (ASL), raised similar
issues regarding MFCL transient effects on protection
engineering. Zenergy recognized that this project, which was
scheduled to undergo full-power and full-voltage type and
acceptance testing, afforded the opportunity to directly
measure the MFCL transient effects on current interruption.
This paper compares actual TRV and RRRV measured values
from fault current testing of a circuit with a saturable-core
HTS FCL and a series reactor providing equivalent fault
current reduction. In a earlier paper, an analytical method of
evaluating the transient recovery voltage of a series current
limiting reactor (CLR) was derived and verified using EMTP-
RV®, and PSCAD® simulations were conducted for a 1.188
mH, 2 mH and 3 mH series reactors [16]. The simulation
results also compare favourably to the real-world test results.
II. TEST CIRCUIT AND RESULTS
Fig. 1 illustrates the three-phase line diagram of the test
circuit used with the 11kV, 1,250-amp MFCL. The testing
was conducted at KEMA’s Powertest’s laboratories in
Chalfont, PA, USA in February 2011. The corresponding
circuit with the series reactor was exactly the same except that
F. Moriconi, Member, IEEE, and F. De La Rosa, Senior Member, IEEE
Transient Recovery Voltage Test Results of a 25
MVA Saturable-Core Fault Current Limiter
S
978-1-4673-1935-5/12/$31.00 ©2012 IEEE

2. 2
it incorporated an equivalent series reactor instead of the
MFCL. The inductance of the series reactor used in the test
was that which produced the same fault current limitation as
the MFCL, and was calculated as follows:
,
1
The source resistance is neglected in (1), as it is assumed
that .
In Equation (1), Vs is the source line-to-ground voltage, ω
the angular velocity = 2πf, and , is the fault current of the
network when a fault current limiter is installed to limit the
current by a specific percentage of its prospective value.
The relevant parameters of this application are as follows:
Rs=0.0163 Ω
Vs=11.3 kV
Xs=1.0577 Ω
Ls = 0.0032 H
f=50 Hz
Xs/Rs≈60
Prospective symmetric fault current = 6.2 kA
Limited prospective fault current , = 4.63 kA (25%
reduction).
LCLR=0.001285 H, from eq. (1). A 1.2 mH reactor was used in
the test.
A bolted three phase fault is set up by closing the Making
Switch MS under Master Breaker MB closed and by opening
the Auxiliary Breaker AUX a few cycles later, the voltage on
both sides of this breaker are measured to determine the
Transient Recovery Voltage as illustrated in Fig. 1. This was
separately done with the MFCL or the series reactor in the
circuit. The objective was to demonstrate that the TRV and
the RRRV in the upstream breaker would be less pronounced
with the MFCL in the circuit than it would with the series
reactor, as our preliminary simulations had revealed.
Fig. 1 – TRV Circuit Setup with the FCL in the Circuit
Fig. 2 is a representative sample of the fault current
waveforms recorded during the test from its start through
interruption a few cycles (119 ms) thereafter, when the current
is interrupted to measure TRV across the AUX breaker.
Notice that during the fault, the voltage across the AUX
breaker or L-N voltage depicted in the three waveforms on
the center is zero, and that the voltage recovers its normal
value at the time of fault interruption. The three bottom
waveforms illustrate the source voltage waveform showing a
dip at the initiation and throughout the duration of the fault.
Fig. 3 shows the corresponding L-N and source voltage
waveforms for the case with the series current limiting reactor
in the circuit..
Fig. 2 – Fault Current (I), Line to Neutral Voltage (V-N) and Source Voltage
(U) with MFCL in circuit.
The voltage waveforms shown in Fig. 4 and Fig. 5, labeled
as TRV waveforms, represent the difference between the time
varying voltage signals measured at both sides of the
Auxiliary Breaker AUX in Fig. 1, here described as voltages
Vs and Vl on the source and load side of the breaker,
respectively:
2
Measurements were performed with a 1 MHz sampling
rate, yielding a digital sample per microsecond.
Fig. 6 depicts around 10 ms of high resolution TRV
waveforms presented on the same scale for convenience to
quickly compare the cases with the MFCL and with the CLR
in the circuit. Notice the larger peak of the waveform with
CLR.
-10
0
10
Ia[kA]
-10
0
10
Ib[kA]
0 0.05 0.1 0.15 0.2 0.25
-10
0
10
Time [sec]
Ic[kA]
-10
0
10
Va-N[kV]
-10
0
10
Vb-N[kV]
0 0.05 0.1 0.15 0.2 0.25
-10
0
10
Time [sec]
Vc-N[kV]
-10
0
10
Ua[kV]
-10
0
10
Ub[kV]
0 0.05 0.1 0.15 0.2 0.25
-10
0
10
Time [sec]
Uc[kV]

3. 3
Fig.3 – Fault Current (I), Line to Neutral Voltage (V-N) and Source Voltage
(U) with Air Core Reactor in circuit.
Fig. 4 – TRV Waveforms for MFCL
Fig. 5 – TRV Waveforms for Air Core Reactor
Fig.6 – Comparative TRV Waveforms for MFCL and Series Air-Core
Reactor. B phase only.
III. PSCAD® SIMULATIONS
Simulations were conducted in PSCAD® to determine the
fault current and transient recovery voltage. Both, a single-
phase and a full three phase representations of the test circuit
were created to produce fault current waveforms up to the
time when fault current reaches the symmetric level and high
resolution runs to produce the microstructure of the TRV,
respectively. Output waveforms were separately produced for
cases with the MFCL and the CLR.
A. Case 1: MFCL
Fig. 7 illustrates the PSCAD® representation of the circuit
with the MFCL in it. The non-linearity of the FCL is described
in [16]. Notice that the fault is represented by the ground
connection attached to the load side of the FCL.
Fig. 7 – PSCAD® TRV Test Circuit With Saturable-Core HTS FCL
In this simulation the MFCL was confirmed to provide a
25% reduction in fault current as depicted in Fig. 8. The
symmetrical current was reduced from 6.2 kA rms to 4.63 kA
rms.
Fig. 8 – Fault Current Reduction with a Saturable-Core MFCL
-10
0
10Ia[kA]
-10
0
10
Ib[kA]
0 0.05 0.1 0.15 0.2 0.25
-10
0
10
Time [sec]
Ic[kA]
-10
0
10
Va-N[kV]
-10
0
10
Vb-N[kV]
0 0.05 0.1 0.15 0.2 0.25
-10
0
10
Time [sec]
Vc-N[kV]
-20
0
20
TRVa[kV]
-20
0
20
TRVb[kV]
0 0.05 0.1 0.15 0.2
-20
0
20
Time [sec]
TRVc[kV]
-20
0
20
TRVa[kV]
-20
0
20
TRVb[kV]
0 0.05 0.1 0.15 0.2
-20
0
20
Time [sec]
TRVc[kV]
0.02 0.022 0.024 0.026 0.028 0.03
-20
-15
-10
-5
0
TRVb-phase[kV]
FCL
Reactor

4. 4
Fig. 9 shows the PSCAD three-phase representation of the
test circuit with the MFCL used to corroborate the voltage and
current signals in the different nodes of the circuit. Fig. 10
depicts, in descending order, the C-phase calculated fault
current and L-N and source voltage waveforms in the same
sequence that was presented for the measured current in Fig.
2. Notice that the waveform asymmetry in the fault current is
evident in the measured and calculated waveforms of Fig. 2
and Fig. 10. This is because the presented simulation time
window corresponds to the initial part of the waveform when
the DC component of the current is still decaying.
Fig. 9 – PSCAD three-phase representation of the test circuit with a Saturable-
Core MFCL
B. Case 1: 1.2mH Series Reactor
Fig. 11 depicts the PSCAD® model for the TRV test circuit
with the series reactor in the circuit. The series reactor
inductance required to deliver the same reduction in fault
current as the MFCL, as it was described in II above using
eq.(1), is around 1.2 mH. This was confirmed through the
PSCAD® simulation shown in Fig. 12. Notice the overlapping
of the two curves showing an air core reactor limited current
comparable to that provided by the FCL. Here again, the fault
is represented by the ground connection on the load side of the
series reactor.
Fig. 10 – PSCAD Calculated waveforms for Phase C with FCL
Fig. 11 – PSCAD® Model for 1.2 mH Series Reactor
Fig. 12 – Instantaneous and RMS Fault Current Profiles for TRV Circuit with
a 1.2 mH Series Reactor
Identically as presented for the case with the MFCL, Fig 13
depicts in descending order, the C-phase calculated fault
current and L-N and source voltage waveforms in the same
sequence that was presented for the measured current in Fig. 3
in the case when the CLR is in the circuit. Likewise, the
measured and calculated waveform asymmetries are evident
comparing Fig. 3 and Fig. 13, respectively.
0.0032[H]
BRK4
0.0032[H]
0.0032[H]
BRK5
BRK6
E2a_FCL
Ea_FCL
Lvar
a b
Ia_w_FCL
BRK4
0.0163[ohm]
Ea_MB_w_FCL
0.012[uF]
8.5E-3[uF]
Ia_FCL
E1a_FCL
Ib_FCL
Ic_FCL
E2b_FCL
Eb_FCL
Lvar
a b
Ib_w_FCL
BRK5
0.0163[ohm]
Eb_BRK_w_FCL
0.012[uF]
8.5E-3[uF]
E1b_FCL
E2c_FCL
Ec_FCL
Lvar
a b
Ic_w_FCL
BRK6
0.0163[ohm]
Ec_BRK_w_FCL
0.012[uF]
8.5E-3[uF]
E1c_FCL
CustInd2.F
BRK8
BRK8
Timed
Breaker
Logic
Closed@t0
Timed
Breaker
Logic
Open@t0
Timed
Breaker
Logic
Open@t0
Timed
Breaker
Logic
Open@t0
Eb_MB_w_FCL
BRK11
Ec_MB_w_FCL
BRK12
BRK11
Timed
Breaker
Logic
Closed@t0
BRK12
Timed
Breaker
Logic
Closed@t0
Ea_BRK_w_FCL
1.0[ohm]
Main:Graphs
0.000 0.050 0.100 0.150 0.200 0.250
-15.0
-7.5
0.0
7.5
15.0
(kA)
Ic_FCL
-15.0
-7.5
0.0
7.5
15.0
(kV)
Ec_MB_w_FCL
-15.0
-7.5
0.0
7.5
15.0
(kV)
Vcn_FCL

5. 5
Fig. 13 – PSCAD®-Calculated waveforms for Phase C with CLR
C. TRV Calculations
As described by eq. (2) the TRV is the difference of the
source and load side voltages of the AUX Breaker. Fig. 14
depicts the measured TRV waveforms across the AUX
breaker with the MFCL in the circuit, and Fig. 15 shows the
corresponding PSCAD calculated waveforms with the air-core
reactor CLR in the circuit, as the breaker opens at the zero-
crossing of the current to interrupt the fault.
Fig. 14 – Measured TRV waveforms for the MFCL and the 1.2 mH CLR
cases
Fig, 15– PSCAD®-Calculated TRV waveforms for the MFCL and the 1.2
mH CLR cases
IV. RELEVANT FIDNINGS
Comparing Figs. 14 and 15, the measured and calculated
waveforms show a close agreement both in the amplitudes and
in the oscillation frequency. The parameters of the connecting
cables were ignored and this may be responsible for the micro
structural differences in the waveforms. However, both
measured and calculated waveforms reveal a first oscillation
with a peak of around 5 kV in the CLR TRV waveform. This
first swinging is associated with an initial measured RRRV of
2100 kV/µs, compared with around 863 kV/µs for the MFCL
for the same range of voltage involved in that first oscillation.
As previously noticed, both measured and calculated results
reveal a higher peak for the TRV as compared with the MFCL
arrangement.
V. CONCLUSIONS
Saturable-core MFCL devices are a potential alternative to
the application of series reactors. The use of series reactors
might stress the interruption duty of the circuit-breaker by
introducing a fast transient oscillation in the TRV. This is due
to the combination of both low capacitance and high
inductance in the device.
Analytical studies conducted with PSCAD® and later
confirmed with full-power testing laboratory measurements
suggest that the employment of equivalent saturable-core
MFCL would have a significantly lower impact on the TRV of
the upstream circuit-breaker compared to the use of an
equivalent series reactor. This should make it possible for
MFCL devices to be installed in the electrical grid without
having to apply TRV mitigation methods such as adding
external capacitors.
Main:Graphs
0.000 0.050 0.100 0.150 0.200 0.250
-15.0
-7.5
0.0
7.5
15.0
(kA)
Ic_CLR
-15.0
-7.5
0.0
7.5
15.0
(kV)
Ec_MB_w_CLR
-15.0
-7.5
0.0
7.5
15.0
(kV)
Vcn_CLR

6. 6
VI. REFERENCES
[1] Schmitt, H., Amon, J. Braun,D., Damstra, G., Hartung, K-H, Jager, J.,
Kida, J, Kunde, K., Le, Q., Martini, L., Steurer, M., Umbricht, Ch,
Waymel, X, and Neumann, C., “Fault Current Limiters – Applications,
Principles and Experience”, CIGRE WG A3.16, CIGRE SC A3&B3
Joint Colloquium in Tokyo, 2005
[2] CIGRE Working Group, “Guideline of the impacts of Fault Current
Limiting Devices on Protection Systems”. CIGRE publishing, Vol
A3.16, February 2008. Standard FCL and Cigre
[3] CIGRE Working Group, “Fault Current Limiters in Electrical medium
and high voltage systems”. CIGRE publishing, Vol A3.10, December
2003.
[4] Noe. M, Eckroad. S, Adapa. R, “Progress on the R&D of Fault Current
Limiters for Utility Applications,” in Conf. Rec. 2008 IEEE Int. Conf
Power and Energy Society General Meeting pp.1-2.
[5] Orpe, S. and Nirmal-Kummar, C.Nair, “State of Art of Fault Current
Limiters and their Impact on Overcurrent Protection”, EEA Apex
Northern Summit 08, November 2008, Power Systems Research Group,
The University of Auckland
[6] Moriconi, F., De La Rosa, F, Singh, A.,, Chen, B., Levitskaya, M.,
Nelson, A., “An Innovative Compact Saturable-Core HTS Fault Current
Limiter - Development, Testing and Application to Transmission Class
Networks, in 2010 IEEE PES Conf. Proceedings, Minneapolis, MN, July
25-29, 2010.
[7] F. Moriconi, F. Darmann, R. Lombaerde, “Design, Test and
Demonstration of Saturable-Core Reactor HTS Fault Current Limiter,”
presented at the US DOE Superconductivity for Electric Systems Peer
Review, August 5, 2009, Alexandria, Virginia
[8] Clarke, C., Moriconi, F., Singh, A., Kamiab, A., Neal, R., Rodriguez, A.,
De La Rosa, F., Koshnick, N., “Resonance of a Distribution Feeder with
a Saturable Core Fault Current Limiter,” Proceedings of 2010 IEEE PES
Transmission and Distribution Conference, April 19-22, New Orleans,
LA, USA.
[9] D. Klaus, A. Wilson, A. Hobl, J. Bock, D. Jones, J. McWilliam, A.
Creighton, L. Masur, F. Moriconi, “Fault Limiting Technologies in
Distribution Networks,” Proceedings of the CIRED 21st
International
Conference on Electricity Distribution, 6-9 June, 2011, Frankfurt,
Germany.
[10] A. Nelson, F. Moriconi, F. DeLaRosa, D. Kirsten, L. Masur, “Saturated-
Core Fault Current Limiter Field Experience at a Distribution
Substation,” Proceedings of the CIRED 21st
International Conference on
Electricity Distribution, 6-9 June, 2011, Frankfurt, Germany.
[11] E. Calixte, et al., "Reduction of rating required for circuit breakers by
employing series-connected fault current limiters," Generation,
Transmission and Distribution, IEE Proceedings-, vol. 151, pp. 36-42,
2004.
[12] D. F. Peelo, et al., "Mitigation of circuit breaker transient recovery
voltages associated with current limiting reactors," Power Delivery,
IEEE Transactions on, vol. 11, pp. 865-871, 1996.
[13] T. A. Bellei, et al., "Current-limiting inductors used in capacitor bank
applications and their impact on fault current interruption," in
Transmission and Distribution Conference and Exposition, 2001
IEEE/PES, 2001, pp. 603-607 vol.1.
[14] A. F. Alcidas, et al., "Evaluation of Position of a Fault Current Limiter
with Regard to the Circuit Breaker," in Power Symposium, 2006. NAPS
2006. 38th North American, 2006, pp. 475-480.
[15] Moriconi, F., Koshnick, N., De La Rosa, F., Singh, A., “Modeling and
Test Validation of a 15kV 24MVASuperconducting Fault Current
Limiter,” Proceedings of 2010 IEEE PES Transmission and Distribution
Conference, April 19-22, 2010, New Orleans, LA, USA.
[16] Lopez-Roldan, J., Price, A. C., DeLaRosa, F., Moriconi, F., “Analysis of
the Effect of a Saturable-Core HTS Fault Current Limiter on the Circuit
Breaker Transient Recovery Voltage,” Proceedings of 2011 IEEE PES
General Meeting, July 24-28, Detroit, MI, USA.

7. 7
VII. BIOGRAPHIES
Franco Moriconi leads Zenergy’s Engineering
effort in the development of a commercial
Superconducting Fault Current Limiter. Under his
technical leadership Zenergy Power installed and
energized a first-ever HTS FCL in the US electric
grid. In 1992, he joined ABB Corporate Research
to lead R&D work in the areas of numerical and
Finite Elements methods, short-circuit strength and
noise reduction of power transformers, Gas
Insulated Switchgear technology, and high-speed
electrical motors and generators. He also
participated in two IEC working groups, and was the Convener of the IEC
Scientific Committee 17C on seismic qualification of GIS. Currently, he is an
active member of the IEEE Task Force on FCL Testing. Franco Moriconi
earned a Bachelor of Science degree and a Master of Science degree in
Mechanical Engineering from UC Berkeley. He is the co-author of six patents
in the field of HV and MV electrical machines.
Francisco De La Rosa joined Zenergy Power Inc.
in April 2008 as Director of Electrical Engineering.
Before joining Zenergy Power, Inc., Francisco held
various positions in R&D, consultancy and training
in the electric power industry for around 30 years.
Francisco holds a PhD degree in Electrical
Engineering from Uppsala University, Sweden and
a MSc from ITESM in Monterrey, Mexico. He is a
Senior Member of IEEE PES and a Member of
CIGRE. His main interests include the assessment
and integration of new technologies in the electric power system in utilities
and industry. Francisco is the author of CRC’s Harmonics and Power Systems
book and has coauthored in the CRC Power Systems, Electric Power
Engineering Handbook, 2nd
Ed. as well as in over 50 power quality related
papers in reviewed journals and in international technical conference
proceedings.