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Hardware Multithreading
Coarse-grained
Fine-grained
Simultaneous
Coarse- grained multithreading
• Single thread runs until a costly stall
– E.g. 2nd level cache miss
• Another thread starts during stall for first
– Pipeline fill time requires several cycles!
• Does not cover short stalls
• Less likely to slow execution of a single thread
(smaller latency)
• Needs hardware support
– PC and register file for each thread
– little other hardware
Fine-grained multithreading
• Two or more threads interleave instructions
– Round-robin fashion
– Skip stalled threads
• Needs hardware support
– Separate PC and register file for each thread
– Hardware to control alternating pattern
• Naturally hides delays
– Data hazards, Cache misses
– Pipeline runs with rare stalls
• Does not make full use of multi-issue architecture
Simultaneous Multithreading (SMT)
• Instructions from multiple threads issued on
same cycle
– Uses register renaming and dynamic scheduling
facility of multi-issue architecture
• Needs more hardware support
– Register files, PC’s for each thread
– Temporary result registers before commit
– Support to sort out which threads get results
from which instructions
• Maximizes utilization of execution units
Conceptual Diagram
(Similar to fig 7.5 in text)
Thread A Thread B Thread C Thread D
Coarse Multithreading
Stalls for A and C would be longer than indicated in previous slide
Assume long stalls at end of each thread indicated in previous
slide
Fine Multithreading
Skip A
Simultaneous Multithreading
Skip A
Skip C

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Hardware multithreading

  • 2. Coarse- grained multithreading • Single thread runs until a costly stall – E.g. 2nd level cache miss • Another thread starts during stall for first – Pipeline fill time requires several cycles! • Does not cover short stalls • Less likely to slow execution of a single thread (smaller latency) • Needs hardware support – PC and register file for each thread – little other hardware
  • 3. Fine-grained multithreading • Two or more threads interleave instructions – Round-robin fashion – Skip stalled threads • Needs hardware support – Separate PC and register file for each thread – Hardware to control alternating pattern • Naturally hides delays – Data hazards, Cache misses – Pipeline runs with rare stalls • Does not make full use of multi-issue architecture
  • 4. Simultaneous Multithreading (SMT) • Instructions from multiple threads issued on same cycle – Uses register renaming and dynamic scheduling facility of multi-issue architecture • Needs more hardware support – Register files, PC’s for each thread – Temporary result registers before commit – Support to sort out which threads get results from which instructions • Maximizes utilization of execution units
  • 5. Conceptual Diagram (Similar to fig 7.5 in text) Thread A Thread B Thread C Thread D
  • 6. Coarse Multithreading Stalls for A and C would be longer than indicated in previous slide Assume long stalls at end of each thread indicated in previous slide