1.
Fedora and Firmware in practice
Linux on RISC-V
Wei Fu <wefu@redhat.com>
Senior Software Engineer
Platform Enablement, Red Hat Software (Beijing) Co.,Ltd.
Nov 30th 2019
Embedded Fest 2019 Kyiv
1

2.
AGENDA
2
What is RISC-VISA
Run Fedora on RISC-VPractice
What is FedoraDistro
Status
Industry standard RISC-V server/PCGoal
Fedora on RISC-V

3.
3
Part I
What is
RISC-V
What is RISC-V
Birth of RISC-V
RISC-V Foundation
Why RISC-V

4.
What is RISC-V (pronounced risk-five)
4
RISC(Reduced Instruction Set Computer)
• A type or category of the processor, or
Instruction Set Architecture (ISA).
• RISC generally refers to a streamlined version of
its predecessor, the Complex Instruction Set
Computer (CISC).
V(fifth)
• The fifth major RISC ISA design effort at UC
Berkeley
• RISC-I, RISC-II, SOAR, and SPUR were the first
four projects with the original RISC-I publications
dating back to 1981
Info Source:
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-6.pdf

5.
What is RISC-V
5
RISC-V is the hardware
Instruction Set Architecture (ISA)
• A high-quality, license-free, royalty-free RISC ISA
• Standard maintained by non-profit RISC-V
Foundation
• Suitable for all types of computing system, MCU
to supercomputers
Rich Ecosystem
• Experiencing rapid uptake in industry and
academia
• Numerous proprietary and open-source cores
• Supported by growing shared software
ecosystem

6.
Birth of RISC-V
6
Seek & Explore
• In 2010, the Computer Science team at
UC Berkeley to look at what ISAs to use
for their next set of projects:
• x86 & ARM impossible – complex, IP
issues
Innovation & Revolution
• UC Berkeley started “3-month project”
during the summer of 2010 to develop
their own clean-slate ISA
• In May of 2014, UC Berkeley released
frozen base user spec

7.
RISC-V Foundation
7
Originate
• In August 2015, articles of incorporation
were filed to create a non-profit RISC-V
Foundation to govern the ISA.
Mission
• non-profit entity serving members and
the industry
• accelerate RISC-V adoption with shared
benefit to the entire community of
stakeholders.

8.
RISC-V Foundation
8
Drive technical priorities in 20+ focus areas
• Opcode Space Mgmt Standing Committee
• Software Standing Committee
• Security Committee
• Base ISA Ratification Task Group
• Privileged ISA Spec Task Group
• B Extension (Bit Manipulation) Task Group
• J Extension (Dynam. Translated Lang) Task Group
• P Extension (Packed-SIMD Inst) Task Group
• V Extension (Vector Ops) Task Group
• Debug Specification Task Group
• Cryptographic Extension Task Group
• Trusted Execution Env Spec Task Group
• Fast Interrupts Spec Task Group
• Memory Model Spec Task Group
• Processor Trace Spec Task Group
• Sv128 Specification Task Group
• Compliance Task Group
• UNIX-Class Platform Spec Task Group
• Formal Specification Task Group
• HPC Special interest Group
• proposed SafetyTask Group

9.
Why RISC-V
9
Free & Open
• The free and open RISC-V ISA is
enabling a new innovation frontier for all
computing devices
RISC-V ushers in new era of silicon design
• Simple
• Stable
• A modular ISA
• Clean-slate design
• Designed for extensibility/specialization

10.
Some RISC-V IP companies
10
Region
Commercial
Companies
Business
model
Open
Source
IP
Commercial
IP
Silicon advantage
US
SiFive
Core IP
Silicon Service
Freedom
E2/3/5/7
S5/7
U5/7/8
FE310/FU540
/FU740
Huami
Huangshan
No. 1
Pioneer,
Leading RISC-V
development
Microsemi
FPGA
(RISC-V
embedded)
Mi-V RV32 PolarFire SoC
RISC-V Soft CPU
for FPGA;
RISC-V + FPGA
SoC
BlueSpec Core IP Piccolo/Flute
Cortus
Core IP
Silicon Service
FPSx
APSx
Esperanto

11.
Some RISC-V IP companies (Cont)
11
Region
Commercial
Companies
Business
model
Open Source
IP
Commercial
IP
Silicon advantage
Taiwan Andes Core IP N22/N25/A25
K*
A*
Has very rich
CPU design
experience
Mainland
China
Nuclei Core IP
Hummingbird
E203
200 Series
300 Series
600 Series
900 Series
GD32V
Famous in
China
ICT
Research
Education
Yes For Test
OpenSource;
Education;
Test Silicon;
New feature;
Russia Syntacore Core IP SCR1 SCR3/4/5/7
EU Codasip Core IP Bk1/3/5/7/10

12.
Some RISC-V Chip Companies
12
Region
Commercial
Companies
Business
model
Commercial
IP
Silicon advantage
Mainland
China
Canaan AI Chip
K210
(New chip is
under
development)
AI module(KPU)
APU(Audio)
FFT accelerator
T-Head
(平头哥)
Chip
C960
E902
Ultra-low power
EU
GreenWaves Chip GAP8
Low power
8 core parallel
compute cluster
UltraSoC IP
debug
monitoring
the commercial
development
env for RISC-V

13.
Some Companies using RISC-V in their product
13
Region
Commercial
Companies
Usage
US
Western
Digital
Storage Controller
NVIDIA Control Core in some GPU
Google MCU in some Soc
Micron memory controlor
Ceva CEVA Extends its IP Platforms for Bluetooth and Wi-Fi with RISC-V
Asia
samsung MCU in some Soc
JL Semi Hi-Speed Hi-performance communication chips

14.
14
Part II
What is
Fedora
Fedora
RHEL
CentOS

15.
Fedora/RHEL/CentOS
15
Fedora RHEL CentOS
 Focus on new features
and new technology
 Community-driven, Free
 Short release cycles
(approximately 6M)
 Focus on stability
 Supported by Red Hat,
Comes with subscription
 Slower releases
(approximately 9M)
 Focus on stability
 Community driven, Free,
but lack of official support
 Based on the same code
base with RHEL

16.
Fedora focus is on new technology
16
Fedora is the pioneer on new technology.
Fedora is also corporate supported by
RedHat. It feeds the RHEL product.
Everything that is considered to be stable
and useful for demanding enterprises,
might be moved in phases towards the
RHEL distribution.
If any new arch wanna get RHEL support,
it need to get Fedora support first.

17.
17
Part III
Fedora
on RISC-V
Bootstrap
Koji
Status
Supported Targets

18.
18
Saving time & effort for
maintaining Compilation scripts
For cross-compiling, we not only have to
port the software itself, but also need to
create and maintain the compilation scripts.
Keep It Simple, Stupid
some system software does not only have
the main bin file, but also includes a lot of
utilities. some of them will run in the
compiling stage, but some will run at
runtime. This increases the Compilation
scripts' complexity.
Target platform is powerful​
Another reason for using cross-compiling is
the Host's performance is much better then
the target. But now, we have QEMU support,
and Fedora is for 64-bit RISC-V which is
powerful too, moreover we have Koji.
Why native build

19.
The issue for a new architecture
19
Chicken And Egg Situation
Generally, one Fedora release is built upon
the previous release. But this can NOT be
done for a brand new architecture, because
we don't have a "previous release" at that
point.
Breakout
We must cross-compile enough
software/packages to "bootstrap" the new
architecture.
bootstrap

20.
Fedora bootstrap
20
Crosstools source code
Bootable basic rootfs
with native tools(gcc)
native rpmbuild
Mock

21.
21
One of them connects with SSD.
3 HiFive Unleasheds
fedora-riscv-x.gcc1xx.osuosl.org
managed by libvirt
(will add more by adding more servers)
142 QEMU VMs(on x86_64)
Main sever, repository creation and VMs
with backup(separate NVMe).
An x86_64 server
for all central infrastructure
Koji Build System
Koji builds RPMs for the Fedora Project and EPEL.
These Koji servers for RISC-V have been moved to the
hardware supplied by SiFive and WD at Fremont.

22.
Status
https://fedoraproject.org/wiki/Infrastructure/Mirroring
22
Active projects
Fedora 32/Rawhide,
including debuginfo,
debugsource and source
packages.
Repositories
https://dl.fedoraproject.org/pub/alt/risc-v/
https://mirror.math.princeton.edu/pub/alt/risc-v/
https://isrc.iscas.ac.cn/mirror/fedora-riscv/
Fedora Developer
Image
has extra packages installed for
developers, all common editors,
RPM tools, building tools, koji
stuff, etc.
GNOMEMinimal

23.
23
Fedora Images can run on the libvirt/QEMU
with graphics parameters (Spice).
Virtual: QEMU and libvirt/QEMU
Fedora GNOME Image can run on SiFive
Unleashed(with Expansion Board, PCI-E
graphic Card & SATA SSD.)
SiFive Unleashed
Supported Targets

24.
24
Fedora GNOME on SiFive Unleashed

25.
25
Fedora Images can run on the QEMU and
AndeShape FPGA board
QEMU for AndeStar V5 &&
AndeShape Development Platform ADP-XC7KFF676
Fedora Developer Image can run on ICT FPGA
Cloud development platform (with PCI-E SSD
and graphic Card)
ICT Development Platform
Tested Targets

26.
Fedora on RISC-V
26
From www.codasip.com
We would like to support more targets based on standard RISC-V Spec.

27.
Summary
27 Info Source:
Most of info comes from Richard Jones and his weblog: https://rwmj.wordpress.com/
RISC-V Koji maintainer: David Abdurachmanov
rpmbuild on RISC-V
by Richard Jones
August 10,
2016
The 2nd bootstrap
for Fedora 27
as the final preparation
Jan 29 ,
2018
Koji
For RISC-V build farm
April 15，
2018
The 1st bootstrap
for Fedora 25
as the first trial.
October 15,
2016
The 3rd bootstrap
for Fedora 28
as the final bootstrap
March ，
2018
Graphic Desktop is enabled
on a real RISC-V Hardware
Aug ，
2018
Red Hat
Join RISC-V
Foundation
Jul，2019
Since Fedora has an upstream first policy and it also applies to Fedora/RISC-V.
We need all the key patchsets for toolchain, Linux kernel and glibc to be merged, then we can do the final bootstrap on RISC-V.
IBM is a Founding member
of Foundation

28.
28
Part IV
Specs
UEFI
TODO
Industry standard
RISC-V server/PC
Please try Fedora 31 for RISC-V development

29.
Learn from other architectures
29
SBSA/SBBR/ACS...

30.
We need some specs for RISC-V server/PC
30
<RISC-V PC/Server Base Boot Requirements>
like the SBBR
• Define minimal firmware platform
• Enables mainstream general purpose OS
<RISC-V PC/Server Base System Architecture>
like the SBSA:
• Define minimal architectural features
• Define minimal server SoC features
<RISC-V PC/Server Architectural Compliance Suite (ACS)>
like the ACS
• SBSA and SBBR verification
For Embedded system, we also need some specs, like EBBR of Arm.

31.
31
The good progress of RISC-V Firmware
HPE has posted their V3 patchset for review.
For Now, with V3 patchset, EDK2(+ OpenSBI) can run on
QEMU( >V4.1.5, -machine sifive_u -cpu sifive-u54 ) and
Real Hardware SiFive Unleashed.
Last year, HPE engineers have made Tianocore
successfully boot on SiFive Freedom U500 VC707
FPGA Dev Kit with OpenSBI integrated in edk2 RISC-V port.
Then they were busy on standardizing firmware spec：
SMBIOS 3.3.0 already released with new record type (type
44) added, CIM works were done as well with RISC-V
processor definitions.

32.
32
The Firmwares and extensions on RISC-V: next step
Also working on below specs：
 ACPI tables for RISC-V processor
 Evaluate the works done in RISC-V TEE WG for drafting
EFI Management Mode spec of RISC-V processor.
 specs for (H)ypervisor, (V)ector and (P)acked-SIMD
keep updating below specs to reflect the latest RISC-V
specs.
 UEFI spec
 Platform Initialization spec

33.
33
Part V
Development tools
Firmware
Fedora Image
Run Fedora on
RISC-V

34.
34
Since Fedora 29, you can just:
“sudo dnf install gcc-riscv64-linux-gnu”
you can get the relative package list by
“dnf list *-riscv*”
Cross compiler for RV64:
"Fedora Developer" Image has extra packages
installed for developers, including RPM tools,
building tools, koji stuff, etc.
You can use them just like on X86 machine.
Native compiler for RV64:
Toolchain
For Building RPM packages and Fedora Images, we only use native compilation.

35.
35
Since Fedora 29, you can just:
“sudo dnf install qemu-system-riscv”
But please install the latest version of them by
“sudo dnf copr enable @virtmaint-sig/virt-preview”
QEMU RPM for RISC-V
The upstream QEMU has supported most of
latest RISC-V spec and can work with latest
software for RISC-V.
Build QEMU from source code
QEMU
If you use dated QEMU(<v4.1.15), it will be incompatible with the latest RISC-V Software(like edk2).

36.
https://dl.fedoraproject.org/pub/alt/risc-v/repo/virt-builder-images/images/
36
VM Tools
You can quickly and easily build new virtual
machines to practice Fedora on RISC-V .
sudo dnf install libguestfs-tools-c
Fedora virt-builder:
a toolkit to manage virtualization platforms, like
creating new KVM, list the supported operating
system variants, and start/stop/remove a VM.
sudo dnf install virt-manager libvirt
The libvirt project:

37.
37
The DATED boot flow for Fedora on RISC-V(abandoned)

38.
The current boot flow for Fedora on RISC-V
38

39.
39
The current Build flow for firmware on RISC-V
1 2
1 2 3

40.
Acknowledgments
40
Alphabetical Listing by Company Name
Al Stone
Andrea Bolognani
Charles Wei
DJ Delorie
John Feeney
Mark Salter
Richard Jones
Alistair Francis
Anup Patel
Atish Kumar Patra
Mikael Frykholm
Stefan O'Rear
David Abdurachmanov
... and countless other individuals and
companies, who have contributed to
RISC-V specifications and software
eco-system!
Abner Chang
Gilbert Chen

41.
linkedin.com/company/red-hat
youtube.com/user/RedHatVideos
facebook.com/redhatinc
twitter.com/RedHat
Red Hat is the world's leading provider of enterprise
open source software solutions. Award-winning support,
training, and consulting services make
Red Hat a trusted adviser to the Fortune 500.
Thank you
41

42.
CONFIDENTIAL Designator
Steps to build firmware(OpenSBI/U-boot) for
Fedora Image on RISC-V platform
FYI
42

43.
Fedora bootstrap(aarch64 vs RV64)
43
Build
System
Stage AArch64 Stage RISC-V RV64
Host
（x86）
Simulator(ARM model)
1
a QEMU
QEMU b HiFive Unleashed
FPGA c Spike
1 Bootable Rootfs
2
a GNU cross-compiler toolchain
b Berkley Bootloader
3
a Linux kernel
b
basic rootfs
Target
(Native)
2 rpmbuild
Cross-compile and install
“rpm” packages & dependencies
install pre-build RPMs
rebuild RPMs from SRPMs natively
4
a install the new RPMs
b build stage4 image3 mock
RISC-V Autobuilder on QEMU
4
koji (builders)
Distribution bootstrap
5 Rebuild in koji
6 koji-shadow

44.
44
Development Info:
• Main Entrance:
https://fedoraproject.org/wiki/Architectures/RISC-V
• Instruction of installation:
https://fedoraproject.org/wiki/Architectures/RISC-V/Installing
Fedora Wiki pages For RISC-V
• Nightly build images: http://fedora.riscv.rocks/koji/tasks?order=-
completion_time&state=closed&view=flat&method=createAppliance
• dist-repos: http://fedora.riscv.rocks/repos-dist/
• SCM: http://fedora.riscv.rocks:3000/
Koji for RISC-V:
Domain Name：fedora.riscv.rocks
IRC
#fedora-riscv (FreeNode)
Fedora Main REPO for RISC-V:
https://dl.fedoraproject.org/pub/alt/risc-v/
Current stable Images (support SiFive Unleashed and QEMU out-of-the-box):
Fedora-Developer-Rawhide-20191123.n.0
Fedora-Minimal-Rawhide-20191123.n.1

45.
45
QEMU：u-boot.bin & fw_payload.bin
Cross compiler:
ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu-
make qemu-riscv64_smode_defconfig
make
<u-boot>/u-boot.bin
U-boot:
git://git.denx.de/u-boot.git
make PLATFORM=qemu/virt
FW_PAYLOAD_PATH=<u-boot_source>/u-boot.bin
<opensbi>/build/platform/qemu/virt/firmware/fw_payload.bin
OpenSBI:
https://github.com/riscv/opensbi.git

46.
46
Test on QEMU
qemu-system-riscv64
-smp 8 -m 2G -machine virt -nographic
-bios fw_payload.bin
-device virtio-blk-device,drive=hd0
-drive file=Fedora-Developer-Rawhide-20191030.n.0-sda.raw,format=raw,id=hd0
-object rng-random,filename=/dev/urandom,id=rng0
-device virtio-rng-device,rng=rng0
-device virtio-net-device,netdev=usernet
-netdev tap,id=usernet,ifname=tap0,script=no,downscript=no
-serial telnet:localhost:7000,server
QEMU
Please set up the network on your host machine correctly for “-netdev”

47.
47
Test with Libvirt
virt-install --name fedora-riscv64 --arch riscv64 --vcpus 8 --memory 4096
--os-variant fedora30
--boot loader=/var/lib/libvirt/images/fw_payload.bin
--import --disk path=/var/lib/libvirt/images/Fedora-Developer-Rawhide-
20191030.n.0-sda.raw
--network network=default
--graphics spice
virt-manager
Libvirt
Please copy the firmware and image to the right directory and set up the correct permission of these files

48.
48
HiFive Unleashed：u-boot.bin & hifive-unleashed-a00.dtb
Cross compiler:
ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu-
make sifive_fu540_defconfig
make
/u-boot.bin
U-boot
#in Linux kernel tree (5.3-rc+)
make defconfig
make dtbs
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dtb
DTB
make CROSSCOMPILE=
/fsbl.bin
freedom-u540-c000-bootloader(Native build on QEMU, currently)
https://github.com/sifive/freedom-u540-c000-bootloader

49.
49
make PLATFORM=sifive/fu540
FW_PAYLOAD_PATH=u-boot.bin
FW_PAYLOAD_FDT_PATH=<linux source>/arch/riscv/boot/dts/sifive/hifive-
unleashed-a00.dtb
/build/platform/sifive/fu540/firmware/fw_payload.bin
OpenSBI
HiFive Unleashed：fw_payload.bin
Cross compiler:
ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu-

50.
50
HiFive Unleashed: Flash into uSD(fsbl/u-boot)

51.
51
HiFive Unleashed: Flash into uSD(Fedora Image)
$ sudo virt-builder
--source https://dl.fedoraproject.org/pub/alt/risc-v/repo/virt-builder-
images/images/index
--no-check-signature
--arch riscv64
--format raw
--hostname testing.riscv.rocks
--output /dev/sdc
--root-password password:fedora_rocks!
fedora-rawhide-developer-20191123.n.0
$ sudo sync
Flash Fedora Image

52.
52
EDK2
REPO: https://github.com/changab/edk2-staging-riscv
branch: RISC-V-V2-v3
SiFive U540：EDK2 Soruce
edk2-platform(submodule of edk2)
REPO: https://github.com/gilbert225/edk2-platforms
branch: devel-riscv-v2-PATCHv5

53.
53
Build commands:
cd $(UEFI_SRC_DIR)
git submodule init ；git submodule update
#make sure that you got opensbi submodule
export PATH=$(CROSS_TOOL_DIR_RV64):${PATH}
export GCC5_RISCV64_PREFIX=riscv64-linux-gnu-
source ./edksetup.sh --reconfig
make -C BaseTools/
build -a RISCV64 -t GCC5
-p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
SiFive U540：EDK2 build procedure

54.
54
HiFive Unleashed: Flash into uSD(fsbl/edk2)
qemu-system-riscv64 -cpu sifive-u54 -smp cpus=5,maxcpus=5 -m 4096 -machine
sifive_u -nographic -bios U540.fd -serial telnet:localhost:7000,server
QEMU(latest, >4.1.15)