System Architecture Exploration Training Class

TRAINING:
SYSTEM ARCHITECTURE EXPLORATION
Deepak Shankar
Founder
Mirabilis Design Inc.
Email: dshankar@mirabilisdesign.com

Logistics of the Webinar
2
To ask a question, click on Cloud Chat sign and type the
question. Folks are standing by to answer your questions.
There will also be a time at the end for Q&A

Support Resources
Application and support engineers at info@mirabilisdesign.com
VisualSim Software download
Training videos:
◦ Complete training: https://www.youtube.com/playlist?list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1
◦ Foundation Tutorial:
https://www.youtube.com/watch?v=0e1LVYU26rc&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=3
◦ Flow Control and Network Modeling:
https://www.youtube.com/watch?v=oH2C0_ET5qY&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=4
◦ Real time applications:
https://www.youtube.com/watch?v=96ro8fpf2aQ&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=5
◦ Power modeling:
https://www.youtube.com/watch?v=n4VudSX3Wjo&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=6
◦ Cache Tutorial:
https://www.youtube.com/watch?v=gOzkYcpU3c4&list=PLizKwf7N88at70EwhqvFq_zDaLkoQEKg1&index=7

Agenda- Day 1
Introduction to VisualSim
Methodology for different applications
Analysis using pre-built models for hardware, software, semiconductor and networking
Basic training on VisualSim GUI and data structure
Traffic generation
Behavior modeling
Queues, delays, schedulers and preemption
Statistics, plotting

Agenda- Day 2
Review the basics from Day 1
Answer questions on the take-home tutorials
Discussion on Scripting and Programming
System Hardware components
Semiconductor Components
Custom Development

Company Milestone
VisualSim Online
18 companies
32 universities
VisualSim 3.0
HW Modelling
35 customers
2003
Company
Incorporated
2005
First Engagement
with HP
2008
VisualSim 1.0
2010
10th Customers
2011
Stochastic
modeling
20132015
2018
New VisualSim
50th Customer
2019
Document generator
250 products built
2020
Failure analysis
ISO/DO/IEC
Target- 70 Customers

Mirabilis Design Offering
VisualSim software with libraries
Quickstart includes training and ongoing model
consulting- user builds the blocks and systems
Modeling services to develop custom library
components- user assembles the models
Modeling Services to develop custom libraries and
models. User conducts parameter study
Modeling services to develop model,
analyse and provide architecture feedback

Products Developed using VisualSim
Market opportunity is huge because of the breath of applications

Application of VisualSim
◦ Mapping algorithms on integrated
and distributed systems
◦ Architecting processor, hardware
accelerator and memory/cache/IO
◦ Resource requirements for software
task graphs
◦ Designing protocols, firmware,
network topology and buses
11
Performance
Analysis
Power
Exploration
HW-SW
Partitioning
Hardware
Software
Network
Libraries
Discrete-Event
Simulator
Graphical
Validate and optimize your design quickly and accurately

Timing
Throughput
Security
Capacity
Planning
Power
Planning
Buffer
Usage
Resource
Efficiency
Failure
Analysis
The Way Forward using System Simulation
and VisualSim Architect
Eliminate all surprises prior to development

Largest System Level IP
Custom Creator
Support
Power
Listeners, Debuggers,
Tracers, Assertions
Table, Energy harvesters,
Battery
Distribution, Sequence,
Trace file, Instruction
profile
Traffic
Reports
Latency, Throughput,
Utilization, Ave/peak
power, Statistics
RTL-Like
RTOS
Clock, Wire-Delay,
Registers, Latches and
Flip-flop, ALU and FSM,
Mux, DeMux, Lookup
table
Generic RTOS, ARINC
653, AUTOSAR
AMBA (AHB/ APB/ AXI), Corelink,
CoreConnect, Network-on-Chip,
Virtual Channel, DMA, Crossbar,
Serial Switch, Bridge
SOC
Board-
Level
VME, PCI/PCI-X/PCIe, SPI 3.0,
Rapid IO, 1553B, FlexRay, CAN-
FD, AFDX, TTEthernet, OpenVPX
Processors ARM (M-Series), ARM (A8, A72, A53,
A76), RISC-V, Nvidia- Drive-PX,
Configurable GPU, DSP, mP and mC,
PowerPC, X86- Intel and AMD, DSP- TI
and ADI, Others: MIPS, Tensilica,
Renesas SH, Marvel
Stochastic
Queue ,Time
Queue, Quantity
Queue, System
Resources,
Scheduling
algorithms
Script language,
600 RegEx, Task
graph, Use cases,
Programming
languages
Storage Flash, NVMe, Disk
Memory Controller, MPMC,
Fibre Channel, Fire Wire
Switched Ethernet, Resilient Packet Ring,
RP3, Wireless LAN 802.11, Bluetooth and
PAN, Spacewire, Audio-Video Bridging,
IEEE802.1Q
Networking
Memory
• Memory Controller, SDR, DDR
DRAM 2,3,4, LPDDR 2, 3, 4,
HBM, HMC, QDR, RDRAM
FPGA Xilinx- Zynq, Virtex, Kintex,
Intel-Stratix, Arria,
Microsemi- Smartfusion,
Programmable logic
generator, External links to
I/O, Network and Memory
Completeness of Library is Key to Rapid Prototyping

Case Studies
• Processor vs FPGA
• Create a table of preferred
parts based on battery
capacity, orbital activities,
sensor rates and error
conditions
• Compared FPGAs, DSP and
ARM-based processor
families
• Established a list of criteria
to select the board for each
spacecraft sub-system
Processor Organization
• Autonomous Driver Assistance System
• Evaluate the behavior of
different software
configurations on highly
distributed networks
• Provide the OEM
recommendations on
assignment of LIDAR/RADAR
and ECU to load software
• Measure the response times for
braking and collision avoidance
Automotive Organization
• Designing Network and
Processing ASICs and Boards
• Create a front-end systems
engineering process for all
Defense ASICs
• Run use cases with different
combination of processor,
memory controller and
backplane ASIC
• Provide customers with
expected performance
metrics by migrating to
latest platform
Defense Organization

Overview of System Modeling
Architecture Exploration
◦ Optimize and validate the system specification
Performance Analysis
Power Measurement
Functional Correctness
Failure Analysis
Making Better Quality Products

Application Mapping on Platform
Complex behavior
- input stream
- data dependent behavior
Contention
- limited resources
- scheduling/arbitration
Interference of multiple applications
- limited resources
- scheduling/arbitration
- anomalies
I/O
DSP
CPU1
CPU2
task1 task2 task3 task4
Scheduling software tasks using limited resources

Determine Impact of Trade-off Decisions
System with faster Bus is slower in places
Unpredictable System Response

Types of High-Level Modeling
Flow Control and Functional Analysis
Task Graphs
SoC Timing and Cycle-Accurate
Mapping Software Application onto Hardware Platform
Failure Analysis
Networked IoT System with RISC-V

Network System with Flow Control

VisualSIm Modeling of Flow Control

VisualSim Model of the Task Graph

SoC/Processor Design
Target
Power < 1.0W
Number of frames in 20 ms > 13K
Three Explorations
1. All tasks deployed in Software
2. Some tasks migrated to Hardware accelerators
3. Adding power management

IP-based Modeling in VisualSim
Processor Bus
Topology
Memory
Controller
Hardware
Accelerators
Power
management
Use Cases

Reports
SW
SWSW
SW
HW HW
HW HW

Software Modeling
Mapping of software tasks onto hardware platforms
Software can be defined as
◦ Task Graph
◦ Source code integrated into the flow
◦ Instruction sequence or statistical model based on execution on real hardware
◦ Trace file from existing system
GEM5 integration to co-simulate with software
◦ Run the OS and Software on GEM5 ISS of RISC-V, ARM or x86
◦ VisualSim runs the SoC and the system

Solving the Design Challenges –
Failure
• Virtual Bus ( VB ) can be CAN , FlexRay etc..
• ECU’s have Preemptable Runnable Task Queues
• T_n’s ( Runnable Task groups ) are assigned to
ECU’s

Evaluating the Impact of Failures
Without Faults
With Faults

Networked IoT System with RISC-V
Device 1
AFE
RISC-V
core
BLE
Radio
Transceiver
Network
Hub Data
Center

IoT model
• Evaluations
• Power consumption of each device
• Optimal HW and SW configuration
to meet the end-to-end
application timing deadline from
IoT to the data center
• Performance with Big data and
fast data workloads

TRAINING: BASICS OF VISUALSIM
Deepak Shankar
Founder

Documentation and Support
Installation Guide
Getting Started
Demo models for
Libraries and
Applications
Quick Reference Guide
List of Libraries and
Regular Expression
Tutorials
List of Training
Videos
Listing of
Errors
OnlineSupport
Portal

Parts of the Block Diagram
3. Libraries
5. Parameters
6. Variables
11. Use cases Behavior
8. Traffic
7. Setup
4. Annotations
2. Toolbar
1. Menu-Bar
10. Architecture
9. Report
12. Mapping

TRAINING: UNDERSTANDING PARAMETERS, DATA
STRUCTURES AND VARIABLES
Deepak Shankar
Founder

Parameters, Variables, Fields
Parameter
◦ Constant throughout a
simulation
◦ Link top-level parameter to
blocks
◦ defined in the model window or
a block
Usage
◦ Sweep through parameter values
Variables
• Variable is a single value
register or memory location
• Can vary during the simulation
• Can be accessed by all blocks
•Types
Local- used in current window
Global- available in full model
Block- available in Script and
ExpressionList blocks
Data Structure Field
• Carried with the packet,
request or transaction
• Dynamically create and
remove fields
•Usage
Can be signal, protocol field or
simulation information
Expression results can be
stored in the Fields
Local- used in current window

ExpressionList- Use Case for Parameter, Data Structure Field or Variable
• If value is used as constant throughout the simulation, then it is a Parameter
• If the value must be modified to run iterations, then best to maintain the parameter at the top-level
• If value is specific to this packet, image or signal, then insert in Field
• If value will change during simulation and is required in multiple model locations, then use a Variable

TRAINING: TRAFFIC, PROCESSING AND REPORTING
Deepak Shankar
Founder

Traffic
• Input to the system that triggers the components to perform a function
• Traffic definition requires:
 Time distribution between generated events
 Data Structure - packet, frame, IC pins etc
 Fields: Define standard data headers/ control such as data, address, source, destination,
priority, ToS etc
 Initial values for the fields of the Data Structure

Trace File Based
• Use a trace dump from the network, cache, memory or processor
pipeline
• Traffic Reader block
• The expected file is
 ASCII text
 Any number of columns and rows
 Each column has the first row with header and the second row with types
 The header name is the field name
 Any number of rows and columns are supported

Processing
•Data Flow
Describe actions based on expressions
Results stored in fields if data frame specify actions or variables if
required by the whole model
•Control Flow
ExpressionList used to deicide if-else; while, and case-switch are used
•Delay
Simple delay before output
•Virtual Flow
Direct data to other parts of the model using named connections and
wireless
Use Mux and Demux blocks for creating instruction decodes, protocol
switching, broadcast etc.

ExpressionList Block
Can add any number of input and output ports
All input ports must be available for the block to execute
All input data vales are saved in queues associated with each port
Code is executed in sequence
No branch, loops or jumps in the code
◦ Exception: Single line if-else statement
Output controlled by Condition

Result
Statistics
◦ ResourceStatistics
◦ Statistics blocks to collect statistics at intermediate points
Plot data
◦ Bar, Histogram or XY plots
◦ Special viewers- Matrix, Image, MPEG and speakers
Collect data
◦ Write to screen or to files (Excel, text or XML)
Assertions or tests
◦ High/low value for scalar
◦ Conditional model activity
◦ Model termination

Time Data Plotter
• Plot double values against simulation time
• View or save the results of the simulation in a XY
format.
• Used to depict latency, throughput and other
variables that vary against time.

Histogram
•The plotter accepts data on the input and plots them as a
histogram.
•View the plot in real-time or save for future viewing.

Text Display
•Output to text the data structure and statistics
• The input type can be of any type.
•Can be set to Save/View from Post Processor
•Cannot be viewed from the Post Processor

TRAINING: RESOURCE TO DEFINE HARDWARE AND
SOFTWARE PLATFORM
Deepak Shankar
Founder

Resources
Two types
◦ Time
◦ Quantity
Time can be four types-
◦ Delay known in advance- Server
◦ Delay not predictable in advance- Queue
◦ Request from multiple flows or actions- System_Resource
◦ Request needs extended processing- System_Resource_Extend
Level of details
◦ Stochastic: Delays, Quantity and Buffering
◦ Timing-Accurate: Processor, Memory and RTO

Quantity Based Resources
• Represents an integer quantity of elements which can be
allocated, freed, created or consumed
• Provides queuing if request cannot be fulfilled
• Passive Resources
• Resource units represent something that must be possessed
before a transaction (DS) can continue
• Full Library -> Resources - > Quantity-Based

Server
• Active Resource
• Advanced Timed_Queue_N_Priority
• Define multiple queues + time delay
• DataStructures queued in FIFO or LIFO order
• Special operation mechanism – SLOT
• Resources - > Server

Queue
• Active Resource
• Multiple independent Queues
• Requires a pop to send DS on the output port
• Delay in Queue is not predictable prior

System Resource Overview
Blocks
◦ Behavior: Mapper, SoftwareMapper, DynamicMapper
◦ Architecture: SystemResource_Extend, SystemResource
◦ Notify: SystemResource_Done
Concept
• Multiple threads map one or more SystemResources
 Can be located anywhere in the model flow
 Dynamically mapped based on DS field or parameter
• SystemResource_Done calls back the SystemResource_Extend to
release for next task during refinement

Differences
Features System Resource SystemResource_Extend
Preemption Yes No
Hierarchical Yes No
Extended Task Processing No Yes
Non – Blocking No Yes

Statistics
•Generated Using
 Resource Statistics
 RegEx Function
 Array Lookup
• Resource Statistics
 gives Buffer Occupancy, Delay, Number of Transactions
entered, exited, rejected
• Array Lookup
 eg: Length_A = Queue_Length(1) -> This gets the length of
Queue Number 1

Experimenting with
Different System Options
Model 1:
◦ Feeding traffic to a processing resources
◦ Feeding traffic to a bus or network resource
◦ Multi-core and Multi-channel design
Model 2:
◦ Multiple applications sending request to a single processor core
◦ Making one software task to be Mutual Exclusion and make the Processor to be preemptable
◦ Adding power analysis to the design

Home Project
Review tutorials in VisualSim
Attempt the following three tutorials
Practice tutorials for this Training
Foundation Tutorial- Part 1
Performance Modeling- Flow Control
Network Modeling- Exploring Network Usage
Architecture Modeling- Cache Tutorial

TRAINING: END OF TRAINING DAY 1
APRIL 13
Deepak Shankar
Founder

TRAINING: TRAINING DAY 2
APRIL 15
Deepak Shankar
Founder

Logistics of the Webinar
62
To ask a question, click on Arrow to the left of Chat and
type the question. Folks are standing by to answer your
questions. There will also be a time at the end for Q&A

ANY QUESTIONS?
Deepak Shankar
Founder

Recap of Day 1
Covered the types of models in VisualSim
Understand the basic methodology in VisualSim
Studied the introductions to Traffic, Analysis, Resource, Processing and Power consumption
Different types of Resources and their usage

TRAINING: POWER MODELING
Deepak Shankar
Founder

Introduction to Power Modeling
Power modeling at the system-level is necessary because power-
based problems are one of the primary causes of costly-respins
◦ Heat dissipation
◦ Low battery life
◦ Lack-luster power-performance trade-off
Power-based and time-based system requirements must be evaluated
in the same environment
Examples of power investigations at the system-level
◦ Dynamic Voltage and Frequency Scaling (DVFS)
◦ Power control logic for SOC power domains
◦ Power gating
◦ SOC architecture comparisons based on power

Block Functional and Power
Mode Diagrams
Function 1
Function 2
Function N
Block Functional Diagram
Block Power Mode Diagram

Statistics
• Instantaneous Power (port)
• Average Power consumed (port)
• Power Dissipated (port)
• Instant (powerCurrent) and total power consumed
(powerCumulative) by device

TRAINING: SCRIPTING
Deepak Shankar
Founder

Programming Logic, Arbitration,
Scheduler
Script language is integrated into the simulator and block diagram
Can add any number of Input and Output part
All inputs are stored in a single queue in order of arrival
◦ Exception: Virtual connections get highest priority
Top section define the variable
Right below will be any code that needs to execute without any input trigger
When input arrives, the code beginning from LABEL:BEGIN will start executing
The currently executing transaction is stored in a variable called port_token.
Note: Multiple transaction can be executing in the code but only one transaction will be active

RegEx, Keywords and Functions
LABEL:BEGIN
◦ Code works lik regular C code
◦ Includes special functions called RegEx
◦ Special keywords are available QUEUE, EVENT, TIMEQ, SEND
Virtual Connections
◦ SEND to another Script block or IN block
◦ SEND to another LABEL in the current code to create a separate Thread
Parameter, Variables and Field
◦ Can be accessed from the same BDE window
◦ Variables can be defined on the top of this code. Also, use Local and Global variables
◦ Add new fields, remove field or update existing field in the Port_Token
◦ Can read content in Queue, Server, SystemResources and Hardware blocks

TRAINING: MODEL DEBUGGING
Deepak Shankar
Founder

Debuggers
•Breakpoints
•Stop & Restart
•Trace Tracking
•Animation
•Dynamic Plotters
•Listen to Port
•Listen to Block
•Listen to Simulator
•Digital Debugger
•Error Messages
• Batch Mode Simulation
• Power Timing Diagram
• Variable Dump
• RegEx
• Script Debugging
• Data Structure Fields
• AutoSave
• Logger for Verilog and SystemC
• Plotters & Text Display

TRAINING: SUPPORT INFRASTRUCTURE
Deepak Shankar
Founder

Database
• Lookup table for doing searches
• Used as Routing Table
• Main features of the Database block:
 Read
 Write
 Remove

Hierarchical Blocks
• Grouping a set of functional blocks
that combine to define a function or
device

Class
• A class is a master version of the block.
• Class is an XML sub-model
• Can be instantiated multiple times in the model.
• Changes made to class block are replicated to all
linked instances
• All sub-models need a Simulator

Dynamic Instantiation
• Creates multiple instances of itself during the
preinitialize phase of model execution.
• Each instance of this block behaves exactly like a
Hierarchical block.
• Helps significantly in building large designs where the
model structure scales.

TRAINING: APPLICATIONS OF THE VISUALSIM
BLOCKS
Deepak Shankar
Founder

Failure Analysis
Hardware Failure: Loss of processing cores, limited storage,
reduced or loss memory device or bus overload/incorrect signals.
Software failure: Resource starvation, deadlocks, data overwrite.
Network failure: Network Congestion, misconfiguration, link loss
and network errors.
RTOS failure :Unable to achieve real-time deadlines, malicious
change in schedule table, and executes beyond time slots.
Power Failure: Both reduced and full power failure. Slower
processing speed, limited number of resources can be executing
concurrently.

Functional Diagram of a Radar System

Architecture Design Challenges
What should be the hardware configuration for this application?
Does the processing meet the timing deadline?
Which tasks consume the most time and memory bandwidth?
Can I modify the sequence or change the prior or create an offset that would get better
performance without changing the hardware
What is the power consumed by the system?
Can I increase the number of sensors or handle larger data sizes?
What is the individual processing and resource capacity for each task- input to the developers?
What are the corner cases for additional test development?

Comparing the Architecture Options

Secondary PCI Bus, 64 Bit Up to 66 MHz
ADSP-TS201S
TigerSHARC DSP
DSP #1
512MB～1024MB
SDRAM
8片TSOPII54
QL5064
QuickLogic
64-bit Embedded
PCI Controller
ADSP-TS201S
TigerSHARC DSP
DSP #2
64-bit, 83.3 MHz DSP Cluster Bus 1
LINK
LINK
LINK
LINK
LINK
VirtexII-Pro
XILINX
LINK to
VirtexII-Pro
RocketIO
(4 Channels)
to VXS P0
Boot
Flash
peripheral
8-bit bus
QL5064 Peripheral
8-bit bus
DSP1 Ints&Flags
DSP2 Ints&Flags
DSP3 Ints&Flags
DSP4 Ints&Flags
QL5064 Peripheral
8-bit bus
ADSP-TS201S
TigerSHARC DSP
DSP #3
512MB～1024MB
SDRAM
8片TSOPII54
QL5064
QuickLogic
64-bit Embedded
PCI Controller
ADSP-TS201S
TigerSHARC DSP
DSP #4
64-bit, 83.3 MHz DSP Cluster Bus 2
LINK
Boot
Flash
peripheral
8-bit bus
LINK to
VirtexII-Pro
LINK to
VirtexII-Pro
LINK to
VirtexII-Pro
DSP 1 LINK
DSP 2 LINK
DSP 3 LINK
DSP 4 LINK
PCI 64/66
IPcore
PowerPC
405e
RS232接口
RS232
串行接口
to P2
PCI 64位/66MHz
PMC槽
Boot
Flash
Map Individual Functions to Hardware Units
LDS6527- Mercury Computer TI DSP based

Hardware Architecture Internals
LDS6527
DSP based

Multi-core BLE 5.0 SoC family with system
PMU (Power Management Unit )
Block Diagram
VisualSim Model

Network on Chip
Block Diagram
VisualSim Model

Multi-Bus SoC
Processor A
H
B
B
U
S
On Chip
Memory
A
X
I
B
U
S
Bridge External
Memory
DMA Display
control
System-on-Chip
Block Diagram
VisualSim Model

Assembling a System
Model 1:
◦ Assembling a system with AXI bus and with AHB and comparing the results
◦ Adding a PCIe to the input interface
◦ Distributing traffic from sensors and processing resources

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