Microprocessor

Charlton S. Inao
Professor Mechatronics
Defence University
Coolege of Engineering
Bishoftu, Ethiopia
Microprocessors and
Microcontrollers
WEEK 10-11

General Objectives
To explain and understand the following
concept:
1. System
2. Architecture
3. Instructions
4. Communication Interface
5. Microcontrollers
6. Memory, Input Output
7. Programming Applications

Microprocessor
• The central processing unit (CPU) is the "brain" of
a computer. It is the part of the computer which
interprets and carries out instructions from the
computer programs.
• Modern desktop computers use microprocessors:
complex integrated circuits containing millions of
transistors and other electronic components. The
microprocessor is mounted in a socket or slot on
the mainboard (motherboard) so that it can be
connected to other components.

Microprocessor Organization
• Although microprocessors are becoming increasingly complex, at root its
operation can be summed up as the repeated sequence of simple tasks:
Fetch an instruction; Decode the instruction; Execute the instruction.
• Each microprocessor recognizes a unique set of binary instructions which
have been predefined and stored permanently in the chip. When the CPU
receives an instruction it passes it to a unit known as the Decode unit
which contains a sequence of operations which must be performed to
complete the operation.
• The Decode unit passes the sequence of instructions to the Control Unit
which holds tiny programs known as microcode for each operation the
microprocessor had been designed to carry out.

ALU
• The actual work of the microprocessor is carried
out in the Arithmetic Logic Unit. Most of these
operations are in fact performed by addition. To
perform subtraction, the CPU first finds the
complement of the number to be subtracted and
then adds the two numbers. Multiplication and
division can be performed by carrying out
multiple addition or subtraction operations. To
compare two numbers, the CPU will subtract
them and then check to see if there is a
remainder, and so on.

REGISTERS
• In order to carry out its operations, the processor has
storage locations, called registers, for the numbers and
instructions it is operating on.
• For example, to add two numbers, the first number
mign be loaded into Register A, the second into
Register B and the result stored in Register C.
• To speed up the operations of the processor, the
Prefetch unit looks ahead in the program to find the
next instructions and preloads them into registers, to
cut down on time wasted waiting for the next
instruction.

Registers
• Most of the registers contain data/instruction
offsets within 64 KB memory segment. There
are four different 64 KB segments for
instructions, stack, data and extra data. To
specify where in 1 MB of processor memory
these 4 segments are located the processor
uses four segment registers:

• Code segment (CS) is a 16-bit register
containing address of 64 KB segment
with processor instructions. The
processor uses CS segment for all
accesses to instructions referenced by
instruction pointer (IP) register. CS
register cannot be changed directly. The
CS register is automatically updated
during far jump, far call and far return
instructions.

• Stack segment (SS) is a 16-bit register containing
address of 64KB segment with program stack. By
default, the processor assumes that all data
referenced by the stack pointer (SP) and base pointer
(BP) registers is located in the stack segment. SS
register can be changed directly using POP
instruction.
• Data segment (DS) is a 16-bit register containing
address of 64KB segment with program data. By
default, the processor assumes that all data
referenced by general registers (AX, BX, CX, DX) and
index register (SI, DI) is located in the data segment.
DS register can be changed directly using POP and
LDS instructions.

• Extra segment (ES) is a 16-bit register
containing address of 64KB segment, usually
with program data. By default, the processor
assumes that the DI register references the ES
segment in string manipulation instructions.
ES register can be changed directly using POP
and LES instructions.
• It is possible to change default segments used
by general and index registers by prefixing
instructions with a CS, SS, DS or ES prefix.

General Registers(A,B, C,D)
• All general registers of the 8086/8088microprocessor can be
used for arithmetic and logic operations. The general registers
are:
• Accumulator register consists of 2 8-bit
registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL
in this case contains the low-order byte of the
word, and AH contains the high-order byte.
Accumulator can be used for I/O operations
and string manipulation.

• Base register consists of 2 8-bit registers BL and BH,
which can be combined together and used as a 16-
bit register BX. BL in this case contains the low-order
byte of the word, and BH contains the high-order
byte. BX register usually contains a data pointer used
for based, based indexed or register indirect
addressing.
• Count register consists of 2 8-bit registers CL and CH,
which can be combined together and used as a 16-
bit register CX. When combined, CL register contains
the low-order byte of the word, and CH contains the
high-order byte. Count register can be used as a
counter in string manipulation and shift/rotate
instructions.

• Data register consists of 2 8-bit registers DL
and DH, which can be combined together and
used as a 16-bit register DX. When combined,
DL register contains the low-order byte of the
word, and DH contains the high-order byte.
Data register can be used as a port number in
I/O operations.
• In integer 32-bit multiply and divide
instruction the DX register contains high-order
word of the initial or resulting number.

Buses
• The microprocessor connects to the external
components of the computer via "buses": sets of
parallel conductors used to move data in the form
of electrical pulses.
• There are three types of buses: the data
bus carries the binary-coded information and
instructions;
• the address bus carries binary-coded numbers
which identify storage locations in main memory,
much like the postal code on a letter;
• the control bus carries timing signals, read-write
signals, interrupt requests and similar signals
between the microprocessor and external devices

• To manage the flow of data into and out of the CPU, two other units are
required: the Memory Management Unit, and the Bus Management Unit.
To summarize, the essential sections of a microprocessor are:
• Arithmetic Logic Unit: executes all logic and arithmetic operations as
specified by the instruction set
• Control Unit: contains the microcode that tells the ALU how to function.
• Decode Unit: translates instruction into control signals and microcode
directions then queues them until requested by the Control Unit.
• Prefetch Unit: queues instruction to assure that the microprocessor is in
continuous operation.
• Memory Management Unit: converts internal logic addresses into
external memory addresses.
• Bus Management Unit: manages the flow of information between the
microprocessor and data storage locations (main disk, CD-ROM, etc.) and
peripherals ( printer, monitor, etc.)

• Many of the refinements in modern
microprocessors are designed to improve
processor utilization and eliminate wasted clock
cycles. The addition of cache memory—high-
speed memory used for temporary storage of
instructions and data; multiple "pipelines" so that
more than one sequence of instructions can be
performed at one time; Branch-prediction units
which attempt to predict which branch of a
program will be executed next so that the cache
memory and extra piplines can be used
efficiently.

Microprocessor Specifications
There are several attributes of a microprocessor
which determine its power and capabilities:
• Width of external data bus in bits
• Width of address bus in bits
• Width of internal data bus in bits
• Cache Memory
• Clock Speed in Megahertz (MHz)
• MIPS (Million Instructions per Second)
• Power Consumption (Watts)

• External Data Bus
• The earliest microprocessors could handle data only in bytes (8 bits). As
the width of the data bus increases, the width of the data bus determines
how much information can be moved in or out of the processor in one
operation. It also determines the number and length of instructions which
can be used.
• Address bus
• The width of the address bus determines how much memory can be
addressed. The Intel 8086 had a 20 bit address bus. Since a 20 bit binary
number can represent 2 different numbers, the 8086 could address 1MB
of memory. The 386 and 486 could address 4GB of memory using a 32-bit
address bus, and the Pentium class processors have a 36-bit address bus
capable of connecting 64GB of memory.

Internal data bus
• The width of the internal data bus and the storage registers may differ from the
external data bus. The 386SX processor, for example had the same internal 32-bit
registers as other 386s, but only a 16-bit external bus. The Pentium class
processors, have an external 64-bit data bus, but the internal registers are only 32-
bit. For this reason the Pentium processors are referred to as 32-bit. Workstation
processors like the SPARC and Alpha are 64-bit, as is the next generation of Intel
chips, the Itanium.
Cache Memory
• As processor speeds increased, the speed of main memory (RAM) could not keep up. To minimize size and
cost, RAM memory uses Dynamic RAM (DRAM). Static RAM (SRAM) is much faster, but also more
expensive, so it is used in small quantities as a temporary storage location for data on the microprocessor
or closely connected to it. This high-speed memory is known as cache memory. It is operated by a cache
controller which attempts to identify which data or instructions will be needed next and load them into the
cache so that the processor will not have to stand idle while waiting for data to be retrieved from RAM.
• Today's microprocessors have cache memory in two levels, referred to as Level 1 (L1)and Level 2 (L2). The
L2 cache was originally mounted on separate chips outside the CPU, and operated at a lower speed than
the processor, but improvements in manufacturing technology have permitted the L2 cache to be moved
onto the processor chip where it operates at the same speed as the processor. In processors like the
Pentium III, an additional external bus operating at processor speed connects the L2 cache; this is known as
the backside bus in contrast to the frontside bus which connects to main memory.

Clock
Clock Speed
An oscillator mounted on the motherboard generates a series of electrical
pulses which the computer uses to synchronize the operations of its many
components. Each complete change in the signal, from positive to
negative and back again is known as a cycle, and the number of cycles per
second, or frequency, is measured in Hertz.
1 000 Hz = 1 kilohertz = 1KHz
1 000 000 Hz = 1 Megahertz = 1 MHz
1 000 000 000 Hz = 1 Gigahertz = 1 GHz.
The speed of the processor is often a multiple of the external bus speed: for
example a 500 MHz chip installed on a 100MHz mainboard will operate at
5x the bus speed.

Clock
The clock signals in microprocessor system are timing
waveforms that are used to synchronize the system’s
operation. Some microprocessors have an internal
oscillator to generate a clock signal. These
microprocessors require only external, passive timing
components. Other microprocessors do not have an
internal oscillator , and require more complicated
external circuitry to generate the clock waveforms.

MIPS
The clock speed does not relate directly to the speed at which the CPU processes
instructions. Early microprocessors required as many as 10 clock cycles to
complete a single instruction. Modern microprocessors with what is called
'superscalar" architecture have dual or multiple 'pipelines' so that more than one
instruction can be executed at once. Therefore, a more accurate measure of
processor speed is MIPS (Millions of Instructions per Second), although the
number of actual instructions processed rarely reaches the theoretical maximum.
Power consumption
Power consumption is an often overlooked measure of microprocessor performance.
Much of the power consumed is given off as heat, which must be dissipated, or it
will cause malfunctions. Low power consumption is also a critical factor in
extending the life of batteries in notebook computers.
The formula for power consumption is Volts x Amps = Watts. However, a decrease in
operating voltage also produces a drop in amperage (Ohm's Law). Older chips
functioned at 5 volts, while Pentium class chips operate in the range of 2 volts. This
results in a power saving of 84% without any other improvements in the circuitry.

Core I7 by Intel
• Intel is soon going to be bringing the fastest mobile processors, it's first of the Core-i7 for notebooks.
There are three processors in this list and all three are Quad-cores based on the
Nehalem microarchitecture.
The first two codenamed Clarksfield is a high-voltage 45 nanometer chip - Core i7-
720QM and 820QM.
•
The Core i7-720QM is clocked at 1.6 GigaHertz has 6 MegaBytes of Cache
while Core i7-820QM is clocked at 1.8 GigaHertz with 8 MegaBytes of Cache. Both
with a power consumption rating of 45 Watts.
•
The third and the fastest is the Extreme edition Core-i7 920XM which is clocked at
2 GigaHertz with 8 MegaBytes of cache and a power rating of 55 Watts.
It comes with Intel's TurboBoost technology which auto-overclocks the CPU to
increase performance.

Intel latest Microprocessor
• Core i7-920XM Specifications:
Speed: 2.00 GHz
Turbo Speed: 3.20 GHz
Cores: 4
Cache Size: 8 MB
Bus Speed: 1333 MHz
Power TDP: 55 W
Price: $1054

Instruction/Microprocessor Machine
Language(8080/8085)

Common Intel 8086 Instructions
MOV moving , loading or storing
OUT output
INT 3 interrupt the program
CALL calling from a subroutine
JMP
unconditional jump to a program
label or line
JNZ jump if NOT zero
RET Return to the program
END End of Program
DEC Decrease/decrement
INC Increase/increment

ROR Rotate Right
ROL Rotate LEFT
LEA Load Effective Address
TAB Table/tabulation
CMP Compare
CS Code Segment
DB Define Byte
DW Define Word

• Code segment (CS) is a 16-bit register
containing address of 64 KB segment with
processor instructions.
• The processor uses CS segment for all
accesses to instructions referenced by
instruction pointer (IP) register.
• CS register cannot be changed directly. The CS
register is automatically updated during far
jump, far call and far return instructions.
CODE SEGMENT

Example no . 1
All LEDs turned ON
1 ORG 100 H
origin a t 100 H, kit start
assigned address
2 MOV AL, 0FFH
move data FF in Accumulator
A,low. F= 15 in hexadecimal,
all are logic 1
3 OUT 53 H, AL
put the contents accumulator
to RAM kit address 53H
4 INT 3 interrupt or stop the program
F=15
(HEXADECIMAL)

1 ORG 100 H origin a t 100 H, kit start assigned address
2 TOP: MOV AL, φFFH
move data FF in Accumulator A,low. F= 15 in hexadecimal, all are
logic 1
3 OUT 53H, AL put the contents accumulator to RAM kit address 53H
4 CALL DLY calling a subroutine program for delay (DLY)
5 MOV AL, 00H move data 00( logic zero)(OFF) ,8 bit) for all 8 LEDs in Accumulator
6 OUT 53H, AL
putting the output of accumulator which is ALL OFF(logic 0), to to
address 53H
7 JMP TOP
8
9 DLY: MOV BL, 10 h a delay 10H is to be moved in accumulator BL
10 L1: MOV CX, , φFFFF H
loop1, Accumulator C (16 bit), complete logic 1 of 16 bit for
decrement timing
11 L2: LOOP L2 looping L2
12 DEC BL decrement Accumulator B, low part (BL)
13 JNZ L1
Jump no Zero, jump to L1 ( CX=FFFF) if not
zero..FFFF,FFFE,FFFD,FFFC,FFFB,FFFA…0000
14 RET RETURN
15 END END/Terminate /Stop program
16
Example No . 2
All lights ON and OFF with delay in between

Example No . 3
4 right most LEDs ON, then 4 leftmost LEDs ON,
alternatively
Example No. 3 4 right most LEDs ON, then 4 leftmost LEDs ON,alternatively
1 ORG 100 H origin a t 100 H, kit start assigned address
2
TOP: MOV Al,
φFh
move data 0F in Accumulator A,low. F= 15 in hexadecimal, 4 bits logic 0,4
bits logic 1
3 OUT 53h, Al put the contents accumulator to RAM kit address 53H
4 CALL DLY calling a subroutine program for delay (DLY)
5 MOV AL, , φFφh move data F0( logic zero)(OFF) ,8 bit) for all 8 LEDs in Accumulator
6 OUT 53H, AL
putting the output of accumulator which is ALL OFF(logic 0), to to address
53H
7 JMP TOP jump to label:TOP
8
9 DLY: MOV BL, 0Ah a delay 0AH (approximately 10 seconds) is to be moved in accumulator BL
10
L1: MOV CX, ,
φFFFF H
loop1, Accumulator C (16 bit), complete logic 1 of 16 bit for decrement
timing
11 L2: LOOP L2 looping L2
12 DEC BL decrement Accumulator B, low part (BL)
13 JNZ L1
Jump no Zero, jump to L1 ( CX=FFFF) if not
zero..FFFF,FFFE,FFFD,FFFC,FFFB,FFFA…0000
14 RET RETURN
15 END END/Terminate /Stop program

Example No. 4 (ROL)
Example No. 4 ROTATE LEFT(ROL)
ORG 100 H origin a t 100 H, kit start assigned address
: MOV Al, φ1 h
move data 0F in Accumulator A,low. To the right most LED going to
left most LED
TOP: OUT 53h, Al
put the contents accumulator to RAM kit address 53H, in the label
TOP
CALL DLY calling a subroutine program for delay (DLY)
ROL Al, 1
Rotate left(ROL),,in the incremental step of 1(sequence of 1 step
increment interval towards the left)
OUT 53H, AL
putting the output of accumulator which is ALL OFF(logic 0), to to
address 53H
JMP TOP jump to label:TOP
INT 3 interrupt or stop the program
END END/Terminate /Stop program
DLY: MOV CX,
0FFFFh
a delay counter starting value of FFFFh (complete or longest 16 bit
of logic 1)
is to be moved in accumulator CX(16 bit)
L1: LOOP L1
RET RETURN to the Start
END end of program
LEFT

Ex. No. 5 ROR( Rotate to the Right)
Example No. 5 ROTATE RIGHT(ROR)
ORG 100 H origin a t 100 H, kit start assigned address
: MOV Al, 80h
move data 80 in Accumulator A,low. F..From the left most LED to the
RIGHTmost LED
TOP: OUT 53h, Al put the contents accumulator to RAM kit address 53H, in the label TOP
CALL DLY calling a subroutine program for delay (DLY)
ROL Al, 01
Rotate left(ROL),,in the incremental step of 1(sequence of 1 step interval
towards the left)
OUT 53H, AL
putting the output of accumulator which is ALL OFF(logic 0), to to address
53H
JMP TOP jump to label:TOP
INT 3 interrupt or stop the program
END END/Terminate /Stop program
DLY: MOV CX,
0FFFFh
a delay counter starting value of FFFFh (complete or longest 16 bit of
logic 1)
is to be moved in accumulator CX(16 bit)
L1: LOOP L1
RET RETURN to the Start
END end of program

ROR bit increment progression
8 4 2 1 8 4 2 1
1 1 0 0 0 0 0 0 0 8 0
2 0 1 0 0 0 0 0 0 4 0
3 0 0 1 0 0 0 0 0 2 0
4 0 0 0 1 0 0 0 0 1 0
5 0 0 0 0 1 0 0 0 0 8
6 0 0 0 0 0 1 0 0 0 4
7 0 0 0 0 0 0 1 0 0 2
8 0 0 0 0 0 0 0 1 0 1
To the right direction

Programming a
Stepper Motor
Using 8086
Microprocessor

Programming a
Stepper Motor 90,
180, 360 degrees
Using 8086
Microprocessor

TRAFFIC LIGHT PROGRAM Lamp
Color
Annotation
ORG 100 H Origin address is 100H
TOP: MOV AL,14 H Green, Red Move the contents of 14 to accumulator Al ( low)
OUT 53 ,AL Output the content of Accumulator A in address 53
CALL DLY 2 Call out DELAY 2 (DLY 2)
MOV AL, 36H yellow –green/
Red Yellow
Move 36H to Accumulator A l
OUT 53H,AL Output in address 53H, the content of Accumulator (l)
CALL DLY 1 Call out subroutine CALL DLY 1
MOV AL,41 H Red, Green Move data 41H to Accumulator Al
OUT 53H,AL Output is sent to address 53H from Accumulator A
CALL DLY 2 Call Out Delay 2
MOV AL,63H Red Yellow
/yellow –green
Move the data 63H to Accumulator Al
OUT 53H,AL Output is sent to address 53H from Accumulator A(low)
CALL DLY 1 Call out subroutine DLY 1
JMP TOP Program jump or goes to label TOP
Two Way Traffic Light(8086)

DLY 2: MOV BL,40H Put the data 40H to accumulator B(low)
L1: MOV CX, OFFFFH FFFF complete hexa digit counter reference move into
accumulator C, X signifies 16 bit
L2: LOOP L2 Looping L2
DEC BL Decrement Accumulator B l
JNZ Jump No Zero
RET Return
END End the program
DLY1:MOV BL,OAH Put the data 0AH to accumulator B (low)
L3:MOV CX,OFFFFH FFFF complete hexa digit counter reference move into
accumulator C, X signifies 16 bit
L4: LOOP L4 Looping L4
DEC BL Jump No Zero
JNZ L3 Jump if No Zero
RET Return
END End the program

Two Way Traffic Light(8086)
TWO WAY TRAFFIC LIGHT SYSTEM(8086) bit assignment
8 4 2 1 8 4 2 1
1 0 0 0 1 0 1 0 0 1 4 H
2 0 0 1 1 0 1 1 0 3 6 H
3 0 1 0 0 0 0 0 1 4 1 H
4 0 1 1 0 0 0 1 1 6 3 H

Course Outline
Microprocessor Based Products
Programming Applications
New Developments
Microcontrollers VS microprocessor
Embedded microprocessor products
Criteria for microprocessor selection
Microcontrollers and Mechatronics

Microprocessor
Based Products
Toys/game console
Playstation/Xbox/Nintendos
Wii
Calculator
Traffic Light
Robot
Cellular Phone
Remote Controls
Machine Tools/Cutting/ Press
Speech Synthesizer
Infrared and Radar Systems
Missiles
Laser Guided Bombs
Airplane controller
PLC
Gasoline Station
Space Craft/Station
Submarine Control
Airplane/Aero Industry
Refrigeration and Aircon
control

• What is superscalar architecture?
• Superscalar architecture is a method of parallel computing
used in many processors. In a superscalar computer, the
central processing unit (CPU) manages multiple instruction
pipelines to execute several instructions concurrently during a
clock cycle. This is achieved by feeding the different pipelines
through a number of execution units within the processor. To
successfully implement a superscalar architecture, the CPU's
instruction fetching mechanism must intelligently retrieve and
delegate instructions. Otherwise, pipeline stalls may occur,
resulting in execution units that are often idle.
New Developments

Very long instruction word (VLIW)
• Very long instruction word (VLIW) describes a
computer processing architecture in which a
language compiler or pre-processor breaks
program instruction down into basic operations that
can be performed by the processor in parallel (that
is, at the same time). These operations are put into a
very long instruction word which the processor can
then take apart without further analysis, handing
each operation to an appropriate functional unit.

Multithreading
• Multithreading is designed to improve
performance by performing work using one or
more threads at the same time.
• multithreading is the ability of a central processing unit (CPU)
or a single core in a multi-core processor to execute multiple
processes or threads concurrently, appropriately supported by
the operating system. This approach differs from
multiprocessing, as with multithreading the processes and
threads have to share the resources of a single or multiple
cores: the computing units, the CPU caches, and the
translation lookaside buffer (TLB).

• Where multiprocessing systems include
multiple complete processing units,
multithreading aims to increase utilization of a
single core by using thread-level as well as
instruction-level parallelism. As the two
techniques are complementary, they are
sometimes combined in systems with multiple
multithreading CPUs and in CPUs with
multiple multithreading cores.

PREFETCHING
• instruction prefetch is a technique used in central
processor units to speed up the execution of a
program by reducing wait states.
• Prefetching occurs when a processor requests an
instruction or data block from main memory before
it is actually needed. Once the block comes back
from memory, it is placed in a cache. When the
instruction/data block is actually needed, it can be
accessed much more quickly from the cache than if it
had to make a request from memory. Thus,
prefetching hides memory access latency and hence,
it is a useful technique for addressing the memory
wall issue.

PIPELINE
A pipeline is a set of data processing elements
connected in series, where the output of one
element is the input of the next one. The
elements of a pipeline are often executed in
parallel or in time-sliced fashion; in that case,
some amount of buffer storage is often
inserted between elements.
• HTTP pipelining, where multiple requests are
sent without waiting for the result of the first
request.

• Computer-related pipelines include:
• INSTRUCTION PIPELINES, such as the classic RISC pipeline, which
are used in central processing units (CPUs) to allow
overlapping execution of multiple instructions with the same
circuitry. The circuitry is usually divided up into stages,
including instruction decoding, arithmetic, and register
fetching stages, wherein each stage processes one instruction
at a time.
• GRAPHICS PIPELINES, found in most graphics processing units
(GPUs), which consist of multiple arithmetic units, or
complete CPUs, that implement the various stages of common
rendering operations (perspective projection, window
clipping, color and light calculation, rendering, etc.).
• SOFTWARE PIPELINES, where commands can be written where
the output of one operation is automatically fed to the next,
following operation. The Unix system call pipe is a classic
example of this concept, although other

• A multi-core processor is a single computing
component with two or more independent
actual central processing units (called "cores"),
which are the units that read and execute
program instructions.
• The instructions are ordinary CPU instructions
such as add, move data, and branch, but the
multiple cores can run multiple instructions at
the same time, increasing overall speed for
programs amenable to parallel computing.
Multi core processing

• Manufacturers typically integrate the cores
onto a single integrated circuit die (known as a
chip multiprocessor or CMP), or onto multiple
dies in a single chip package.
• Processors were originally developed with only one
core. A dual-core processor has two cores (e.g. AMD
Phenom II X2, Intel Core Duo), a quad-core processor
contains four cores (e.g. AMD Phenom II X4, Intel's
quad-core processors, see i3, i5, and i7 at Intel Core),
a hexa-core processor contains six cores (e.g. AMD
Phenom II X6, Intel Core i7 Extreme Edition 980X), an
octa-core processor contains eight cores (e.g. Intel
Xeon E7-2820, AMD FX-8150).

• A multi-core processor implements multiprocessing
in a single physical package. Designers may couple
cores in a multi-core device tightly or loosely.
• For example, cores may or may not share caches, and
they may implement message passing or shared
memory inter-core communication methods.
• Common network topologies to interconnect cores
include bus, ring, two-dimensional mesh, and
crossbar.
• Homogeneous multi-core systems include only
identical cores, heterogeneous multi-core systems
have cores that are not identical.

• Just as with single-processor systems, cores in
multi-core systems may implement
architectures such as superscalar, VLIW, vector
processing, SIMD, or multithreading.
• Multi-core processors are widely used across
many application domains including general-
purpose, embedded, network, digital signal
processing (DSP), and graphics.
• The improvement in performance gained by
the use of a multi-core processor depends
very much on the software algorithms used
and their implementation.

Nehalem Microarchitecture
Nehalem (pronounced /nəˈheɪləm/[1]) is the
codename for an Intel processor
microarchitecture, successor to the Core
microarchitecture. Nehalem processors use
the 45 nm process. A preview system with
two Nehalem processors was shown at Intel
Developer Forum in 2007. The first
processor released with the Nehalem
architecture was the desktop Core i7,.which
was released in November 2008.

• Nehalem, a recycled codename, refers to a
completely different architecture from Netburst,
although Nehalem still has some things in
common with NetBurst.
• Nehalem-based microprocessors utilize higher
clock speeds and are more energy-efficient than
Penryn microprocessors.
• Hyper-threading is reintroduced along with a
reduction in L2, which has been incorporated as
L3 Cache which is usable by all cores. Nehalem
was replaced with the Sandy Bridge
microarchitecture, released in January 2011
• .

Sandy Bridge microarchitecture
• Sandy Bridge is the codename for a
microarchitecture developed by Intel beginning
in 2005 for central processing units in computers
to replace the Nehalem microarchitecture..
• Originally, implementations targeted a 32
nanometer manufacturing process based on
planar double-gate transistors.Subsequent
products, codenamed Ivy Bridge, use a 22
nanometer process. The Ivy Bridge die shrink,
known in the Intel Tick-Tock model as the "tick",
is based on 3D tri-gate transistors.

Ivy Bridge Microarchitecture
• Ivy Bridge is the codename for an Intel microprocessor
using the Sandy Bridge microarchitecture.
• The name is also applied more broadly to the 22 nm
die shrink of the microarchitecture based on tri-gate
("3D") transistors, which is also used in the future Ivy
Bridge-EX and Ivy Bridge-EP microprocessors.
• Ivy Bridge processors are backwards-compatible with
the Sandy Bridge platform, but might require a
firmware update (vendor specific).
• Intel has released new 7-series Panther Point chipsets
with integrated USB 3.0 to complement Ivy Bridge.

Haswell Microarchitecture
Haswell will be the first processor to be designed from
the ground up to fully optimize the power savings and
performance benefits from the move to 3D or tri-gate
transistors on the improved 22 nm process node.
Performance
Compared to Ivy Bridge (expected):
At least 10% CPU performance increase.
Double the performance of the integrated GPU.
Technology
A 22 nm manufacturing process.
3D tri-gate transistors.
A 14-stage pipeline (since the Core microarchitecture)

• A microcontroller (or MCU, short for microcontroller
unit) is a small computer (SoC) on a single integrated
circuit containing a processor core, memory, and
programmable input/output peripherals.
• Program memory in the form of Ferroelectric RAM,
NOR flash or OTP ROM is also often included on chip,
as well as a typically small amount of RAM.
Microcontrollers are designed for embedded
applications, in contrast to the microprocessors used
in personal computers or other general purpose
applications consisting of various discrete chips.

• Microcontrollers are used in automatically
controlled products and devices, such as
• automobile engine control systems,
• implantable medical devices,
• remote controls,
• office machines, appliances,
• power tools,
• toys and other embedded systems.

By reducing the size and cost compared to a
design that uses a separate microprocessor,
memory, and input/output devices,
microcontrollers make it economical to
digitally control even more devices and
processes. Mixed signal microcontrollers are
common, integrating analog components
needed to control non-digital electronic
systems.

Microcontroller
VS
Microprocessor

Embedded Products Using
Microcontrollers

8 bit Microcontrollers
• Motorola -68HC08
• Intel -8051
• Atmel -AVR
• Zilog- Z8
• MicrochipTechnology -PIC

Mechatronics and
Microcontrollers

Microprocessor

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