This is to prepare training course material for new onboard fellow workers who interest in reliability analysis technique of semiconductor IC. Some irrelevant parameters, names, dates, and details have been removed for better understanding and focus on key considerations.In this report, a lot of attention is given to internal qualification than RA Lab operations. In this report, I put crucial points to remind myside during the time I have ever working alone and supports from third party laboratories and test program compilers.

1. preconditioning test, high temperature storage test,
thermal shock, temperature cycling, unbiased,
accelerated moisture resistance, steady state
temperature humidity
CH Shen
沈志豪
RELIABILITY QUALIFICATION
ACCELERATED ENVIRONMENT STRESS TEST
QUALIFICATION FOR INTEGRED CIRCUIT

2. The quote I like the most about self-development is:
“I think it’s very important to have a feedback loop, where you’re
constantly thinking about what you’ve done and how you could
be doing it better.” – Elon Musk, Entrepreneur

3. 1.Preconditioning test (MSL3)
apply for all kinds of package [exclude PDIP & BCC]
Test procedure:
1. Initial electrical test
2. Initial acoustic microscopy
3. 40X optical microscope inspection
4. Five temperature cycles≦-40℃ to ≥ 60 ℃
5. Bake the device 24 h at min.125 +5/-0 ℃
6. Moisture soak, 30 ℃, 60%RH, 192 h
(85 ℃, 85%RH, 168 h?)
7. Reflow (3) cycles
8. Flux, clean and dry
9. Final electrical Test
10. Final acoustic microscopy
basic note:
*1 e.g. datasheet values, test spec, etc.
*2 select correct transducer for SAT.
SAT method for specific application will be
discussed in my IC failure analysis slides.
*3 meet outgoing quality criteria
*4 TCT to simulate shipping condition
*5 Bake to remove all moisture from the
package so that it will be “dry”
*6 moisture soak started within 2 h of bake.
*7 the time between reflows min 5 minutes,
max 60 minutes.
*8 not for BGA, LGA

4. 1.1 Preconditioning test
Temperature cycling
Perform 5 cycles of temperature cycle to simulate
shipping condition. A~I, L~N defined in table 1 are
acceptable. this step is optional based on product.

5. 1.2 Preconditioning test
Moisture Soak
• If we know the activation energy for moisture diffusion of these
package materials, then the accelerated equivalent is an option.

6. 1.3 Preconditioning test
• Thin, small volume SMD package reach higher body temperature
during reflow soldering to board than larger packages.
Reflow temperature

7. 1.4 Preconditioning test
Reflow time: >15min; <4 hours (if cannot be met: re-bake & re-soak).
Reflow temperature
pb-free package Tc 260℃ ;Tp 30sec
supplier: > Tc 260℃ ; the time above 255℃ must be exceed 30sec.
user: < Tc 260℃ ; the time above 255℃ must NOT exceed 30sec.

8. 1.5 Preconditioning test
If Tc is 260 ℃ and Tp is 30sec, this means supplier (user) peak
temperature must at least (not exceed) 260 ℃. the time above 255℃
must at least (not exceed) 30 sec.
Reflow profile

9. 2.High Temperature Storage Test (JESD22-A103)
duration: 42 days (1,000 h)
Qual. (JESD47) and RA monitor typically require a
duration of 1,000 hours per condition B.
Considerations: Melting point. (especially metals, e.g.
solder. degradation includes metallurgical interface). 2.
Package degradation (e.g. glass, polymeric) 3.Moisture
rating (J-STD-020) 4.Temperature limitation of Silicon
device 5. Test condition (temperature and time) coverage

10. 3.Thermal Shock (JESD22-A106B)
The total transfer time from hot to cold or from cold
to hot shall not exceed 20 seconds. test condition
can be (-)40℃(5min) ~ (+)85 ℃(5min), 15/30/75
cycles. For Air, can be (-)40℃ (10min) ~ (+)85
℃(10min), 300/500/1,000 cycles.

11. 4.Temperature Cycling (JESD22-A104E)
duration: 21 days (1,000 cycles at 0.5h/cycle)
Test Conditions that exceed 125 °C for
Ts (max) are not recommended to
Pb/Sn solder compositions due to
potential dynamic recrystallization.
For solder interconnections, cycle times
less than 30 minutes are not recommended.
Consider solder fatigue, avoid transient
thermal gradients. Typically <15 °C/min
(prefer 10 °C -14 °C /min)

12. 5.Accelerated Moisture Resistance - Unbiased
HAST (JESD22-A118)
It typically generates the same failure mechanisms as
those in an unbiased "85°C/85%RH" Steady State
Humidity Life Test.
Non-condensing environment avoids failures, e.g., pin-
to-pin leakage or lead corrosion.
Bias is not applied to ensure the failure
mechanisms(e.g. galvanic corrosion) can be uncovered.
Qual. (JESD47) typically require:

13. 6.Steady State Temperature Humidity Bias Life
Test (JESD22-A101C)
Continuous bias: The dc bias shall be
applied continuously.
It’s more severe than cycled bias
when the die temperature Tdie is ≤ 10
°C higher than the Tja chamber
ambient temperature. Or if the Tdie is
not known, when the heat dissipation
of the DUT is < 200 mW.
If the heat dissipation of the DUT
>200 mW, then the Tdie should be
calculated.
NOTE 4 Typically 1000(-24,+168)
Cycled bias: The dc voltage should be
periodically interrupted.
It’s more severe than continuous bias
If ΔTja >10 °C. Cycled bias permits
moisture collection on the die during
the off periods when device power
dissipation does not occur.
Cycling the DUT bias with 1 hour on
and 1 hour off is optimal for most
plastic-encapsulated microcircuits.

14. IMD qualityDevice character Metal qualityGox quality
HCI Vt stable TDDB EM
Life Test PackageRobustness Test
HTOL/LTOL PC/MSL
THB
HAST
TCT HTSL
HBM LU
SM
Idsat, Vt,device
parameter shift
Oxide leakage
current
Open or short
Gate oxide
breakdown, junction
or metal burn out
Crack, void, corrosion,
delamination
DD TDDB
leakage
current
Function fail,
relevant to device
CDM
What are the failures in each reliability test

15. SM physics
drainsource
sio2
gate
Vg
Vs Vd
drainsource
sio2
gate
Vg
Vs Vd
bulk
EM, SM, BEOL TDDB
GOI (DD, TDDB)
HCI, Vt stability
gate
sio2
+N +N
Vd>VdsatVs=0
e-
Hole+
e-
E
Isub
ii
HCI physics
before stress
DEPLETION
(- cathode)
ACCUMULATION
(+ anode)
after stress
apply stress current
what kind of failure mechanism occurs in each stress test

16. http://www.slideshare.net/CHShen/