Focus of this work is a hybrid approach to improve traditional library characterization performance. Traditional circuit simulation for dynamic power characterization, Contributor based approach for leakage characterization

1. A Hybrid Approach to Standard Cell Power
Characterization based on PVT Independent
Contributor Modeling for use in Traditional
Power Analysis Flows
Nagu Dhanwada, Arun Joseph, Spandana Rachamalla, William Dungan,
Arya Madhusoodanan, Suriya Skariah, Karl Moody, David Kadzov
IBM Systems Group

2. Motivation: Library Characterization in a Traditional
Power Analysis Flow
Library
Characterization
Corner 1 ………. Corner N
Power Model 1
Power Model 2
Power Model N
Corner N + 1
(P. V. T)
Workload
Analysis Results
@ Corner N + 1,
Workload 1
Chip Level
Power Analysis
Corner 1 ……. Corner N
Workload 1….Workload N
Input to Wafer Test,
System Planning,
Power Sorting and
Binning
Cell
Library IP Block
Power Analysis
Interpolation
Macro/IP Block
Chip
Huge characterization effort: MaintainingHuge characterization effort: Maintaining
libraries, Memory image sizelibraries, Memory image size
Cell characterizationCell characterization
5 corners x 5 voltages x 5 temperatures5 corners x 5 voltages x 5 temperatures
= 125X increase in effort and file sizes= 125X increase in effort and file sizes

3. Main Idea
 Contributor modeling approach enables significant efficiency
improvements to power analysis flows,
 Adoption of this approach needs
- Tools for contributor model generation
- Power analysis tool enhancements to understand contributor models
 Contributor based modeling can be used even within a
traditional power analysis framework to significantly improve
library characterization times.
 Focus of this work is a hybrid approach to improve traditional
library characterization performance.
- Traditional circuit simulation for dynamic power characterization,
- Contributor based approach for leakage characterization

4. 4
Main Idea: Hybrid Approach using Contributor based Models
Logical Analysis
Characterization
PVT
Specialization
(Leakage)
Circuit Simulation
Characterization
(Dynamic)
Circuit model-based power
contributor evaluation
during analysis
PVT specific design
analysis
Contributor based Power Analysis flow
Conventional PVT Specific Power Analysis flow
PVT Specific
Model
(.lib)
Power Contributor
Model
Cell
schematic
Leak Sim
Hybrid Approach for Library Characterization
 Contributors to power
- are separable: Capacitive switching,
Leakage (gate and channel), and
Shoot-through/Short-Circuit/Direct-Path current
- can be summed,
- behave the same in different cells.
 Use these characteristics:
- Don’t put power in a power model
Instead, list the power contributors (per condition / event),
- Don’t add up power directly in a power tool
Instead add up “compatible” instances of contributors.
 What are power contributors?
- An encapsulation of the non-linear behavior we want to model,
- Current approach: A transistor stack with applied voltages.
 Circuit Simulation Framework calls the circuit simulator and
the PVT specialization step for contributor evaluation
 PVT Specialization
- Evaluation of the Contributor Model using information present in
the contributor model (powerpins, leaking width)
- Uses C callable Leakage equations to evaluate contributors
 Gathers the results from both the above steps to write out a
PVT specific .lib model.

5. Logical Analysis Characterization: Standard Cell
Power Contributor Model Generation Overview
Extracted Netlist of Standard Cell
Flattening of Netlist
Estimating Logic
Expression of Nets
in Design
Logic Simulation
Toggle count
computation
Computation of
Leakage Duty Cycle
from Toggle Counts
Power Contributor Model for Leakage
<tx_leakage>
<rail>
<sink>gnd</sink>
<source>vdd</source>
</rail>
<lk_type>gate_on</lk_type>
<device_type>HVT_NFET</device_type>
<width>1234</width>
<length>1</length>
<count>45</count>
</tx_leakage>
<tx_leakage>
<rail>
<sink>gnd</sink>
<source>vdd</source>
</rail>
<lk_type>gate_off</lk_type>
<device_type>HVT_NFET</device_type>
<width>1234</width>
<length>1</length>
<count>45</count>
</tx_leakage>
<tx_leakage>
<rail>
<sink>gnd</sink>
<source>vdd</source>
</rail>
<lk_type>channel</lk_type>
<device_type>HVT_NFET</device_type>
<width>1234</width>
<length>1</length>
<count>45</count>
</tx_leakage>
Channel Gate On Gate Off

6. Experimental Results
 Contributor based approach was used for
leakage power characterization of an industry
strength standard cell library used in the
design of next generation server class IBM
microprocessors. Accuracy and Turn Around
Time (TAT) reduction was compared against
the traditional IDDQ based circuit simulation
approach.
 Summary of the comparison for a single
corner, for 13 unique cells varying complexity,
and representative of the entire library
demonstrates a TAT reduction of 4x-215641x
with an error margin of 0.2-3.5%.
 Similar accuracy and TAT benefits were
observed across a range of process, voltage
and temperature corners. For simpler libraries
this translated to ~40x and ~100x of TAT
reduction for complex libraries
 For multi-PVT corner cell characterization this
can be much higher, depending on the
number of parallel compute resources. Chart
shows results for a library of size 1200 cells. P
indicates the number of processors available
for executing the characterization in parallel.
Cell No of States
TAT reduction
ratio (x) Error %
Cell1 2 4 0.4
Cell2 4 4 0.2
Cell3 4 5 0.3
Cell4 4 14 1.3
Cell5 8 20 2.8
Cell7 16 67 3.4
Cell8 16 69 0.7
Cell9 32 145 0.8
Cell10 64 305 1.1
Cell11 128 640 0.9
Cell12 256 1338 1.4
Cell13 65536 215641 3.5

7. Experimental Results
 Contributor based approach was used for
leakage power characterization of an industry
strength standard cell library used in the
design of next generation server class IBM
microprocessors. Accuracy and Turn Around
Time (TAT) reduction was compared against
the traditional IDDQ based circuit simulation
approach.
 Summary of the comparison for a single
corner, for 13 unique cells varying complexity,
and representative of the entire library
demonstrates a TAT reduction of 4x-215641x
with an error margin of 0.2-3.5%.
 Similar accuracy and TAT benefits were
observed across a range of process, voltage
and temperature corners. For simpler libraries
this translated to ~40x and ~100x of TAT
reduction for complex libraries
 For multi-PVT corner cell characterization this
can be much higher, depending on the
number of parallel compute resources. Chart
shows results for a library of size 1200 cells. P
indicates the number of processors available
for executing the characterization in parallel.
Cell No of States
TAT reduction
ratio (x) Error %
Cell1 2 4 0.4
Cell2 4 4 0.2
Cell3 4 5 0.3
Cell4 4 14 1.3
Cell5 8 20 2.8
Cell7 16 67 3.4
Cell8 16 69 0.7
Cell9 32 145 0.8
Cell10 64 305 1.1
Cell11 128 640 0.9
Cell12 256 1338 1.4
Cell13 65536 215641 3.5