SlideShare a Scribd company logo
1 of 24
E0 284: Digital VLSI Circuits
Project: Title Name
Author
Program (Micro/ESE – please expand it)
Indian Institute of Science (IISc), Bangalore
1
Introduction
2
• Problem Statement
• Dataset description
• NOTE: Keep it to 1 slide.
Network Description
3
• Network architecture [feed-forward, fully connected]
• Network parameters - Number of Inputs, outputs, number of neurons in
hidden layer, activation function for hidden layer, output format
• NOTE: Keep it to 1 slide.
Software Implementation
4
• Tasks you performed on MATLAB.
• Highlight any optimizations you performed on given code.
• Fixed point design approach:
• Bit widths allocated for integer and fraction part.
• Total memory needed for weights and biases (in bits).
• Size of multiplier needed (Ex: 8 bit x 8 bit)
• Scripting to get HW compatible data.
• NOTE: Do not add any accuracy results here, there is a section for that
later.
LFSR Implementation
5
• Algorithm used to implement LFSR in Verilog/MATLAB.
• Block diagram of LFSR.
Hardware Specifications
6
• Frequency of operation
• Latency – For 1 input image, measure the total cycles needed to complete
the processing – from the clock cycle on which 1st part of input data is sent
to design, till the cycle when output calculation is done and output can be
read from design.
• Initiation interval – Measure the minimum interval (in clock cycles)
between 2 successive images being sent to HW such that they can be
correctly recognized.
• I/Os of your design in tabular form – with bit widths, direction, and
description of the signals.
Hardware Architecture
7
• Overall Block diagram of your design – showing all main sub-modules and
data paths between them, and appropriate info (bit widths, signal names).
• Describe in 1 line what each block does – Describe how inputs get
processed to outputs/ what operation that block performs.
Control FSM
8
• FSM diagram
• Explain the control path very briefly – how many cycles does each state of
the fsm take
Hardware Schematic
9
• Picture of Schematic from Genus (post-synthesis)
HW Simulation
10
• Description of testbench – How you are providing inputs to your design,
how you are checking if output matches the expected value.
• A sample picture of how the HW inputs looks like – if you have stored them
in array, add a picture of part of that text file.
HW Simulation
11
• Hidden Layer Output
• Take a hidden layer neuron, show its output over a series of clock
cycles in pre-synthesis simulation.
• Compare it with MATLAB hidden layer output.
• Justify your floating to fixed point conversion.
Pre-synthesis Simulation Waveform
12
• Add picture of a sample simulation waveform of 1 input image (pre-
synthesis) that has the important signals and captures from the moment
input is provided to design till the output calculation is completed.
• Add some labelling to help us understand what is happening.
Post-synthesis Simulation Waveform
13
• Add picture of a sample simulation waveform 1 input image (post-
synthesis) with the same input as earlier (pre-synth) picture for
comparison. What is your conclusion from the 2 waveforms.
Accuracy Results
14
• Software Accuracy:
• Train data:
• Testing with floating point weights:
• Test data with fixed point weights:
• Accuracy on HW:
• Pre-synthesis: (10 images)
• Post-synthesis: (same 10 images)
• If there is an accuracy drop, why has it happened?
• NOTE: Do not change this slide
Synthesis Reports
15
• QOR and Power Reports from Synthesis.
LEC Report
16
• Picture of LEC report, and your conclusion from it.
Placement
17
• Picture of Placed Design
Routing
18
• Picture of Routed Design
Post-Routing Reports
19
• Setup and Hold Reports post-route
• Power report
• Geometry and Connectivity reports
Design Highlights
20
• Describe key features/optimizations that you have done that can make
your design stand out w.r.t. your peers.
GDS
21
• Picture of successful GDS streamout from the terminal.
Conclusions
22
• Number of neurons in hidden layer =
• Accuracy on synthesized HW =
• Clock Frequency =
• Latency =
• Initiation Interval =
• Total Area =
• Total Power (post-routing) =
• Setup TNS and WNS (post-routing) = … and ….
• Hold TNS and WNS (post-routing) = … and …
• NOTE: Keep the format given here. Only fill the values
Learning Outcomes
23
• What did you learn from this project?
• NOTE: Keep it to 1 slide.
24
Thank You

More Related Content

Similar to DVLSI_project_presentation_template.pptx

Design and implementation of complex floating point processor using fpga
Design and implementation of complex floating point processor using fpgaDesign and implementation of complex floating point processor using fpga
Design and implementation of complex floating point processor using fpgaVLSICS Design
 
Alex Smola, Professor in the Machine Learning Department, Carnegie Mellon Uni...
Alex Smola, Professor in the Machine Learning Department, Carnegie Mellon Uni...Alex Smola, Professor in the Machine Learning Department, Carnegie Mellon Uni...
Alex Smola, Professor in the Machine Learning Department, Carnegie Mellon Uni...MLconf
 
Dot matrix display design using fpga
Dot matrix display design using fpgaDot matrix display design using fpga
Dot matrix display design using fpgaHossam Hassan
 
VLSI design Dr B.jagadeesh UNIT-5.pptx
VLSI design Dr B.jagadeesh   UNIT-5.pptxVLSI design Dr B.jagadeesh   UNIT-5.pptx
VLSI design Dr B.jagadeesh UNIT-5.pptxjagadeesh276791
 
Siemens s7 300 programming
Siemens s7 300 programming Siemens s7 300 programming
Siemens s7 300 programming satyajit patra
 
Summary Of Academic Projects
Summary Of Academic ProjectsSummary Of Academic Projects
Summary Of Academic Projectsawan2008
 
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_ArchitectureARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_ArchitectureRaahul Raghavan
 
Sys cat i181e-en-07+sysmac studio
Sys cat i181e-en-07+sysmac studioSys cat i181e-en-07+sysmac studio
Sys cat i181e-en-07+sysmac studioMaulana Kharis
 
System on Chip Design and Modelling Dr. David J Greaves
System on Chip Design and Modelling   Dr. David J GreavesSystem on Chip Design and Modelling   Dr. David J Greaves
System on Chip Design and Modelling Dr. David J GreavesSatya Harish
 
Introduction to Chainer
Introduction to ChainerIntroduction to Chainer
Introduction to ChainerSeiya Tokui
 
Performance Benchmarking of the R Programming Environment on the Stampede 1.5...
Performance Benchmarking of the R Programming Environment on the Stampede 1.5...Performance Benchmarking of the R Programming Environment on the Stampede 1.5...
Performance Benchmarking of the R Programming Environment on the Stampede 1.5...James McCombs
 
SOC Application Studies: Image Compression
SOC Application Studies: Image CompressionSOC Application Studies: Image Compression
SOC Application Studies: Image CompressionA B Shinde
 
Project Slides for Website 2020-22.pptx
Project Slides for Website 2020-22.pptxProject Slides for Website 2020-22.pptx
Project Slides for Website 2020-22.pptxAkshitAgiwal1
 
Energy efficient AI workload partitioning on multi-core systems
Energy efficient AI workload partitioning on multi-core systemsEnergy efficient AI workload partitioning on multi-core systems
Energy efficient AI workload partitioning on multi-core systemsDeepak Shankar
 
Lecture 16 RC Architecture Types & FPGA Interns Lecturer.pptx
Lecture 16 RC Architecture Types & FPGA Interns Lecturer.pptxLecture 16 RC Architecture Types & FPGA Interns Lecturer.pptx
Lecture 16 RC Architecture Types & FPGA Interns Lecturer.pptxwafawafa52
 

Similar to DVLSI_project_presentation_template.pptx (20)

Design and implementation of complex floating point processor using fpga
Design and implementation of complex floating point processor using fpgaDesign and implementation of complex floating point processor using fpga
Design and implementation of complex floating point processor using fpga
 
Alex Smola, Professor in the Machine Learning Department, Carnegie Mellon Uni...
Alex Smola, Professor in the Machine Learning Department, Carnegie Mellon Uni...Alex Smola, Professor in the Machine Learning Department, Carnegie Mellon Uni...
Alex Smola, Professor in the Machine Learning Department, Carnegie Mellon Uni...
 
Lvs
LvsLvs
Lvs
 
Dot matrix display design using fpga
Dot matrix display design using fpgaDot matrix display design using fpga
Dot matrix display design using fpga
 
VLSI design Dr B.jagadeesh UNIT-5.pptx
VLSI design Dr B.jagadeesh   UNIT-5.pptxVLSI design Dr B.jagadeesh   UNIT-5.pptx
VLSI design Dr B.jagadeesh UNIT-5.pptx
 
Sathya Final review
Sathya Final reviewSathya Final review
Sathya Final review
 
Siemens s7 300 programming
Siemens s7 300 programming Siemens s7 300 programming
Siemens s7 300 programming
 
5-3.pptx
5-3.pptx5-3.pptx
5-3.pptx
 
Summary Of Academic Projects
Summary Of Academic ProjectsSummary Of Academic Projects
Summary Of Academic Projects
 
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_ArchitectureARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
ARM® Cortex™ M Bootup_CMSIS_Part_3_3_Debug_Architecture
 
VLSI design flow.pptx
VLSI design flow.pptxVLSI design flow.pptx
VLSI design flow.pptx
 
Sys cat i181e-en-07+sysmac studio
Sys cat i181e-en-07+sysmac studioSys cat i181e-en-07+sysmac studio
Sys cat i181e-en-07+sysmac studio
 
System on Chip Design and Modelling Dr. David J Greaves
System on Chip Design and Modelling   Dr. David J GreavesSystem on Chip Design and Modelling   Dr. David J Greaves
System on Chip Design and Modelling Dr. David J Greaves
 
Introduction to Chainer
Introduction to ChainerIntroduction to Chainer
Introduction to Chainer
 
Performance Benchmarking of the R Programming Environment on the Stampede 1.5...
Performance Benchmarking of the R Programming Environment on the Stampede 1.5...Performance Benchmarking of the R Programming Environment on the Stampede 1.5...
Performance Benchmarking of the R Programming Environment on the Stampede 1.5...
 
SOC Application Studies: Image Compression
SOC Application Studies: Image CompressionSOC Application Studies: Image Compression
SOC Application Studies: Image Compression
 
Project Slides for Website 2020-22.pptx
Project Slides for Website 2020-22.pptxProject Slides for Website 2020-22.pptx
Project Slides for Website 2020-22.pptx
 
Energy efficient AI workload partitioning on multi-core systems
Energy efficient AI workload partitioning on multi-core systemsEnergy efficient AI workload partitioning on multi-core systems
Energy efficient AI workload partitioning on multi-core systems
 
Chapter1.slides
Chapter1.slidesChapter1.slides
Chapter1.slides
 
Lecture 16 RC Architecture Types & FPGA Interns Lecturer.pptx
Lecture 16 RC Architecture Types & FPGA Interns Lecturer.pptxLecture 16 RC Architecture Types & FPGA Interns Lecturer.pptx
Lecture 16 RC Architecture Types & FPGA Interns Lecturer.pptx
 

Recently uploaded

Moment Distribution Method For Btech Civil
Moment Distribution Method For Btech CivilMoment Distribution Method For Btech Civil
Moment Distribution Method For Btech CivilVinayVitekari
 
AIRCANVAS[1].pdf mini project for btech students
AIRCANVAS[1].pdf mini project for btech studentsAIRCANVAS[1].pdf mini project for btech students
AIRCANVAS[1].pdf mini project for btech studentsvanyagupta248
 
HOA1&2 - Module 3 - PREHISTORCI ARCHITECTURE OF KERALA.pptx
HOA1&2 - Module 3 - PREHISTORCI ARCHITECTURE OF KERALA.pptxHOA1&2 - Module 3 - PREHISTORCI ARCHITECTURE OF KERALA.pptx
HOA1&2 - Module 3 - PREHISTORCI ARCHITECTURE OF KERALA.pptxSCMS School of Architecture
 
Work-Permit-Receiver-in-Saudi-Aramco.pptx
Work-Permit-Receiver-in-Saudi-Aramco.pptxWork-Permit-Receiver-in-Saudi-Aramco.pptx
Work-Permit-Receiver-in-Saudi-Aramco.pptxJuliansyahHarahap1
 
Verification of thevenin's theorem for BEEE Lab (1).pptx
Verification of thevenin's theorem for BEEE Lab (1).pptxVerification of thevenin's theorem for BEEE Lab (1).pptx
Verification of thevenin's theorem for BEEE Lab (1).pptxchumtiyababu
 
NO1 Top No1 Amil Baba In Azad Kashmir, Kashmir Black Magic Specialist Expert ...
NO1 Top No1 Amil Baba In Azad Kashmir, Kashmir Black Magic Specialist Expert ...NO1 Top No1 Amil Baba In Azad Kashmir, Kashmir Black Magic Specialist Expert ...
NO1 Top No1 Amil Baba In Azad Kashmir, Kashmir Black Magic Specialist Expert ...Amil baba
 
A CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptx
A CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptxA CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptx
A CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptxmaisarahman1
 
Bhubaneswar🌹Call Girls Bhubaneswar ❤Komal 9777949614 💟 Full Trusted CALL GIRL...
Bhubaneswar🌹Call Girls Bhubaneswar ❤Komal 9777949614 💟 Full Trusted CALL GIRL...Bhubaneswar🌹Call Girls Bhubaneswar ❤Komal 9777949614 💟 Full Trusted CALL GIRL...
Bhubaneswar🌹Call Girls Bhubaneswar ❤Komal 9777949614 💟 Full Trusted CALL GIRL...Call Girls Mumbai
 
School management system project Report.pdf
School management system project Report.pdfSchool management system project Report.pdf
School management system project Report.pdfKamal Acharya
 
Unit 4_Part 1 CSE2001 Exception Handling and Function Template and Class Temp...
Unit 4_Part 1 CSE2001 Exception Handling and Function Template and Class Temp...Unit 4_Part 1 CSE2001 Exception Handling and Function Template and Class Temp...
Unit 4_Part 1 CSE2001 Exception Handling and Function Template and Class Temp...drmkjayanthikannan
 
Generative AI or GenAI technology based PPT
Generative AI or GenAI technology based PPTGenerative AI or GenAI technology based PPT
Generative AI or GenAI technology based PPTbhaskargani46
 
HAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKAR
HAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKARHAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKAR
HAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKARKOUSTAV SARKAR
 
Employee leave management system project.
Employee leave management system project.Employee leave management system project.
Employee leave management system project.Kamal Acharya
 
DC MACHINE-Motoring and generation, Armature circuit equation
DC MACHINE-Motoring and generation, Armature circuit equationDC MACHINE-Motoring and generation, Armature circuit equation
DC MACHINE-Motoring and generation, Armature circuit equationBhangaleSonal
 
COST-EFFETIVE and Energy Efficient BUILDINGS ptx
COST-EFFETIVE  and Energy Efficient BUILDINGS ptxCOST-EFFETIVE  and Energy Efficient BUILDINGS ptx
COST-EFFETIVE and Energy Efficient BUILDINGS ptxJIT KUMAR GUPTA
 
Online food ordering system project report.pdf
Online food ordering system project report.pdfOnline food ordering system project report.pdf
Online food ordering system project report.pdfKamal Acharya
 
Block diagram reduction techniques in control systems.ppt
Block diagram reduction techniques in control systems.pptBlock diagram reduction techniques in control systems.ppt
Block diagram reduction techniques in control systems.pptNANDHAKUMARA10
 

Recently uploaded (20)

Moment Distribution Method For Btech Civil
Moment Distribution Method For Btech CivilMoment Distribution Method For Btech Civil
Moment Distribution Method For Btech Civil
 
AIRCANVAS[1].pdf mini project for btech students
AIRCANVAS[1].pdf mini project for btech studentsAIRCANVAS[1].pdf mini project for btech students
AIRCANVAS[1].pdf mini project for btech students
 
HOA1&2 - Module 3 - PREHISTORCI ARCHITECTURE OF KERALA.pptx
HOA1&2 - Module 3 - PREHISTORCI ARCHITECTURE OF KERALA.pptxHOA1&2 - Module 3 - PREHISTORCI ARCHITECTURE OF KERALA.pptx
HOA1&2 - Module 3 - PREHISTORCI ARCHITECTURE OF KERALA.pptx
 
Work-Permit-Receiver-in-Saudi-Aramco.pptx
Work-Permit-Receiver-in-Saudi-Aramco.pptxWork-Permit-Receiver-in-Saudi-Aramco.pptx
Work-Permit-Receiver-in-Saudi-Aramco.pptx
 
Call Girls in South Ex (delhi) call me [🔝9953056974🔝] escort service 24X7
Call Girls in South Ex (delhi) call me [🔝9953056974🔝] escort service 24X7Call Girls in South Ex (delhi) call me [🔝9953056974🔝] escort service 24X7
Call Girls in South Ex (delhi) call me [🔝9953056974🔝] escort service 24X7
 
Verification of thevenin's theorem for BEEE Lab (1).pptx
Verification of thevenin's theorem for BEEE Lab (1).pptxVerification of thevenin's theorem for BEEE Lab (1).pptx
Verification of thevenin's theorem for BEEE Lab (1).pptx
 
NO1 Top No1 Amil Baba In Azad Kashmir, Kashmir Black Magic Specialist Expert ...
NO1 Top No1 Amil Baba In Azad Kashmir, Kashmir Black Magic Specialist Expert ...NO1 Top No1 Amil Baba In Azad Kashmir, Kashmir Black Magic Specialist Expert ...
NO1 Top No1 Amil Baba In Azad Kashmir, Kashmir Black Magic Specialist Expert ...
 
Cara Menggugurkan Sperma Yang Masuk Rahim Biyar Tidak Hamil
Cara Menggugurkan Sperma Yang Masuk Rahim Biyar Tidak HamilCara Menggugurkan Sperma Yang Masuk Rahim Biyar Tidak Hamil
Cara Menggugurkan Sperma Yang Masuk Rahim Biyar Tidak Hamil
 
A CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptx
A CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptxA CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptx
A CASE STUDY ON CERAMIC INDUSTRY OF BANGLADESH.pptx
 
Bhubaneswar🌹Call Girls Bhubaneswar ❤Komal 9777949614 💟 Full Trusted CALL GIRL...
Bhubaneswar🌹Call Girls Bhubaneswar ❤Komal 9777949614 💟 Full Trusted CALL GIRL...Bhubaneswar🌹Call Girls Bhubaneswar ❤Komal 9777949614 💟 Full Trusted CALL GIRL...
Bhubaneswar🌹Call Girls Bhubaneswar ❤Komal 9777949614 💟 Full Trusted CALL GIRL...
 
FEA Based Level 3 Assessment of Deformed Tanks with Fluid Induced Loads
FEA Based Level 3 Assessment of Deformed Tanks with Fluid Induced LoadsFEA Based Level 3 Assessment of Deformed Tanks with Fluid Induced Loads
FEA Based Level 3 Assessment of Deformed Tanks with Fluid Induced Loads
 
School management system project Report.pdf
School management system project Report.pdfSchool management system project Report.pdf
School management system project Report.pdf
 
Unit 4_Part 1 CSE2001 Exception Handling and Function Template and Class Temp...
Unit 4_Part 1 CSE2001 Exception Handling and Function Template and Class Temp...Unit 4_Part 1 CSE2001 Exception Handling and Function Template and Class Temp...
Unit 4_Part 1 CSE2001 Exception Handling and Function Template and Class Temp...
 
Generative AI or GenAI technology based PPT
Generative AI or GenAI technology based PPTGenerative AI or GenAI technology based PPT
Generative AI or GenAI technology based PPT
 
HAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKAR
HAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKARHAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKAR
HAND TOOLS USED AT ELECTRONICS WORK PRESENTED BY KOUSTAV SARKAR
 
Employee leave management system project.
Employee leave management system project.Employee leave management system project.
Employee leave management system project.
 
DC MACHINE-Motoring and generation, Armature circuit equation
DC MACHINE-Motoring and generation, Armature circuit equationDC MACHINE-Motoring and generation, Armature circuit equation
DC MACHINE-Motoring and generation, Armature circuit equation
 
COST-EFFETIVE and Energy Efficient BUILDINGS ptx
COST-EFFETIVE  and Energy Efficient BUILDINGS ptxCOST-EFFETIVE  and Energy Efficient BUILDINGS ptx
COST-EFFETIVE and Energy Efficient BUILDINGS ptx
 
Online food ordering system project report.pdf
Online food ordering system project report.pdfOnline food ordering system project report.pdf
Online food ordering system project report.pdf
 
Block diagram reduction techniques in control systems.ppt
Block diagram reduction techniques in control systems.pptBlock diagram reduction techniques in control systems.ppt
Block diagram reduction techniques in control systems.ppt
 

DVLSI_project_presentation_template.pptx

  • 1. E0 284: Digital VLSI Circuits Project: Title Name Author Program (Micro/ESE – please expand it) Indian Institute of Science (IISc), Bangalore 1
  • 2. Introduction 2 • Problem Statement • Dataset description • NOTE: Keep it to 1 slide.
  • 3. Network Description 3 • Network architecture [feed-forward, fully connected] • Network parameters - Number of Inputs, outputs, number of neurons in hidden layer, activation function for hidden layer, output format • NOTE: Keep it to 1 slide.
  • 4. Software Implementation 4 • Tasks you performed on MATLAB. • Highlight any optimizations you performed on given code. • Fixed point design approach: • Bit widths allocated for integer and fraction part. • Total memory needed for weights and biases (in bits). • Size of multiplier needed (Ex: 8 bit x 8 bit) • Scripting to get HW compatible data. • NOTE: Do not add any accuracy results here, there is a section for that later.
  • 5. LFSR Implementation 5 • Algorithm used to implement LFSR in Verilog/MATLAB. • Block diagram of LFSR.
  • 6. Hardware Specifications 6 • Frequency of operation • Latency – For 1 input image, measure the total cycles needed to complete the processing – from the clock cycle on which 1st part of input data is sent to design, till the cycle when output calculation is done and output can be read from design. • Initiation interval – Measure the minimum interval (in clock cycles) between 2 successive images being sent to HW such that they can be correctly recognized. • I/Os of your design in tabular form – with bit widths, direction, and description of the signals.
  • 7. Hardware Architecture 7 • Overall Block diagram of your design – showing all main sub-modules and data paths between them, and appropriate info (bit widths, signal names). • Describe in 1 line what each block does – Describe how inputs get processed to outputs/ what operation that block performs.
  • 8. Control FSM 8 • FSM diagram • Explain the control path very briefly – how many cycles does each state of the fsm take
  • 9. Hardware Schematic 9 • Picture of Schematic from Genus (post-synthesis)
  • 10. HW Simulation 10 • Description of testbench – How you are providing inputs to your design, how you are checking if output matches the expected value. • A sample picture of how the HW inputs looks like – if you have stored them in array, add a picture of part of that text file.
  • 11. HW Simulation 11 • Hidden Layer Output • Take a hidden layer neuron, show its output over a series of clock cycles in pre-synthesis simulation. • Compare it with MATLAB hidden layer output. • Justify your floating to fixed point conversion.
  • 12. Pre-synthesis Simulation Waveform 12 • Add picture of a sample simulation waveform of 1 input image (pre- synthesis) that has the important signals and captures from the moment input is provided to design till the output calculation is completed. • Add some labelling to help us understand what is happening.
  • 13. Post-synthesis Simulation Waveform 13 • Add picture of a sample simulation waveform 1 input image (post- synthesis) with the same input as earlier (pre-synth) picture for comparison. What is your conclusion from the 2 waveforms.
  • 14. Accuracy Results 14 • Software Accuracy: • Train data: • Testing with floating point weights: • Test data with fixed point weights: • Accuracy on HW: • Pre-synthesis: (10 images) • Post-synthesis: (same 10 images) • If there is an accuracy drop, why has it happened? • NOTE: Do not change this slide
  • 15. Synthesis Reports 15 • QOR and Power Reports from Synthesis.
  • 16. LEC Report 16 • Picture of LEC report, and your conclusion from it.
  • 18. Routing 18 • Picture of Routed Design
  • 19. Post-Routing Reports 19 • Setup and Hold Reports post-route • Power report • Geometry and Connectivity reports
  • 20. Design Highlights 20 • Describe key features/optimizations that you have done that can make your design stand out w.r.t. your peers.
  • 21. GDS 21 • Picture of successful GDS streamout from the terminal.
  • 22. Conclusions 22 • Number of neurons in hidden layer = • Accuracy on synthesized HW = • Clock Frequency = • Latency = • Initiation Interval = • Total Area = • Total Power (post-routing) = • Setup TNS and WNS (post-routing) = … and …. • Hold TNS and WNS (post-routing) = … and … • NOTE: Keep the format given here. Only fill the values
  • 23. Learning Outcomes 23 • What did you learn from this project? • NOTE: Keep it to 1 slide.