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Low Power Design of CMOS Inverters

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Varun Bansal
Varun Bansal

The document discusses the CMOS inverter, including its basic structure and operation, transient response characteristics, voltage transfer curve, propagation delay, and design considerations for improving performance such as minimizing delay. It provides analysis of how varying factors like transistor widths, supply voltage, and load capacitance affect the inverter's switching threshold, rise/fall times, and propagation delay. The goal of the analysis is to determine the optimal transistor width ratios and device parameters needed to design a high-performance symmetric CMOS inverter with minimum total propagation delay.

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Low Power VLSI Design The Inverter Dr Anu Mehra
The CMOS Inverter: A First Glance V in V out C L V DD
CMOS Inverter Polysilicon In Out GND PMOS 2  Metal 1 NMOS Contacts N Well V DD
Two Inverters Connect in Metal Share power and ground Abut cells
CMOS Inverter First-Order DC Analysis V OL = 0 V OH = V DD V M = f(R n , R p ) V DD V DD V in 5 V DD V in 5 0 V out V out R n R p
CMOS Inverter: Transient Response V out V out R n R p V DD V DD V in 5 V DD V in 5 0 (a) Low-to-high (b) High-to-low C L C L t pHL = f(R on .C L ) = 0.69 R on C L
Voltage Transfer Characteristic
PMOS Load Lines V DSp I Dp V GSp =-2.5 V GSp =-1 V DSp I Dn V in =0 V in =1.5 V out I Dn V in =0 V in =1.5 V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp V out I Dn V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp
CMOS Inverter Load Characteristics
CMOS Inverter VTC
Switching Threshold as a function of Transistor Ratio 10 0 10 1 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 M V (V) W p /W n
Determining V IH and V IL A simplified approach V OH V OL V in V out V M V IL V IH
Inverter Gain
Simulated VTC
Propagation Delay
CMOS Inverter Propagation Delay Approach 1 ∆ t=C L ∆V/I DS Iav is average charging current and ∆V is V DD /2 V DD V out V in = V DD C L I av t pHL = C L V swing /2 I av
CMOS Inverter Propagation Delay Approach 2
Transient Response t p = 0.69 C L (R eqn +R eqp )/2 t pLH t pHL
Delay as a function of V DD
The Transistor as a Switch
Design for Performance (minimum delay) ,[object Object],[object Object],[object Object],[object Object]
To MAKE A SYMMETRIC INVERTER tpHL=tpLH ,[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object]
To minimize total delay ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
[object Object],[object Object],[object Object]
[object Object]
NMOS/PMOS ratio tpLH tpHL tp  = W p /W n

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Low Power Design of CMOS Inverters